Searched refs:BIT_2 (Results 1 – 6 of 6) sorted by relevance
189 #define BIT_2 (1 << 2) macro307 #define PCI_REV_DESC BIT_2 /* Reverse Desc. Bytes */338 #define PCI_ASPM_A1_MODE_SELECT BIT_2 /* A1 Mode Select (A1 only) */371 #define PCI_GAT_LOADER_FINISHED BIT_2 /* EPROM Loader Finished */401 #define PEX_DC_EN_FAT_ER_RP BIT_2 /* Enable Fatal Error Reporting */801 #define CS_MRST_SET BIT_2 /* Set Master Reset */814 #define PC_VAUX_OFF BIT_2 /* Switch VAUX Off */844 #define Y2_IS_CHK_RX1 BIT_2 /* Descriptor error Rx 1 */877 #define Y2_IS_PAR_RX1 BIT_2 /* Parity Error Rx Queue 1 */938 #define Y2_CLK_GAT_LNK1_DIS BIT_2 /* Disable clock gating Link 1 */[all …]
41 #define BIT_2 (0x1 << 2) macro187 #define Q81_CTL_SYSTEM_ENABLE_MDC BIT_2257 #define Q81_CTL_CONFIG_LR BIT_2274 #define Q81_CTL_STATUS_PL0 BIT_2299 #define Q81_CTL_INTRM_LH0 BIT_2472 #define Q81_CTL_RD_MCAST_MATCH BIT_2658 #define Q81_TX_MAC_VLAN_OFF_V BIT_2697 #define Q81_TX_TSO_VLAN_OFF_V BIT_2816 #define Q81_RX_FLAGS0_TE BIT_2
40 #define BIT_2 (0x1 << 2) macro
150 data = (BIT_2|BIT_1|BIT_0); in ql_rdwr_offchip_mem()
2863 WRITE_REG32(ha, Q8_MBOX_INT_ENABLE, BIT_2); in qla_confirm_9kb_enable()