Searched refs:B2_Y2_CLK_GATE (Results 1 – 2 of 2) sorted by relevance
1268 CSR_WRITE_1(sc, B2_Y2_CLK_GATE, val); in msk_phy_power()1336 CSR_WRITE_1(sc, B2_Y2_CLK_GATE, val); in msk_phy_power()1818 if (!(CSR_READ_1(sc, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC)) in mskc_attach()
466 #define B2_Y2_CLK_GATE 0x011d /* 8 bit Clock Gating (Yukon-2) */ macro