| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | ISDOpcodes.h | 63 AssertZext, enumerator
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| H A D | SelectionDAGNodes.h | 735 case ISD::AssertZext:
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | LegalizeTypesGeneric.cpp | 599 Lo = DAG.getNode(ISD::AssertZext, dl, L.getValueType(), L, N->getOperand(1)); in SplitVecRes_AssertZext()
600 Hi = DAG.getNode(ISD::AssertZext, dl, H.getValueType(), H, N->getOperand(1)); in SplitVecRes_AssertZext()
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| H A D | SelectionDAGDumper.cpp | 126 case ISD::AssertZext: return "AssertZext"; in getOperationName()
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| H A D | LegalizeIntegerTypes.cpp | 60 case ISD::AssertZext: Res = PromoteIntRes_AssertZext(N); break; in PromoteIntegerResult()
383 return DAG.getNode(ISD::AssertZext, SDLoc(N), in PromoteIntRes_AssertZext()
882 ? ISD::AssertZext in PromoteIntRes_FP_TO_XINT()
2966 case ISD::AssertZext: ExpandIntRes_AssertZext(N, Lo, Hi); break; in ExpandIntegerResult()
3929 Hi = DAG.getNode(ISD::AssertZext, dl, NVT, Hi, in ExpandIntRes_AssertZext()
3933 Lo = DAG.getNode(ISD::AssertZext, dl, NVT, Lo, DAG.getValueType(EVT)); in ExpandIntRes_AssertZext()
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| H A D | SelectionDAGBuilder.cpp | 947 Parts[i] = DAG.getNode(isSExt ? ISD::AssertSext : ISD::AssertZext, dl, in getCopyFromRegs()
6049 case ISD::AssertZext: in getUnderlyingArgRegs()
10562 SDValue ZExt = DAG.getNode(ISD::AssertZext, SL, Op.getValueType(), Op, in lowerRangeToAssertZExt()
11317 AssertOp = ISD::AssertZext; in LowerCallTo()
11867 AssertOp = ISD::AssertZext; in LowerArguments()
11916 if (Res.getOpcode() == ISD::AssertZext) in LowerArguments()
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| H A D | LegalizeVectorTypes.cpp | 61 case ISD::AssertZext: in ScalarizeVectorResult()
1122 case ISD::AssertZext: SplitVecRes_AssertZext(N, Lo, Hi); break; in SplitVectorResult()
4678 case ISD::AssertZext: Res = WidenVecRes_AssertZext(N); break; in WidenVectorResult()
6057 return DAG.getNode(ISD::AssertZext, SDLoc(N), InOp.getValueType(), InOp, in WidenVecRes_AssertZext()
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| H A D | LegalizeVectorOps.cpp | 895 NewOpc = ISD::AssertZext; in PromoteFP_TO_INT()
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| H A D | SelectionDAGISel.cpp | 3274 case ISD::AssertZext: in SelectCodeCommon()
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| H A D | SelectionDAG.cpp | 4092 case ISD::AssertZext: { in computeKnownBits()
4749 case ISD::AssertZext: in ComputeNumSignBits()
5531 case ISD::AssertZext: in canCreateUndefOrPoison()
7653 case ISD::AssertZext: { in getNode()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonPatterns.td | 804 def AssertZextSD: SDNode<"ISD::AssertZext", SDTAssertZext>;
805 class AssertZext<ValueType T>: PatFrag<(ops node:$A), (AssertZextSD $A, T)>;
832 defm: Cmpb_pat <A4_cmpbeqi, seteq, AssertZext<i8>, IsUGT<8,31>, 255>;
833 defm: CmpbN_pat <A4_cmpbeqi, setne, AssertZext<i8>, IsUGT<8,31>, 255>;
834 defm: Cmpb_pat <A4_cmpbgtui, setugt, AssertZext<i8>, IsUGT<32,31>, 255>;
835 defm: CmpbN_pat <A4_cmpbgtui, setule, AssertZext<i8>, IsUGT<32,31>, 255>;
836 defm: Cmpb_pat <A4_cmphgtui, setugt, AssertZext<i16>, IsUGT<32,31>, 65535>;
837 defm: CmpbN_pat <A4_cmphgtui, setule, AssertZext<i16>, IsUGT<32,31>, 65535>;
838 defm: CmpbND_pat<A4_cmpbgtui, setult, AssertZext<i8>, IsUGT<32,32>, 255>;
839 defm: CmpbND_pat<A4_cmphgtui, setult, AssertZext<i16>, IsUGT<32,32>, 65535>;
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| H A D | HexagonISelDAGToDAG.cpp | 1690 case ISD::AssertZext: in keepsLowBits()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86InstrFragments.td | 715 // be copying from a truncate. AssertSext/AssertZext/AssertAlign aren't saying
725 N->getOpcode() != ISD::AssertZext &&
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| H A D | X86ISelLoweringCall.cpp | 1811 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue, in LowerFormalArguments()
2696 Op == ISD::AssertZext) { in MatchingStackOffset()
2702 if (TruncInput.getOpcode() == ISD::AssertZext && in MatchingStackOffset()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/BPF/ |
| H A D | BPFISelLowering.cpp | 391 ArgValue = DAG.getNode(ISD::AssertZext, DL, RegVT, ArgValue, in LowerFormalArguments()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/MSP430/ |
| H A D | MSP430ISelLowering.cpp | 544 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue, in LowerCCCArguments()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Lanai/ |
| H A D | LanaiISelLowering.cpp | 461 ArgValue = DAG.getNode(ISD::AssertZext, DL, RegVT, ArgValue, in LowerCCCArguments()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/VE/ |
| H A D | VEISelLowering.cpp | 479 Arg = DAG.getNode(ISD::AssertZext, DL, VA.getLocVT(), Arg, in LowerFormalArguments()
817 RV = DAG.getNode(ISD::AssertZext, DL, VA.getLocVT(), RV, in LowerCall()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIISelLowering.cpp | 2133 unsigned Opc = Arg->Flags.isZExt() ? ISD::AssertZext : ISD::AssertSext; in convertArgType()
3161 NewArg = DAG.getNode(ISD::AssertZext, DL, NewArg.getValueType(), NewArg, in LowerFormalArguments()
3200 ISD::AssertZext, DL, VT, Val, in LowerFormalArguments()
3218 Val = DAG.getNode(ISD::AssertZext, DL, VT, Val, DAG.getValueType(ValVT)); in LowerFormalArguments()
3409 Val = DAG.getNode(ISD::AssertZext, DL, VA.getLocVT(), Val, in LowerCallResult()
8269 return DAG.getNode(ISD::AssertZext, SL, MVT::i32, Param, in lowerImplicitZextParam()
8987 return DAG.getNode(ISD::AssertZext, SL, MVT::i32, Val, in lowerWorkitemID()
12313 SDValue Ext = DAG.getNode(ISD::AssertZext, SL, VT, BFE, in performAndCombine()
12710 case ISD::AssertZext: in calculateByteProvider()
12718 Op->getOpcode() == ISD::AssertZext || in calculateByteProvider()
[all …]
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| /freebsd/contrib/llvm-project/llvm/lib/Target/M68k/ |
| H A D | M68kISelLowering.cpp | 314 if (TruncInput.getOpcode() == ISD::AssertZext && in MatchingStackOffset()
965 ArgValue = DAG.getNode(ISD::AssertZext, DL, RegVT, ArgValue, in LowerFormalArguments()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsISelLowering.cpp | 526 ISD::OR, ISD::ADD, ISD::SUB, ISD::AssertZext, ISD::SHL, in MipsTargetLowering()
3726 Val = DAG.getNode(ISD::AssertZext, DL, VA.getLocVT(), Val, in LowerCallResult()
3788 Val = DAG.getNode(ISD::AssertZext, DL, LocVT, Val, DAG.getValueType(ValVT)); in UnpackFromArgumentSlot()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Xtensa/ |
| H A D | XtensaISelLowering.cpp | 478 Opcode = ISD::AssertZext; in LowerFormalArguments()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Sparc/ |
| H A D | SparcISelLowering.cpp | 668 Arg = DAG.getNode(ISD::AssertZext, DL, VA.getLocVT(), Arg, in LowerFormalArguments_64()
1477 RV = DAG.getNode(ISD::AssertZext, DL, VA.getLocVT(), RV, in LowerCall_64()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/ |
| H A D | SystemZISelLowering.cpp | 1813 Value = DAG.getNode(ISD::AssertZext, DL, VA.getLocVT(), Value, in convertLocVTToValVT()
4766 Flag = DAG.getNode(ISD::AssertZext, DL, MVT::i128, Flag, in lowerXALUO()
4867 Flag = DAG.getNode(ISD::AssertZext, DL, MVT::i128, Flag, in lowerUADDSUBO_CARRY()
5209 SDValue OrigVal = DAG.getNode(ISD::AssertZext, DL, WideVT, AtomicOp.getValue(0), in lowerATOMIC_CMP_SWAP()
8237 else if (LHS->getOpcode() == ISD::AssertZext) in combineSTORE()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AVR/ |
| H A D | AVRISelLowering.cpp | 1379 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue, in LowerFormalArguments()
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