| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | ISDOpcodes.h | 62 AssertSext, enumerator
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| H A D | SelectionDAGNodes.h | 734 case ISD::AssertSext:
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86InstrFragments.td | 715 // be copying from a truncate. AssertSext/AssertZext/AssertAlign aren't saying
724 N->getOpcode() != ISD::AssertSext &&
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| H A D | X86ISelLoweringCall.cpp | 1808 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue, in LowerFormalArguments()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAGDumper.cpp | 125 case ISD::AssertSext: return "AssertSext"; in getOperationName()
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| H A D | LegalizeIntegerTypes.cpp | 59 case ISD::AssertSext: Res = PromoteIntRes_AssertSext(N); break; in PromoteIntegerResult()
376 return DAG.getNode(ISD::AssertSext, SDLoc(N), in PromoteIntRes_AssertSext()
883 : ISD::AssertSext, in PromoteIntRes_FP_TO_XINT()
2965 case ISD::AssertSext: ExpandIntRes_AssertSext(N, Lo, Hi); break; in ExpandIntegerResult()
3907 Hi = DAG.getNode(ISD::AssertSext, dl, NVT, Hi, in ExpandIntRes_AssertSext()
3911 Lo = DAG.getNode(ISD::AssertSext, dl, NVT, Lo, DAG.getValueType(EVT)); in ExpandIntRes_AssertSext()
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| H A D | LegalizeVectorOps.cpp | 897 NewOpc = ISD::AssertSext; in PromoteFP_TO_INT()
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| H A D | SelectionDAGBuilder.cpp | 947 Parts[i] = DAG.getNode(isSExt ? ISD::AssertSext : ISD::AssertZext, dl, in getCopyFromRegs()
6050 case ISD::AssertSext: in getUnderlyingArgRegs()
11315 AssertOp = ISD::AssertSext; in LowerCallTo()
11865 AssertOp = ISD::AssertSext; in LowerArguments()
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| H A D | SelectionDAGISel.cpp | 3273 case ISD::AssertSext: in SelectCodeCommon()
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| H A D | SelectionDAG.cpp | 4746 case ISD::AssertSext: in ComputeNumSignBits()
5530 case ISD::AssertSext: in canCreateUndefOrPoison()
7652 case ISD::AssertSext: in getNode()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/BPF/ |
| H A D | BPFISelLowering.cpp | 388 ArgValue = DAG.getNode(ISD::AssertSext, DL, RegVT, ArgValue, in LowerFormalArguments()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelDAGToDAG.cpp | 1643 case ISD::AssertSext: { in DetectUseSxtw()
1689 case ISD::AssertSext: in keepsLowBits()
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| H A D | HexagonISelLowering.cpp | 1146 if (Op.getOpcode() != ISD::AssertSext) in LowerSETCC()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Sparc/ |
| H A D | SparcISelLowering.cpp | 506 Arg = DAG.getNode(ISD::AssertSext, dl, MVT::i32, Arg, in LowerFormalArguments_32()
664 Arg = DAG.getNode(ISD::AssertSext, DL, VA.getLocVT(), Arg, in LowerFormalArguments_64()
1473 RV = DAG.getNode(ISD::AssertSext, DL, VA.getLocVT(), RV, in LowerCall_64()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/MSP430/ |
| H A D | MSP430ISelLowering.cpp | 541 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue, in LowerCCCArguments()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Lanai/ |
| H A D | LanaiISelLowering.cpp | 458 ArgValue = DAG.getNode(ISD::AssertSext, DL, RegVT, ArgValue, in LowerCCCArguments()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/VE/ |
| H A D | VEISelLowering.cpp | 475 Arg = DAG.getNode(ISD::AssertSext, DL, VA.getLocVT(), Arg, in LowerFormalArguments()
813 RV = DAG.getNode(ISD::AssertSext, DL, VA.getLocVT(), RV, in LowerCall()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Xtensa/ |
| H A D | XtensaISelLowering.cpp | 476 Opcode = ISD::AssertSext; in LowerFormalArguments()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsISelLowering.cpp | 3732 Val = DAG.getNode(ISD::AssertSext, DL, VA.getLocVT(), Val, in LowerCallResult()
3783 Val = DAG.getNode(ISD::AssertSext, DL, LocVT, Val, DAG.getValueType(ValVT)); in UnpackFromArgumentSlot()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AVR/ |
| H A D | AVRISelLowering.cpp | 1374 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue, in LowerFormalArguments()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/M68k/ |
| H A D | M68kISelLowering.cpp | 962 ArgValue = DAG.getNode(ISD::AssertSext, DL, RegVT, ArgValue, in LowerFormalArguments()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIISelLowering.cpp | 2133 unsigned Opc = Arg->Flags.isZExt() ? ISD::AssertZext : ISD::AssertSext; in convertArgType()
3214 Val = DAG.getNode(ISD::AssertSext, DL, VT, Val, DAG.getValueType(ValVT)); in LowerFormalArguments()
3414 Val = DAG.getNode(ISD::AssertSext, DL, VA.getLocVT(), Val, in LowerCallResult()
12711 case ISD::AssertSext: { in calculateByteProvider()
12719 Op->getOpcode() == ISD::AssertSext) { in calculateByteProvider()
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| H A D | AMDGPUISelLowering.cpp | 635 ISD::AssertSext, ISD::INTRINSIC_WO_CHAIN}); in AMDGPUTargetLowering()
5482 case ISD::AssertSext: in PerformDAGCombine()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/Target/ |
| H A D | TargetSelectionDAG.td | 884 def assertsext : SDNode<"ISD::AssertSext", SDT_assert>;
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| /freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/ |
| H A D | LoongArchISelLowering.cpp | 2769 if ((Op0.getOpcode() == ISD::AssertSext || in lowerSINT_TO_FP()
4958 case ISD::AssertSext: { in checkValueWidth()
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