| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | ISDOpcodes.h | 61 AssertSext, enumerator
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86InstrFragments.td | 689 // be copying from a truncate. AssertSext/AssertZext/AssertAlign aren't saying
697 N->getOpcode() != ISD::AssertSext &&
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| H A D | X86ISelLoweringCall.cpp | 1777 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue, in LowerFormalArguments()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Xtensa/ |
| H A D | XtensaISelLowering.cpp | 247 Opcode = ISD::AssertSext; in LowerFormalArguments()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAGDumper.cpp | 115 case ISD::AssertSext: return "AssertSext"; in getOperationName()
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| H A D | LegalizeIntegerTypes.cpp | 59 case ISD::AssertSext: Res = PromoteIntRes_AssertSext(N); break; in PromoteIntegerResult()
356 return DAG.getNode(ISD::AssertSext, SDLoc(N), in PromoteIntRes_AssertSext()
861 : ISD::AssertSext, in PromoteIntRes_FP_TO_XINT()
2784 case ISD::AssertSext: ExpandIntRes_AssertSext(N, Lo, Hi); break; in ExpandIntegerResult()
3709 Hi = DAG.getNode(ISD::AssertSext, dl, NVT, Hi, in ExpandIntRes_AssertSext()
3713 Lo = DAG.getNode(ISD::AssertSext, dl, NVT, Lo, DAG.getValueType(EVT)); in ExpandIntRes_AssertSext()
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| H A D | LegalizeVectorOps.cpp | 821 NewOpc = ISD::AssertSext; in PromoteFP_TO_INT()
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| H A D | SelectionDAGBuilder.cpp | 951 Parts[i] = DAG.getNode(isSExt ? ISD::AssertSext : ISD::AssertZext, dl, in getCopyFromRegs()
5958 case ISD::AssertSext: in getUnderlyingArgRegs()
11161 AssertOp = ISD::AssertSext; in LowerCallTo()
11722 AssertOp = ISD::AssertSext; in LowerArguments()
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| H A D | SelectionDAGISel.cpp | 3218 case ISD::AssertSext: in SelectCodeCommon()
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| H A D | SelectionDAG.cpp | 4475 case ISD::AssertSext: in ComputeNumSignBits()
7095 case ISD::AssertSext: in getNode()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/BPF/ |
| H A D | BPFISelLowering.cpp | 372 ArgValue = DAG.getNode(ISD::AssertSext, DL, RegVT, ArgValue, in LowerFormalArguments()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Sparc/ |
| H A D | SparcISelLowering.cpp | 502 Arg = DAG.getNode(ISD::AssertSext, dl, MVT::i32, Arg, in LowerFormalArguments_32()
660 Arg = DAG.getNode(ISD::AssertSext, DL, VA.getLocVT(), Arg, in LowerFormalArguments_64()
1482 RV = DAG.getNode(ISD::AssertSext, DL, VA.getLocVT(), RV, in LowerCall_64()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Lanai/ |
| H A D | LanaiISelLowering.cpp | 468 ArgValue = DAG.getNode(ISD::AssertSext, DL, RegVT, ArgValue, in LowerCCCArguments()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/VE/ |
| H A D | VEISelLowering.cpp | 477 Arg = DAG.getNode(ISD::AssertSext, DL, VA.getLocVT(), Arg, in LowerFormalArguments()
823 RV = DAG.getNode(ISD::AssertSext, DL, VA.getLocVT(), RV, in LowerCall()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/MSP430/ |
| H A D | MSP430ISelLowering.cpp | 662 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue, in LowerCCCArguments()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelDAGToDAG.cpp | 1679 case ISD::AssertSext: in keepsLowBits()
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| H A D | HexagonISelLowering.cpp | 1077 if (Op.getOpcode() != ISD::AssertSext) in LowerSETCC()
1082 // The type that was sign-extended to get the AssertSext must be in LowerSETCC()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsISelLowering.cpp | 3574 Val = DAG.getNode(ISD::AssertSext, DL, VA.getLocVT(), Val, in LowerCallResult()
3625 Val = DAG.getNode(ISD::AssertSext, DL, LocVT, Val, DAG.getValueType(ValVT)); in UnpackFromArgumentSlot()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AVR/ |
| H A D | AVRISelLowering.cpp | 1421 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue, in LowerFormalArguments()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/ |
| H A D | LoongArchISelLowering.cpp | 1622 if ((Op0.getOpcode() == ISD::AssertSext || in lowerSINT_TO_FP()
3463 case ISD::AssertSext: { in checkValueWidth()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIISelLowering.cpp | 2026 unsigned Opc = Arg->Flags.isZExt() ? ISD::AssertZext : ISD::AssertSext; in convertArgType()
3093 Val = DAG.getNode(ISD::AssertSext, DL, VT, Val, in LowerFormalArguments()
3291 Val = DAG.getNode(ISD::AssertSext, DL, VA.getLocVT(), Val, in LowerCallResult()
11941 case ISD::AssertSext: { in calculateByteProvider()
11949 Op->getOpcode() == ISD::AssertSext) { in calculateByteProvider()
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| H A D | AMDGPUISelLowering.cpp | 622 ISD::AssertSext, ISD::INTRINSIC_WO_CHAIN}); in AMDGPUTargetLowering()
5249 case ISD::AssertSext: in PerformDAGCombine()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/M68k/ |
| H A D | M68kISelLowering.cpp | 961 ArgValue = DAG.getNode(ISD::AssertSext, DL, RegVT, ArgValue, in LowerFormalArguments()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/Target/ |
| H A D | TargetSelectionDAG.td | 826 def assertsext : SDNode<"ISD::AssertSext", SDT_assert>;
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| /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.cpp | 4484 ArgVal = DAG.getNode(ISD::AssertSext, dl, MVT::i64, ArgVal, in extendArgForPPC64()
5397 Val = DAG.getNode(ISD::AssertSext, dl, VA.getLocVT(), Val, in LowerCallResult()
7120 ArgValue = DAG.getNode(ISD::AssertSext, dl, LocVT, ArgValue, in truncateScalarIntegerArg()
17811 ExtsSrc.getOperand(0).getOpcode() == ISD::AssertSext) in combineSHL()
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