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Searched refs:AsmName (Results 1 – 11 of 11) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/CSKY/
H A DCSKYRegisterInfo.td24 // Because CSKYFReg64 register have AsmName and AltNames that alias with their
36 let AsmName = subreg.AsmName;
44 let AsmName = subreg.AsmName;
/freebsd/contrib/llvm-project/llvm/lib/Target/VE/
H A DVERegisterInfo.td56 def AsmName : RegAltNameIndex;
101 let RegAltNameIndices = [AsmName] in {
167 } // RegAltNameIndices = [AsmName]
/freebsd/contrib/llvm-project/llvm/utils/TableGen/
H A DAsmWriterEmitter.cpp589 std::string &AsmName = AsmNames[i++]; in emitRegisterNameString() local
594 AsmName = std::string(Reg.TheDef->getValueAsString("AsmName")); in emitRegisterNameString()
595 if (AsmName.empty()) in emitRegisterNameString()
596 AsmName = std::string(Reg.getName()); in emitRegisterNameString()
614 AsmName = std::string(AltNames[Idx]); in emitRegisterNameString()
617 StringTable.add(AsmName); in emitRegisterNameString()
H A DAsmMatcherEmitter.cpp2633 StringRef AsmName = Reg.TheDef->getValueAsString("AsmName"); in emitMatchRegisterName() local
2634 if (AsmName.empty()) in emitMatchRegisterName()
2637 Matches.emplace_back(AsmName.str(), "return " + Namespace + in emitMatchRegisterName()
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVRegisterInfo.td33 : RISCVRegWithSubRegs<subreg.HWEncoding{4-0}, subreg.AsmName, [subreg],
38 // Because RISCVReg64 register have AsmName and AltNames that alias with their
43 : RISCVRegWithSubRegs<subreg.HWEncoding{4-0}, subreg.AsmName, [subreg],
574 def X0_Pair : RISCVRegWithSubRegs<0, X0.AsmName,
586 Reg.AsmName,
/freebsd/contrib/llvm-project/llvm/lib/Target/VE/MCTargetDesc/
H A DVEInstPrinter.cpp32 unsigned AltIdx = VE::AsmName; in printRegName()
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DVOP3Instructions.td1531 multiclass VOP3_F16_Real_gfx9<bits<10> op, string OpName, string AsmName> {
1535 let AsmString = AsmName # ps.AsmOperands;
1539 multiclass VOP3OpSel_F16_Real_gfx9<bits<10> op, string AsmName> {
1543 let AsmString = AsmName # ps.AsmOperands;
1547 multiclass VOP3Interp_F16_Real_gfx9<bits<10> op, string OpName, string AsmName> {
1551 let AsmString = AsmName # ps.AsmOperands;
1555 multiclass VOP3_Real_gfx9<bits<10> op, string AsmName> {
1559 let AsmString = AsmName # ps.AsmOperands;
H A DVOP2Instructions.td2264 multiclass VOP2be_Real_e32e64_vi_only <bits<6> op, string OpName, string AsmName> {
2269 let AsmString = AsmName # ps.AsmOperands;
2275 let AsmString = AsmName # ps.AsmOperands;
2282 let AsmString = AsmName # ps.AsmOperands;
2289 let AsmString = AsmName # ps.AsmOperands;
2297 multiclass VOP2be_Real_e32e64_gfx9 <bits<6> op, string OpName, string AsmName> {
2302 let AsmString = AsmName # ps.AsmOperands;
2308 let AsmString = AsmName # ps.AsmOperands;
2315 let AsmString = AsmName # ps.AsmOperands;
2322 let AsmString = AsmName # ps.AsmOperands;
/freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchRegisterInfo.td35 : LoongArchRegWithSubRegs<subreg.HWEncoding, subreg.AsmName, [subreg],
/freebsd/contrib/llvm-project/llvm/utils/TableGen/Common/
H A DCodeGenRegisters.cpp674 StringInit *AsmName = StringInit::get(RK, ""); in expand() local
680 AsmName = StringInit::get(RK, RegNames[n]); in expand()
717 RV.setValue(AsmName); in expand()
/freebsd/contrib/llvm-project/llvm/include/llvm/Target/
H A DTarget.td165 string AsmName = n;
420 // the AsmName and Dwarf numbers are cleared.