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Searched refs:ArgRC (Results 1 – 5 of 5) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUCallLowering.cpp802 const TargetRegisterClass *ArgRC; in passSpecialInputs() local
809 std::tie(OutgoingArg, ArgRC, ArgTy) = in passSpecialInputs()
818 assert(IncomingArgRC == ArgRC); in passSpecialInputs()
823 LI->loadInputValue(InputReg, MIRBuilder, IncomingArg, ArgRC, ArgTy); in passSpecialInputs()
853 const TargetRegisterClass *ArgRC; in passSpecialInputs() local
856 std::tie(OutgoingArg, ArgRC, ArgTy) = in passSpecialInputs()
859 std::tie(OutgoingArg, ArgRC, ArgTy) = in passSpecialInputs()
862 std::tie(OutgoingArg, ArgRC, ArgTy) = in passSpecialInputs()
H A DAMDGPULegalizerInfo.h116 const TargetRegisterClass *ArgRC, LLT ArgTy) const;
H A DAMDGPULegalizerInfo.cpp4261 const TargetRegisterClass *ArgRC, in loadInputValue() argument
4268 *ArgRC, B.getDebugLoc(), ArgTy); in loadInputValue()
4297 const TargetRegisterClass *ArgRC; in loadInputValue() local
4316 ArgRC = &AMDGPU::SReg_32RegClass; in loadInputValue()
4321 ArgRC = &AMDGPU::SReg_32RegClass; in loadInputValue()
4326 ArgRC = &AMDGPU::SReg_32RegClass; in loadInputValue()
4335 std::tie(Arg, ArgRC, ArgTy) = MFI->getPreloadedValue(ArgType); in loadInputValue()
4353 return loadInputValue(DstReg, B, Arg, ArgRC, ArgTy); in loadInputValue()
4382 const TargetRegisterClass *ArgRC; in legalizeWorkitemIDIntrinsic() local
4384 std::tie(Arg, ArgRC, ArgTy) = MFI->getPreloadedValue(ArgType); in legalizeWorkitemIDIntrinsic()
H A DSIISelLowering.cpp3358 const TargetRegisterClass *ArgRC; in passSpecialInputs() local
3367 std::tie(OutgoingArg, ArgRC, ArgTy) = in passSpecialInputs()
3377 assert(IncomingArgRC == ArgRC); in passSpecialInputs()
3380 EVT ArgVT = TRI->getSpillSize(*ArgRC) == 8 ? MVT::i64 : MVT::i32; in passSpecialInputs()
3384 InputReg = loadInputValue(DAG, ArgRC, ArgVT, DL, *IncomingArg); in passSpecialInputs()
3419 const TargetRegisterClass *ArgRC; in passSpecialInputs() local
3422 std::tie(OutgoingArg, ArgRC, Ty) = in passSpecialInputs()
3425 std::tie(OutgoingArg, ArgRC, Ty) = in passSpecialInputs()
3428 std::tie(OutgoingArg, ArgRC, Ty) = in passSpecialInputs()
3451 InputReg = loadInputValue(DAG, ArgRC, MVT::i32, DL, *IncomingArgX); in passSpecialInputs()
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/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DDAGCombiner.cpp19452 const TargetRegisterClass *ArgRC = in canMergeExpensiveCrossRegisterBankCopy() local
19455 if (ArgRC == ResRC || !TLI.isOperationLegal(ISD::LOAD, ResVT)) in canMergeExpensiveCrossRegisterBankCopy()
19463 if (!TRI || TRI->getCommonSubClass(ArgRC, ResRC)) in canMergeExpensiveCrossRegisterBankCopy()