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Searched refs:ArgRC (Results 1 – 5 of 5) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUCallLowering.cpp804 const TargetRegisterClass *ArgRC; in passSpecialInputs() local
811 std::tie(OutgoingArg, ArgRC, ArgTy) = in passSpecialInputs()
820 assert(IncomingArgRC == ArgRC); in passSpecialInputs()
825 LI->buildLoadInputValue(InputReg, MIRBuilder, IncomingArg, ArgRC, ArgTy); in passSpecialInputs()
855 const TargetRegisterClass *ArgRC; in passSpecialInputs() local
858 std::tie(OutgoingArg, ArgRC, ArgTy) = in passSpecialInputs()
861 std::tie(OutgoingArg, ArgRC, ArgTy) = in passSpecialInputs()
864 std::tie(OutgoingArg, ArgRC, ArgTy) = in passSpecialInputs()
H A DAMDGPULegalizerInfo.h116 const TargetRegisterClass *ArgRC, LLT ArgTy) const;
H A DAMDGPULegalizerInfo.cpp4320 const TargetRegisterClass *ArgRC, in buildLoadInputValue() argument
4327 *ArgRC, B.getDebugLoc(), ArgTy); in buildLoadInputValue()
4354 const TargetRegisterClass *ArgRC; in loadInputValue() local
4373 ArgRC = &AMDGPU::SReg_32RegClass; in loadInputValue()
4378 ArgRC = &AMDGPU::SReg_32RegClass; in loadInputValue()
4383 ArgRC = &AMDGPU::SReg_32RegClass; in loadInputValue()
4392 std::tie(Arg, ArgRC, ArgTy) = MFI->getPreloadedValue(ArgType); in loadInputValue()
4410 buildLoadInputValue(DstReg, B, Arg, ArgRC, ArgTy); in loadInputValue()
4440 const TargetRegisterClass *ArgRC; in legalizeWorkitemIDIntrinsic() local
4442 std::tie(Arg, ArgRC, ArgTy) = MFI->getPreloadedValue(ArgType); in legalizeWorkitemIDIntrinsic()
H A DSIISelLowering.cpp3483 const auto [OutgoingArg, ArgRC, ArgTy] = in passSpecialInputs()
3490 assert(IncomingArgRC == ArgRC); in passSpecialInputs()
3493 EVT ArgVT = TRI->getSpillSize(*ArgRC) == 8 ? MVT::i64 : MVT::i32; in passSpecialInputs()
3497 InputReg = loadInputValue(DAG, ArgRC, ArgVT, DL, *IncomingArg); in passSpecialInputs()
3532 auto [OutgoingArg, ArgRC, Ty] = in passSpecialInputs()
3535 std::tie(OutgoingArg, ArgRC, Ty) = in passSpecialInputs()
3538 std::tie(OutgoingArg, ArgRC, Ty) = in passSpecialInputs()
3561 InputReg = loadInputValue(DAG, ArgRC, MVT::i32, DL, *IncomingArgX); in passSpecialInputs()
3569 SDValue Y = loadInputValue(DAG, ArgRC, MVT::i32, DL, *IncomingArgY); in passSpecialInputs()
3579 SDValue Z = loadInputValue(DAG, ArgRC, MVT::i32, DL, *IncomingArgZ); in passSpecialInputs()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DDAGCombiner.cpp20451 const TargetRegisterClass *ArgRC = in canMergeExpensiveCrossRegisterBankCopy() local
20454 if (ArgRC == ResRC || !TLI.isOperationLegal(ISD::LOAD, ResVT)) in canMergeExpensiveCrossRegisterBankCopy()
20462 if (!TRI || TRI->getCommonSubClass(ArgRC, ResRC)) in canMergeExpensiveCrossRegisterBankCopy()