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Searched refs:ArgDescriptor (Results 1 – 12 of 12) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUArgumentUsageInfo.h24 struct ArgDescriptor { struct
41 ArgDescriptor(unsigned Val = 0, unsigned Mask = ~0u, bool IsStack = false, argument
45 static ArgDescriptor createRegister(Register Reg, unsigned Mask = ~0u) { argument
46 return ArgDescriptor(Reg, Mask, false, true);
49 static ArgDescriptor createStack(unsigned Offset, unsigned Mask = ~0u) {
50 return ArgDescriptor(Offset, Mask, true, true);
53 static ArgDescriptor createArg(const ArgDescriptor &Arg, unsigned Mask) { in createArg() argument
54 return ArgDescriptor(Arg.Reg, Mask, Arg.IsStack, Arg.IsSet); in createArg()
90 inline raw_ostream &operator<<(raw_ostream &OS, const ArgDescriptor &Arg) { argument
95 struct KernArgPreloadDescriptor : public ArgDescriptor {
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H A DAMDGPUArgumentUsageInfo.cpp26 void ArgDescriptor::print(raw_ostream &OS, in print()
90 std::tuple<const ArgDescriptor *, const TargetRegisterClass *, LLT>
158 = ArgDescriptor::createRegister(AMDGPU::SGPR0_SGPR1_SGPR2_SGPR3); in fixedABILayout()
159 AI.DispatchPtr = ArgDescriptor::createRegister(AMDGPU::SGPR4_SGPR5); in fixedABILayout()
160 AI.QueuePtr = ArgDescriptor::createRegister(AMDGPU::SGPR6_SGPR7); in fixedABILayout()
164 AI.ImplicitArgPtr = ArgDescriptor::createRegister(AMDGPU::SGPR8_SGPR9); in fixedABILayout()
165 AI.DispatchID = ArgDescriptor::createRegister(AMDGPU::SGPR10_SGPR11); in fixedABILayout()
168 AI.WorkGroupIDX = ArgDescriptor::createRegister(AMDGPU::SGPR12); in fixedABILayout()
169 AI.WorkGroupIDY = ArgDescriptor::createRegister(AMDGPU::SGPR13); in fixedABILayout()
170 AI.WorkGroupIDZ = ArgDescriptor::createRegister(AMDGPU::SGPR14); in fixedABILayout()
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H A DSIMachineFunctionInfo.cpp79 ArgDescriptor::createRegister(ScratchRSrcReg); in SIMachineFunctionInfo()
95 ArgDescriptor::createRegister(ScratchRSrcReg); in SIMachineFunctionInfo()
153 ArgDescriptor::createRegister(AMDGPU::SGPR5); in SIMachineFunctionInfo()
193 ArgDescriptor::createRegister(TRI.getMatchingSuperReg( in addPrivateSegmentBuffer()
200 ArgInfo.DispatchPtr = ArgDescriptor::createRegister(TRI.getMatchingSuperReg( in addDispatchPtr()
207 ArgInfo.QueuePtr = ArgDescriptor::createRegister(TRI.getMatchingSuperReg( in addQueuePtr()
215 = ArgDescriptor::createRegister(TRI.getMatchingSuperReg( in addKernargSegmentPtr()
222 ArgInfo.DispatchID = ArgDescriptor::createRegister(TRI.getMatchingSuperReg( in addDispatchID()
229 ArgInfo.FlatScratchInit = ArgDescriptor::createRegister(TRI.getMatchingSuperReg( in addFlatScratchInit()
236 ArgInfo.PrivateSegmentSize = ArgDescriptor::createRegister(getNextUserSGPR()); in addPrivateSegmentSize()
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H A DSIMachineFunctionInfo.h772 ArgInfo.WorkGroupIDX = ArgDescriptor::createRegister(getNextSystemSGPR());
778 ArgInfo.WorkGroupIDY = ArgDescriptor::createRegister(getNextSystemSGPR());
784 ArgInfo.WorkGroupIDZ = ArgDescriptor::createRegister(getNextSystemSGPR());
790 ArgInfo.WorkGroupInfo = ArgDescriptor::createRegister(getNextSystemSGPR());
798 void setWorkItemIDX(ArgDescriptor Arg) {
802 void setWorkItemIDY(ArgDescriptor Arg) {
806 void setWorkItemIDZ(ArgDescriptor Arg) {
812 = ArgDescriptor::createRegister(getNextSystemSGPR());
818 ArgInfo.PrivateSegmentWaveByteOffset = ArgDescriptor::createRegister(Reg);
865 std::tuple<const ArgDescriptor *, const TargetRegisterClass *, LLT>
H A DAMDGPUCallLowering.cpp801 const ArgDescriptor *OutgoingArg; in passSpecialInputs()
814 const ArgDescriptor *IncomingArg; in passSpecialInputs()
852 const ArgDescriptor *OutgoingArg; in passSpecialInputs()
874 const ArgDescriptor *IncomingArgX = std::get<0>(WorkitemIDX); in passSpecialInputs()
875 const ArgDescriptor *IncomingArgY = std::get<0>(WorkitemIDY); in passSpecialInputs()
876 const ArgDescriptor *IncomingArgZ = std::get<0>(WorkitemIDZ); in passSpecialInputs()
929 ArgDescriptor IncomingArg = ArgDescriptor::createArg( in passSpecialInputs()
H A DAMDGPUTargetMachine.cpp1620 ArgDescriptor &Arg, unsigned UserSGPRs, in parseMachineFunctionInfo()
1634 Arg = ArgDescriptor::createRegister(Reg); in parseMachineFunctionInfo()
1636 Arg = ArgDescriptor::createStack(A->StackOffset); in parseMachineFunctionInfo()
1639 Arg = ArgDescriptor::createArg(Arg, *A->Mask); in parseMachineFunctionInfo()
H A DAMDGPUISelLowering.h25 struct ArgDescriptor;
371 const ArgDescriptor &Arg) const;
H A DAMDGPULegalizerInfo.h115 const ArgDescriptor *Arg,
H A DSIISelLowering.cpp1971 const ArgDescriptor *InputPtrReg; in lowerKernArgParameterPtr()
2136 const ArgDescriptor *Reg = nullptr; in getPreloadedValue()
2141 const ArgDescriptor WorkGroupIDX = in getPreloadedValue()
2142 ArgDescriptor::createRegister(AMDGPU::TTMP9); in getPreloadedValue()
2146 const ArgDescriptor WorkGroupIDY = ArgDescriptor::createRegister( in getPreloadedValue()
2149 const ArgDescriptor WorkGroupIDZ = in getPreloadedValue()
2150 ArgDescriptor::createRegister(AMDGPU::TTMP7, 0xFFFF0000u); in getPreloadedValue()
2255 Info.setWorkItemIDX(ArgDescriptor::createRegister(Reg, Mask)); in allocateSpecialEntryInputVGPRs()
2261 Info.setWorkItemIDY(ArgDescriptor::createRegister(AMDGPU::VGPR0, in allocateSpecialEntryInputVGPRs()
2268 Info.setWorkItemIDY(ArgDescriptor::createRegister(Reg)); in allocateSpecialEntryInputVGPRs()
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H A DAMDGPULegalizerInfo.cpp4260 const ArgDescriptor *Arg, in loadInputValue()
4296 const ArgDescriptor *Arg = nullptr; in loadInputValue()
4301 const ArgDescriptor WorkGroupIDX = in loadInputValue()
4302 ArgDescriptor::createRegister(AMDGPU::TTMP9); in loadInputValue()
4306 const ArgDescriptor WorkGroupIDY = ArgDescriptor::createRegister( in loadInputValue()
4309 const ArgDescriptor WorkGroupIDZ = in loadInputValue()
4310 ArgDescriptor::createRegister(AMDGPU::TTMP7, 0xFFFF0000u); in loadInputValue()
4381 const ArgDescriptor *Arg; in legalizeWorkitemIDIntrinsic()
H A DSIISelLowering.h85 const ArgDescriptor &ArgDesc) const;
H A DAMDGPUISelLowering.cpp5365 const ArgDescriptor &Arg) const { in loadInputValue()