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Searched refs:ArgDescriptor (Results 1 – 12 of 12) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUArgumentUsageInfo.h25 struct ArgDescriptor { struct
42 ArgDescriptor(unsigned Val = 0, unsigned Mask = ~0u, bool IsStack = false, argument
46 static ArgDescriptor createRegister(Register Reg, unsigned Mask = ~0u) { argument
47 return ArgDescriptor(Reg, Mask, false, true);
50 static ArgDescriptor createStack(unsigned Offset, unsigned Mask = ~0u) {
51 return ArgDescriptor(Offset, Mask, true, true);
54 static ArgDescriptor createArg(const ArgDescriptor &Arg, unsigned Mask) { in createArg() argument
55 return ArgDescriptor(Arg.Reg, Mask, Arg.IsStack, Arg.IsSet); in createArg()
93 inline raw_ostream &operator<<(raw_ostream &OS, const ArgDescriptor &Arg) { argument
98 struct KernArgPreloadDescriptor : public ArgDescriptor {
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H A DAMDGPUArgumentUsageInfo.cpp25 void ArgDescriptor::print(raw_ostream &OS, in print()
89 std::tuple<const ArgDescriptor *, const TargetRegisterClass *, LLT>
157 = ArgDescriptor::createRegister(AMDGPU::SGPR0_SGPR1_SGPR2_SGPR3); in fixedABILayout()
158 AI.DispatchPtr = ArgDescriptor::createRegister(AMDGPU::SGPR4_SGPR5); in fixedABILayout()
159 AI.QueuePtr = ArgDescriptor::createRegister(AMDGPU::SGPR6_SGPR7); in fixedABILayout()
163 AI.ImplicitArgPtr = ArgDescriptor::createRegister(AMDGPU::SGPR8_SGPR9); in fixedABILayout()
164 AI.DispatchID = ArgDescriptor::createRegister(AMDGPU::SGPR10_SGPR11); in fixedABILayout()
167 AI.WorkGroupIDX = ArgDescriptor::createRegister(AMDGPU::SGPR12); in fixedABILayout()
168 AI.WorkGroupIDY = ArgDescriptor::createRegister(AMDGPU::SGPR13); in fixedABILayout()
169 AI.WorkGroupIDZ = ArgDescriptor::createRegister(AMDGPU::SGPR14); in fixedABILayout()
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H A DSIMachineFunctionInfo.cpp88 ArgDescriptor::createRegister(ScratchRSrcReg); in SIMachineFunctionInfo()
104 ArgDescriptor::createRegister(ScratchRSrcReg); in SIMachineFunctionInfo()
157 ArgDescriptor::createRegister(AMDGPU::SGPR5); in SIMachineFunctionInfo()
199 ArgDescriptor::createRegister(TRI.getMatchingSuperReg( in addPrivateSegmentBuffer()
206 ArgInfo.DispatchPtr = ArgDescriptor::createRegister(TRI.getMatchingSuperReg( in addDispatchPtr()
213 ArgInfo.QueuePtr = ArgDescriptor::createRegister(TRI.getMatchingSuperReg( in addQueuePtr()
221 = ArgDescriptor::createRegister(TRI.getMatchingSuperReg( in addKernargSegmentPtr()
228 ArgInfo.DispatchID = ArgDescriptor::createRegister(TRI.getMatchingSuperReg( in addDispatchID()
235 ArgInfo.FlatScratchInit = ArgDescriptor::createRegister(TRI.getMatchingSuperReg( in addFlatScratchInit()
242 ArgInfo.PrivateSegmentSize = ArgDescriptor::createRegister(getNextUserSGPR()); in addPrivateSegmentSize()
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H A DSIMachineFunctionInfo.h863 ArgInfo.WorkGroupIDX = ArgDescriptor::createRegister(getNextSystemSGPR());
869 ArgInfo.WorkGroupIDY = ArgDescriptor::createRegister(getNextSystemSGPR());
875 ArgInfo.WorkGroupIDZ = ArgDescriptor::createRegister(getNextSystemSGPR());
881 ArgInfo.WorkGroupInfo = ArgDescriptor::createRegister(getNextSystemSGPR());
889 void setWorkItemIDX(ArgDescriptor Arg) {
893 void setWorkItemIDY(ArgDescriptor Arg) {
897 void setWorkItemIDZ(ArgDescriptor Arg) {
903 = ArgDescriptor::createRegister(getNextSystemSGPR());
909 ArgInfo.PrivateSegmentWaveByteOffset = ArgDescriptor::createRegister(Reg);
956 std::tuple<const ArgDescriptor *, const TargetRegisterClass *, LLT>
H A DAMDGPUCallLowering.cpp803 const ArgDescriptor *OutgoingArg; in passSpecialInputs()
816 const ArgDescriptor *IncomingArg; in passSpecialInputs()
854 const ArgDescriptor *OutgoingArg; in passSpecialInputs()
876 const ArgDescriptor *IncomingArgX = std::get<0>(WorkitemIDX); in passSpecialInputs()
877 const ArgDescriptor *IncomingArgY = std::get<0>(WorkitemIDY); in passSpecialInputs()
878 const ArgDescriptor *IncomingArgZ = std::get<0>(WorkitemIDZ); in passSpecialInputs()
932 ArgDescriptor IncomingArg = ArgDescriptor::createArg( in passSpecialInputs()
H A DAMDGPUISelLowering.h25 struct ArgDescriptor;
372 const ArgDescriptor &Arg) const;
H A DAMDGPULegalizerInfo.h115 const ArgDescriptor *Arg,
H A DAMDGPUTargetMachine.cpp1888 ArgDescriptor &Arg, unsigned UserSGPRs, in parseMachineFunctionInfo()
1902 Arg = ArgDescriptor::createRegister(Reg); in parseMachineFunctionInfo()
1904 Arg = ArgDescriptor::createStack(A->StackOffset); in parseMachineFunctionInfo()
1907 Arg = ArgDescriptor::createArg(Arg, *A->Mask); in parseMachineFunctionInfo()
H A DSIISelLowering.cpp2241 const ArgDescriptor *Reg = nullptr; in getPreloadedValue()
2246 const ArgDescriptor WorkGroupIDX = in getPreloadedValue()
2247 ArgDescriptor::createRegister(AMDGPU::TTMP9); in getPreloadedValue()
2251 const ArgDescriptor WorkGroupIDY = ArgDescriptor::createRegister( in getPreloadedValue()
2254 const ArgDescriptor WorkGroupIDZ = in getPreloadedValue()
2255 ArgDescriptor::createRegister(AMDGPU::TTMP7, 0xFFFF0000u); in getPreloadedValue()
2358 Info.setWorkItemIDX(ArgDescriptor::createRegister(Reg, Mask)); in allocateSpecialEntryInputVGPRs()
2365 ArgDescriptor::createRegister(AMDGPU::VGPR0, 0x3ff << 10)); in allocateSpecialEntryInputVGPRs()
2371 Info.setWorkItemIDY(ArgDescriptor::createRegister(Reg)); in allocateSpecialEntryInputVGPRs()
2379 ArgDescriptor::createRegister(AMDGPU::VGPR0, 0x3ff << 20)); in allocateSpecialEntryInputVGPRs()
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H A DAMDGPULegalizerInfo.cpp4319 const ArgDescriptor *Arg, in buildLoadInputValue()
4353 const ArgDescriptor *Arg = nullptr; in loadInputValue()
4358 const ArgDescriptor WorkGroupIDX = in loadInputValue()
4359 ArgDescriptor::createRegister(AMDGPU::TTMP9); in loadInputValue()
4363 const ArgDescriptor WorkGroupIDY = ArgDescriptor::createRegister( in loadInputValue()
4366 const ArgDescriptor WorkGroupIDZ = in loadInputValue()
4367 ArgDescriptor::createRegister(AMDGPU::TTMP7, 0xFFFF0000u); in loadInputValue()
4439 const ArgDescriptor *Arg; in legalizeWorkitemIDIntrinsic()
H A DSIISelLowering.h85 const ArgDescriptor &ArgDesc) const;
H A DAMDGPUISelLowering.cpp5598 const ArgDescriptor &Arg) const { in loadInputValue()