| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SILowerI1Copies.h | 60 unsigned AndOp; variable
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| H A D | SILowerI1Copies.cpp | 455 AndOp = AMDGPU::S_AND_B32; in PhiLoweringHelper()
463 AndOp = AMDGPU::S_AND_B64; in PhiLoweringHelper()
825 BuildMI(MBB, I, DL, TII->get(AndOp), CurMaskedReg) in buildMergeLaneMasks()
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| H A D | AMDGPUGlobalISelDivergenceLowering.cpp | 177 B.buildInstr(AndOp, {CurMaskedReg}, {ExecReg, CurRegCopy}); in buildMergeLaneMasks()
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| /freebsd/contrib/llvm-project/llvm/lib/TableGen/ |
| H A D | SetTheory.cpp | 63 struct AndOp : public SetTheory::Operator { struct
260 addOperator("and", std::make_unique<AndOp>()); in SetTheory()
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| /freebsd/contrib/llvm-project/clang/lib/CIR/Lowering/ |
| H A D | LoweringHelpers.cpp | 176 return bld.create<mlir::LLVM::AndOp>(lhs.getLoc(), lhs, rhsVal); in createAnd()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/M68k/ |
| H A D | M68kFrameLowering.cpp | 204 unsigned AndOp = M68k::AND32di; in BuildStackAlignAND() local
216 MachineInstr *MI = BuildMI(MBB, MBBI, DL, TII.get(AndOp), Tmp) in BuildStackAlignAND()
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| /freebsd/contrib/llvm-project/clang/lib/CIR/Lowering/DirectToLLVM/ |
| H A D | LowerToLLVM.cpp | 522 rewriter.create<mlir::LLVM::AndOp>(op.getLoc(), popcnt, one); in matchAndRewrite()
1613 rewriter.replaceOpWithNewOp<mlir::LLVM::AndOp>(op, lhs, rhs); in matchAndRewrite()
1739 rewriter.replaceOpWithNewOp<mlir::LLVM::AndOp>(cmpOp, realCmp, imagCmp); in matchAndRewrite()
1747 rewriter.replaceOpWithNewOp<mlir::LLVM::AndOp>(cmpOp, realCmp, imagCmp); in matchAndRewrite()
1839 rewriter.replaceOpWithNewOp<mlir::LLVM::AndOp>(op, adaptor.getCondition(), in matchAndRewrite()
2349 mlir::Value maskedIndices = rewriter.create<mlir::LLVM::AndOp>( in matchAndRewrite()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86FrameLowering.cpp | 1310 unsigned AndOp = getANDriOpcode(Uses64BitFramePtr, Val); in BuildStackAlignAND() local
1351 BuildMI(entryMBB, DL, TII.get(AndOp), FinalStackProbed) in BuildStackAlignAND()
1443 MachineInstr *MI = BuildMI(MBB, MBBI, DL, TII.get(AndOp), Reg) in BuildStackAlignAND()
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| H A D | X86ISelLowering.cpp | 31795 Value *AndOp; in FindSingleBitChange() local
31797 if (match(BitV, m_c_And(m_Value(AndOp), m_SpecificInt(ShiftMask)))) in FindSingleBitChange()
31798 BitV = AndOp; in FindSingleBitChange()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| H A D | IRTranslator.cpp | 1186 auto AndOp = MIB.buildAnd(SwitchTy, SwitchVal, CstMask); in emitBitTestCase() local
1188 Cmp = MIB.buildICmp(CmpInst::ICMP_NE, LLT::scalar(1), AndOp, CstZero) in emitBitTestCase()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 6972 SDValue AndOp; in LowerVSETCC() local
6974 AndOp = Op0; in LowerVSETCC()
6976 AndOp = Op1; in LowerVSETCC()
6979 if (AndOp.getNode() && AndOp.getOpcode() == ISD::BITCAST) in LowerVSETCC()
6980 AndOp = AndOp.getOperand(0); in LowerVSETCC()
6982 if (AndOp.getNode() && AndOp.getOpcode() == ISD::AND) { in LowerVSETCC()
6983 Op0 = DAG.getNode(ISD::BITCAST, dl, CmpVT, AndOp.getOperand(0)); in LowerVSETCC()
6984 Op1 = DAG.getNode(ISD::BITCAST, dl, CmpVT, AndOp.getOperand(1)); in LowerVSETCC()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAGBuilder.cpp | 3315 SDValue AndOp = DAG.getNode(ISD::AND, dl, in visitBitTestCase() local
3319 AndOp, DAG.getConstant(0, dl, VT), ISD::SETNE); in visitBitTestCase()
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| H A D | DAGCombiner.cpp | 6700 SDValue AndOp = DAG.getNode(ISD::AND, DL, OpVT, NotOp, in foldAndOrOfSETCC() local
6702 return DAG.getNode(ISD::SETCC, DL, VT, AndOp, in foldAndOrOfSETCC()
6708 SDValue AndOp = DAG.getNode(ISD::AND, DL, OpVT, AddOp, in foldAndOrOfSETCC() local
6710 return DAG.getNode(ISD::SETCC, DL, VT, AndOp, in foldAndOrOfSETCC()
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