| /freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/ |
| H A D | LoongArchISelLowering.cpp | 3550 SDNode *AndNode = N->getOperand(0).getNode(); in performSETCCCombine() local
3551 if (AndNode->getOpcode() != ISD::AND) in performSETCCCombine()
3554 SDValue AndInputValue2 = AndNode->getOperand(1); in performSETCCCombine()
3559 SDValue AndInputValue1 = AndNode->getOperand(0); in performSETCCCombine()
3597 AndNode->getValueType(0) != TruncInputValue1->getValueType(0)) in performSETCCCombine()
3605 SDValue NewAnd = DAG.getNode(ISD::AND, SDLoc(N), AndNode->getValueType(0), in performSETCCCombine()
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| /freebsd/contrib/llvm-project/llvm/lib/IR/ |
| H A D | AutoUpgrade.cpp | 1982 Value* AndNode = Builder.CreateAnd(Mask, APInt(8, 1)); in upgradeMaskedMove() local
1983 Value* Cmp = Builder.CreateIsNotNull(AndNode); in upgradeMaskedMove()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 23505 SDNode *AndNode, SelectionDAG &DAG, in performSubsToAndsCombine() argument
23522 ConstantSDNode *AndC = dyn_cast<ConstantSDNode>(AndNode->getOperand(1)); in performSubsToAndsCombine()
23531 AArch64ISD::ANDS, DL, SubsNode->getVTList(), AndNode->getOperand(0), in performSubsToAndsCombine()
23566 SDNode *AndNode = SubsNode->getOperand(0).getNode(); in performCONDCombine() local
23569 if (AndNode->getOpcode() != ISD::AND) in performCONDCombine()
23572 if (SDValue Val = performSubsToAndsCombine(N, SubsNode, AndNode, DAG, CCIndex, in performCONDCombine()
23576 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(AndNode->getOperand(1))) { in performCONDCombine()
23587 SDValue AddValue = AndNode->getOperand(0); in performCONDCombine()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | LegalizeIntegerTypes.cpp | 5206 SDValue AndNode = DAG.getNode(ISD::AND, DL, ShAmtVT, ShAmt, in ExpandIntRes_FunnelShift() local
5209 DAG.getSetCC(DL, ShAmtCCVT, AndNode, DAG.getConstant(0, DL, ShAmtVT), in ExpandIntRes_FunnelShift()
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| H A D | TargetLowering.cpp | 8155 SDValue AndNode = DAG.getNode(ISD::AND, dl, ShAmtVT, ShAmt, in expandShiftParts() local
8157 SDValue Cond = DAG.getSetCC(dl, ShAmtCCVT, AndNode, in expandShiftParts()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 46091 SDValue AndNode = Cond.getOperand(0); in combineSelect() local
46092 if (AndNode.getOpcode() == ISD::AND && CC == ISD::SETEQ && in combineSelect()
46094 isOneConstant(AndNode.getOperand(1))) { in combineSelect()
46097 AndNode = DAG.getZExtOrTrunc(AndNode, DL, MVT::i8); in combineSelect()
46098 return DAG.getNode(ISD::SELECT, DL, VT, AndNode, RHS, LHS); in combineSelect()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 15972 auto AndNode = DAG.getNode(ISD::AND, SDLoc(N), CountZeroes.getValueType(), in foldSelectOfCTTZOrCTLZ()
15974 return DAG.getZExtOrTrunc(AndNode, SDLoc(N), N->getValueType(0)); in useInversedSetcc()
15969 auto AndNode = DAG.getNode(ISD::AND, SDLoc(N), CountZeroes.getValueType(), foldSelectOfCTTZOrCTLZ() local
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