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Searched refs:AndNode (Results 1 – 7 of 7) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchISelLowering.cpp5045 SDNode *AndNode = N->getOperand(0).getNode(); in performSETCCCombine() local
5046 if (AndNode->getOpcode() != ISD::AND) in performSETCCCombine()
5049 SDValue AndInputValue2 = AndNode->getOperand(1); in performSETCCCombine()
5054 SDValue AndInputValue1 = AndNode->getOperand(0); in performSETCCCombine()
5092 AndNode->getValueType(0) != TruncInputValue1->getValueType(0)) in performSETCCCombine()
5100 SDValue NewAnd = DAG.getNode(ISD::AND, SDLoc(N), AndNode->getValueType(0), in performSETCCCombine()
/freebsd/contrib/llvm-project/llvm/lib/IR/
H A DAutoUpgrade.cpp2159 Value* AndNode = Builder.CreateAnd(Mask, APInt(8, 1)); in upgradeMaskedMove() local
2160 Value* Cmp = Builder.CreateIsNotNull(AndNode); in upgradeMaskedMove()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp24661 SDNode *AndNode, SelectionDAG &DAG, in performSubsToAndsCombine() argument
24678 ConstantSDNode *AndC = dyn_cast<ConstantSDNode>(AndNode->getOperand(1)); in performSubsToAndsCombine()
24687 AArch64ISD::ANDS, DL, SubsNode->getVTList(), AndNode->getOperand(0), in performSubsToAndsCombine()
24722 SDNode *AndNode = SubsNode->getOperand(0).getNode(); in performCONDCombine() local
24725 if (AndNode->getOpcode() != ISD::AND) in performCONDCombine()
24728 if (SDValue Val = performSubsToAndsCombine(N, SubsNode, AndNode, DAG, CCIndex, in performCONDCombine()
24732 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(AndNode->getOperand(1))) { in performCONDCombine()
24743 SDValue AddValue = AndNode->getOperand(0); in performCONDCombine()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeIntegerTypes.cpp5442 SDValue AndNode = DAG.getNode(ISD::AND, DL, ShAmtVT, ShAmt, in ExpandIntRes_FunnelShift() local
5445 DAG.getSetCC(DL, ShAmtCCVT, AndNode, DAG.getConstant(0, DL, ShAmtVT), in ExpandIntRes_FunnelShift()
H A DTargetLowering.cpp8373 SDValue AndNode = DAG.getNode(ISD::AND, dl, ShAmtVT, ShAmt, in expandShiftParts() local
8375 SDValue Cond = DAG.getSetCC(dl, ShAmtCCVT, AndNode, in expandShiftParts()
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp47834 SDValue AndNode = Cond.getOperand(0); in combineSelect() local
47835 if (AndNode.getOpcode() == ISD::AND && CC == ISD::SETEQ && in combineSelect()
47837 isOneConstant(AndNode.getOperand(1))) { in combineSelect()
47840 AndNode = DAG.getZExtOrTrunc(AndNode, DL, MVT::i8); in combineSelect()
47841 return DAG.getNode(ISD::SELECT, DL, VT, AndNode, RHS, LHS); in combineSelect()
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp18533 auto AndNode = DAG.getNode(ISD::AND, SDLoc(N), CountZeroes.getValueType(), in foldSelectOfCTTZOrCTLZ() local
18535 return DAG.getZExtOrTrunc(AndNode, SDLoc(N), N->getValueType(0)); in foldSelectOfCTTZOrCTLZ()