| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonLoopIdiomRecognition.cpp | 1608 Instruction *And1 = dyn_cast<Instruction>(I->getOperand(1)); in setupPreSimplifier() local
1609 if (!And0 || !And1) in setupPreSimplifier()
1612 And1->getOpcode() != Instruction::And) in setupPreSimplifier()
1614 if (And0->getOperand(1) != And1->getOperand(1)) in setupPreSimplifier()
1617 return B.CreateAnd(B.CreateXor(And0->getOperand(0), And1->getOperand(0)), in setupPreSimplifier()
1740 Instruction *And1 = dyn_cast<Instruction>(Xor->getOperand(1)); in setupPostSimplifier() local
1743 std::swap(And0, And1); in setupPostSimplifier()
1752 return B.CreateAnd(B.CreateXor(And0->getOperand(0), And1), C0); in setupPostSimplifier()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | ExpandFp.cpp | 549 Value *And1 = in expandIToFP() local
551 Value *Or1 = Builder.CreateOr(Shl1, And1); in expandIToFP()
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| /freebsd/contrib/llvm-project/llvm/lib/Transforms/InstCombine/ |
| H A D | InstCombineSimplifyDemanded.cpp | 639 Instruction *And1 = BinaryOperator::CreateAnd(I->getOperand(0), One); in SimplifyDemandedUseBits() local
640 return InsertNewInstWith(And1, I->getIterator()); in SimplifyDemandedUseBits()
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| H A D | InstCombineCasts.cpp | 1050 Value *And1 = in transformZExtICmp() local
1053 Zext, Builder.CreateZExtOrTrunc(And1, Zext.getType())); in transformZExtICmp()
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| H A D | InstCombineCompares.cpp | 5576 Value *And1 = Builder.CreateAnd(BO0->getOperand(0), Mask); in foldICmpBinOp() local
5578 return new ICmpInst(Pred, And1, And2); in foldICmpBinOp()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelDAGToDAG.cpp | 3728 SDValue And1 = N->getOperand(1); in tryBitfieldInsertOpFromOr() local
3729 if (And0.hasOneUse() && And1.hasOneUse() && in tryBitfieldInsertOpFromOr()
3731 isOpcWithIntImmediate(And1.getNode(), ISD::AND, Mask1Imm) && in tryBitfieldInsertOpFromOr()
3739 std::swap(And0, And1); in tryBitfieldInsertOpFromOr()
3743 SDValue Src = And1->getOperand(0); in tryBitfieldInsertOpFromOr()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| H A D | LegalizerHelper.cpp | 8220 Register And1; in lowerFCopySign() local
8222 And1 = MIRBuilder.buildAnd(Src1Ty, Src1, SignBitMask).getReg(0); in lowerFCopySign()
8227 And1 = MIRBuilder.buildAnd(Src0Ty, Shift, SignBitMask).getReg(0); in lowerFCopySign()
8232 And1 = MIRBuilder.buildAnd(Src0Ty, Trunc, SignBitMask).getReg(0); in lowerFCopySign()
8243 MIRBuilder.buildOr(Dst, And0, And1, Flags); in lowerFCopySign()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/NVPTX/ |
| H A D | NVPTXISelLowering.cpp | 2870 SDValue And1 = DAG.getNode(ISD::AND, DL, MVT::i1, Cond, TrueVal); in lowerSELECT() local
2873 SDValue Or = DAG.getNode(ISD::OR, DL, MVT::i1, And1, And2); in lowerSELECT()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | TargetLowering.cpp | 2867 SDValue And1 = TLO.DAG.getNode(ISD::AND, dl, VT, Op.getOperand(0), One); in SimplifyDemandedBits() local
2868 return TLO.CombineTo(Op, And1); in SimplifyDemandedBits()
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| H A D | DAGCombiner.cpp | 7157 SDValue And0 = And->getOperand(0), And1 = And->getOperand(1); in combineShiftAnd1ToBitTest() local
7160 if (!isOneConstant(And1) || !And0.hasOneUse()) in combineShiftAnd1ToBitTest()
|