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Searched refs:Amt1 (Results 1 – 2 of 2) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPURegBankLegalizeHelper.cpp200 auto [Amt0, Amt1] = unpackAExt(MI.getOperand(2).getReg()); in lowerUnpackBitShift()
202 Hi = B.buildInstr(MI.getOpcode(), {SgprRB_S32}, {Val1, Amt1}).getReg(0); in lowerUnpackBitShift()
207 auto [Amt0, Amt1] = unpackZExt(MI.getOperand(2).getReg()); in lowerUnpackBitShift()
209 Hi = B.buildInstr(MI.getOpcode(), {SgprRB_S32}, {Val1, Amt1}).getReg(0); in lowerUnpackBitShift()
214 auto [Amt0, Amt1] = unpackSExt(MI.getOperand(2).getReg()); in lowerUnpackBitShift()
216 Hi = B.buildAShr(SgprRB_S32, Val1, Amt1).getReg(0); in lowerUnpackBitShift()
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp30546 SDValue Amt1 = DAG.getVectorShuffle(VT, dl, Amt, Amt, {1, 1}); in LowerShift() local
30548 SDValue R1 = DAG.getNode(Opc, dl, VT, R, Amt1); in LowerShift()
30800 SDValue Amt1 = in LowerShift() local
30806 return DAG.getSelect(dl, VT, Amt1, Sra1, Res); in LowerShift()
30816 SDValue Amt0, Amt1, Amt2, Amt3; in LowerShift() local
30819 Amt1 = DAG.getVectorShuffle(VT, dl, Amt, DAG.getUNDEF(VT), {1, 1, 1, 1}); in LowerShift()
30830 Amt1 = DAG.getVectorShuffle(VT, dl, Amt, Z, {1, 5, -1, -1}); in LowerShift()
30840 Amt1 = DAG.getNode(X86ISD::PSHUFLW, dl, MVT::v8i16, Amt01, Msk13); in LowerShift()
30848 SDValue R1 = DAG.getNode(ShOpc, dl, VT, R, DAG.getBitcast(VT, Amt1)); in LowerShift()
50489 auto MergeShifts = [&](SDValue X, uint64_t Amt0, uint64_t Amt1) { in combineVectorShiftImm() argument
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