| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | RegAllocGreedy.h | 42 class AllocationOrder; variable
331 const AllocationOrder &Order);
342 MCRegister tryAssign(const LiveInterval &, AllocationOrder &,
344 MCRegister tryEvict(const LiveInterval &, AllocationOrder &,
347 MCRegister tryRegionSplit(const LiveInterval &, AllocationOrder &,
351 AllocationOrder &Order,
357 AllocationOrder &Order,
366 AllocationOrder &Order);
370 AllocationOrder &Order, MCRegister PhysReg,
374 unsigned tryBlockSplit(const LiveInterval &, AllocationOrder &,
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| H A D | AllocationOrder.h | 30 class LLVM_LIBRARY_VISIBILITY AllocationOrder {
45 const AllocationOrder &AO;
49 Iterator(const AllocationOrder &AO, int Pos) : AO(AO), Pos(Pos) {} in Iterator()
84 static AllocationOrder create(unsigned VirtReg, const VirtRegMap &VRM,
90 AllocationOrder(SmallVector<MCPhysReg, 16> &&Hints, ArrayRef<MCPhysReg> Order, in AllocationOrder() function
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| H A D | AllocationOrder.cpp | 29 AllocationOrder AllocationOrder::create(unsigned VirtReg, const VirtRegMap &VRM, in create()
50 return AllocationOrder(std::move(Hints), Order, HardHints); in create()
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| H A D | RegAllocEvictionAdvisor.h | 21 class AllocationOrder; variable
108 const LiveInterval &VirtReg, const AllocationOrder &Order,
129 const AllocationOrder &Order,
211 const AllocationOrder &, uint8_t,
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| H A D | RegisterScavenging.cpp | 130 const LiveRegUnits &LiveOut, ArrayRef<MCPhysReg> AllocationOrder, in determineKillsAndDefs()
152 for (MCPhysReg Reg : AllocationOrder) { in determineKillsAndDefs()
177 for (MCPhysReg Reg : AllocationOrder) { in forward()
305 ArrayRef<MCPhysReg> AllocationOrder = RC.getRawAllocationOrder(MF); in findSurvivorBackwards()
307 *MRI, std::prev(MBBI), To, LiveUnits, AllocationOrder, RestoreAfter); in findSurvivorBackwards()
283 findSurvivorBackwards(const MachineRegisterInfo & MRI,MachineBasicBlock::iterator From,MachineBasicBlock::iterator To,const LiveRegUnits & LiveOut,ArrayRef<MCPhysReg> AllocationOrder,bool RestoreAfter) findSurvivorBackwards() argument
458 ArrayRef<MCPhysReg> AllocationOrder = RC.getRawAllocationOrder(MF); scavengeRegisterBackwards() local
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| H A D | RegAllocGreedy.cpp | 398 AllocationOrder &Order, in tryAssign()
464 AllocationOrder::create(VirtReg.reg(), *VRM, RegClassInfo, Matrix)) { in canReassign()
532 const AllocationOrder &Order, in getOrderLimit()
578 AllocationOrder &Order, in tryEvict()
869 const AllocationOrder &Order) { in calcGlobalSplitCost()
1061 AllocationOrder &Order, in tryRegionSplit()
1095 AllocationOrder &Order, in calculateRegionSplitCostAroundReg()
1172 AllocationOrder &Order, in calculateRegionSplitCost()
1234 AllocationOrder &Order) { in trySplitAroundHintReg()
1294 AllocationOrder &Order, in tryBlockSplit()
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| H A D | RegAllocFast.cpp | 938 ArrayRef<MCPhysReg> AllocationOrder = RegClassInfo.getOrder(&RC); in allocVirtReg() local
939 for (MCPhysReg PhysReg : AllocationOrder) { in allocVirtReg()
993 ArrayRef<MCPhysReg> AllocationOrder = RegClassInfo.getOrder(&RC); in allocVirtRegUndef() local
994 assert(!AllocationOrder.empty() && "Allocation order must not be empty"); in allocVirtRegUndef()
995 PhysReg = AllocationOrder[0]; in allocVirtRegUndef()
1072 ArrayRef<MCPhysReg> AllocationOrder = RegClassInfo.getOrder(&RC); in defineVirtReg() local
1073 if (AllocationOrder.empty()) in defineVirtReg()
1075 return setPhysReg(MI, MO, *AllocationOrder.begin()); in defineVirtReg()
1163 ArrayRef<MCPhysReg> AllocationOrder = RegClassInfo.getOrder(&RC); in useVirtReg() local
1164 if (AllocationOrder.empty()) in useVirtReg()
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| H A D | MLRegallocEvictAdvisor.cpp | |
| H A D | MLRegAllocEvictAdvisor.cpp | 308 const AllocationOrder &Order,
324 const LiveInterval &VirtReg, const AllocationOrder &Order,
441 const LiveInterval &VirtReg, const AllocationOrder &Order,
591 const LiveInterval &, const AllocationOrder &, unsigned, uint8_t, in tryFindEvictionCandidatePosition() argument
667 const LiveInterval &VirtReg, const AllocationOrder &Order, in tryFindEvictionCandidate()
1088 const LiveInterval &VirtReg, const AllocationOrder &Order, in tryFindEvictionCandidatePosition()
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| H A D | RegAllocEvictionAdvisor.cpp | 277 const LiveInterval &VirtReg, const AllocationOrder &Order, in tryFindEvictionCandidate()
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| H A D | RegAllocBasic.cpp | 262 AllocationOrder::create(VirtReg.reg(), *VRM, RegClassInfo, Matrix); in selectOrSplit()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCRegisterInfo.td | 499 // Make AllocationOrder as similar as G8RC's to avoid potential spilling.
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| /freebsd/lib/clang/libllvm/ |
| H A D | Makefile | 201 SRCS_MIN+= CodeGen/AllocationOrder.cpp
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