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Searched refs:AllocateReg (Results 1 – 20 of 20) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVCallingConv.cpp246 if (MCRegister Reg = State.AllocateReg(ArgGPRs)) { in CC_RISCVAssign2XLen()
267 if (MCRegister Reg = State.AllocateReg(ArgGPRs)) { in CC_RISCVAssign2XLen()
289 if (MCRegister Reg = State.AllocateReg(RISCV::V0)) in allocateRVVReg()
291 return State.AllocateReg(ArgVRs); in allocateRVVReg()
294 return State.AllocateReg(ArgVRM2s); in allocateRVVReg()
296 return State.AllocateReg(ArgVRM4s); in allocateRVVReg()
298 return State.AllocateReg(ArgVRM8s); in allocateRVVReg()
300 return State.AllocateReg(ArgVRN2M1s); in allocateRVVReg()
302 return State.AllocateReg(ArgVRN3M1s); in allocateRVVReg()
304 return State.AllocateReg(ArgVRN4M1s); in allocateRVVReg()
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/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCCallingConv.cpp45 State.AllocateReg(ELF64ArgGPRs); in CC_PPC64_ELF_Shadow_GPR_Regs()
52 if ((State.AllocateReg(ELF64ArgGPRs) - PPC::X3) % 2 == 1) in CC_PPC64_ELF_Shadow_GPR_Regs()
53 State.AllocateReg(ELF64ArgGPRs); in CC_PPC64_ELF_Shadow_GPR_Regs()
54 State.AllocateReg(ELF64ArgGPRs); in CC_PPC64_ELF_Shadow_GPR_Regs()
84 State.AllocateReg(ArgRegs[RegNum]); in CC_PPC32_SVR4_Custom_AlignArgRegs()
109 State.AllocateReg(ArgRegs[RegNum + i]); in CC_PPC32_SVR4_Custom_SkipLastArgRegsPPCF128()
133 State.AllocateReg(ArgRegs[RegNum]); in CC_PPC32_SVR4_Custom_AlignFPArgRegs()
153 MCRegister Reg = State.AllocateReg(HiRegList); in CC_PPC32_SPE_CustomSplitFP64()
162 MCRegister T = State.AllocateReg(LoRegList[i]); in CC_PPC32_SPE_CustomSplitFP64()
182 MCRegister Reg = State.AllocateReg(HiRegList, LoRegList); in CC_PPC32_SPE_RetF64()
H A DPPCISelLowering.cpp6908 MCRegister Reg = State.AllocateReg(GPRs); in CC_AIX()
6919 if (MCRegister Reg = State.AllocateReg(GPRs)) in CC_AIX()
6946 if (MCRegister Reg = State.AllocateReg(GPRs)) in CC_AIX()
6961 MCRegister FReg = State.AllocateReg(FPR); in CC_AIX()
6967 if (MCRegister Reg = State.AllocateReg(GPRs)) { in CC_AIX()
7007 if (MCRegister VReg = State.AllocateReg(VR)) { in CC_AIX()
7025 MCRegister Reg = State.AllocateReg(GPRs); in CC_AIX()
7037 if (MCRegister VReg = State.AllocateReg(VR)) { in CC_AIX()
7041 State.AllocateReg(GPRs); in CC_AIX()
7066 const MCRegister FirstReg = State.AllocateReg(PPC::R9); in CC_AIX()
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/freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZCallingConv.h121 Reg = State.AllocateReg(SystemZ::ELFArgGPRs); in CC_SystemZ_I128Indirect()
123 Reg = State.AllocateReg(SystemZ::XPLINK64ArgGPRs); in CC_SystemZ_I128Indirect()
160 State.AllocateReg(SystemZ::XPLINK64ArgGPRs); in CC_XPLINK64_Shadow_Reg()
164 State.AllocateReg(SystemZ::XPLINK64ArgGPRs); in CC_XPLINK64_Shadow_Reg()
165 State.AllocateReg(SystemZ::XPLINK64ArgGPRs); in CC_XPLINK64_Shadow_Reg()
172 State.AllocateReg(SystemZ::XPLINK64ArgFPRs[I + 1]); in CC_XPLINK64_Shadow_Reg()
189 State.AllocateReg(SystemZ::R1D); in CC_XPLINK64_Allocate128BitVararg()
191 bool AllocGPR2 = State.AllocateReg(SystemZ::R2D); in CC_XPLINK64_Allocate128BitVararg()
192 bool AllocGPR3 = State.AllocateReg(SystemZ::R3D); in CC_XPLINK64_Allocate128BitVararg()
/freebsd/contrib/llvm-project/llvm/lib/Target/CSKY/
H A DCSKYCallingConv.h30 Register Reg = State.AllocateReg(ArgGPRs); in CC_CSKY_ABIV2_SOFT_64()
38 if (!State.AllocateReg(ArgGPRs)) in CC_CSKY_ABIV2_SOFT_64()
49 Register Reg = State.AllocateReg(ArgGPRs); in Ret_CSKY_ABIV2_SOFT_64()
54 if (!State.AllocateReg(ArgGPRs)) in Ret_CSKY_ABIV2_SOFT_64()
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMCallingConv.cpp26 if (MCRegister Reg = State.AllocateReg(RegList)) in f64AssignAPCS()
40 if (MCRegister Reg = State.AllocateReg(RegList)) in f64AssignAPCS()
69 MCRegister Reg = State.AllocateReg(HiRegList, ShadowRegList); in f64AssignAAPCS()
73 Reg = State.AllocateReg(GPRArgRegs); in f64AssignAAPCS()
91 MCRegister T = State.AllocateReg(LoRegList[i]); in f64AssignAAPCS()
118 MCRegister Reg = State.AllocateReg(HiRegList, LoRegList); in f64RetAssign()
207 State.AllocateReg(RegList[RegIdx++]); in CC_ARM_AAPCS_Custom_Aggregate()
252 It.convertToReg(State.AllocateReg(RegList[RegIdx++])); in CC_ARM_AAPCS_Custom_Aggregate()
265 State.AllocateReg(Reg); in CC_ARM_AAPCS_Custom_Aggregate()
290 MCRegister Reg = State.AllocateReg(RegList); in CustomAssignInRegList()
H A DARMISelLowering.cpp3037 MCRegister Reg = State->AllocateReg(GPRArgRegs); in HandleByVal()
3044 Reg = State->AllocateReg(GPRArgRegs); in HandleByVal()
3057 while (State->AllocateReg(GPRArgRegs)) in HandleByVal()
3074 State->AllocateReg(GPRArgRegs); in HandleByVal()
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86CallingConv.cpp53 MCRegister Reg = State.AllocateReg(AvailableRegs[I]); in CC_X86_32_RegCall_Assign2Regs()
104 MCRegister AssigedReg = State.AllocateReg(Reg); in CC_X86_VectorCallAssignRegister()
149 (void)State.AllocateReg(CC_X86_VectorCallGetSSEs(ValVT)); in CC_X86_64_VectorCall()
157 (void)State.AllocateReg(CC_X86_64_VectorCallGetGPRs()); in CC_X86_64_VectorCall()
160 if (MCRegister Reg = State.AllocateReg(CC_X86_VectorCallGetSSEs(ValVT))) { in CC_X86_64_VectorCall()
211 if (MCRegister Reg = State.AllocateReg(CC_X86_VectorCallGetSSEs(ValVT))) { in CC_X86_32_VectorCall()
261 if (MCRegister Reg = State.AllocateReg(RegList)) { in CC_X86_32_MCUInReg()
282 It.convertToReg(State.AllocateReg(RegList[FirstFree++])); in CC_X86_32_MCUInReg()
/freebsd/contrib/llvm-project/llvm/lib/Target/M68k/
H A DM68kCallingConv.h65 IsPtr ? State.AllocateReg(AddrRegList) : State.AllocateReg(DataRegList); in CC_M68k_Any_AssignToReg()
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUCallLowering.cpp458 CCInfo.AllocateReg(PrivateSegmentBufferReg); in allocateHSAUserSGPRs()
464 CCInfo.AllocateReg(DispatchPtrReg); in allocateHSAUserSGPRs()
470 CCInfo.AllocateReg(QueuePtrReg); in allocateHSAUserSGPRs()
481 CCInfo.AllocateReg(InputPtrReg); in allocateHSAUserSGPRs()
487 CCInfo.AllocateReg(DispatchIDReg); in allocateHSAUserSGPRs()
493 CCInfo.AllocateReg(FlatScratchInitReg); in allocateHSAUserSGPRs()
499 CCInfo.AllocateReg(PrivateSegmentSizeReg); in allocateHSAUserSGPRs()
612 CCInfo.AllocateReg(ImplicitBufferPtrReg); in lowerFormalArguments()
619 CCInfo.AllocateReg(FlatScratchInitReg); in lowerFormalArguments()
688 CCInfo.AllocateReg(AMDGPU::VGPR0); in lowerFormalArguments()
[all …]
H A DSIISelLowering.cpp2355 CCInfo.AllocateReg(Reg); in allocateSpecialEntryInputVGPRs()
2370 CCInfo.AllocateReg(Reg); in allocateSpecialEntryInputVGPRs()
2384 CCInfo.AllocateReg(Reg); in allocateSpecialEntryInputVGPRs()
2409 Reg = CCInfo.AllocateReg(Reg); in allocateVGPR32Input()
2427 Reg = CCInfo.AllocateReg(Reg); in allocateSGPR32InputImpl()
2441 Reg = CCInfo.AllocateReg(Reg); in allocateFixedSGPRInputImpl()
2489 Register Reg = CCInfo.AllocateReg(AMDGPU::VGPR31); in allocateSpecialInputVGPRsFixed()
2544 CCInfo.AllocateReg(ImplicitBufferPtrReg); in allocateHSAUserSGPRs()
2551 CCInfo.AllocateReg(PrivateSegmentBufferReg); in allocateHSAUserSGPRs()
2557 CCInfo.AllocateReg(DispatchPtrReg); in allocateHSAUserSGPRs()
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/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64CallingConvention.cpp66 State.AllocateReg(ZRegList[I]); in finishStackBlock()
72 State.AllocateReg(PRegList[I]); in finishStackBlock()
208 State.AllocateReg(Reg); in CC_AArch64_Custom_Block()
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DCallingConvLower.h332 MCRegister AllocateReg(MCPhysReg Reg) { in AllocateReg() function
340 MCRegister AllocateReg(MCPhysReg Reg, MCPhysReg ShadowReg) { in AllocateReg() function
351 MCRegister AllocateReg(ArrayRef<MCPhysReg> Regs) { in AllocateReg() function
393 MCRegister AllocateReg(ArrayRef<MCPhysReg> Regs, const MCPhysReg *ShadowRegs) { in AllocateReg() function
/freebsd/contrib/llvm-project/llvm/lib/Target/Xtensa/
H A DXtensaISelLowering.cpp355 while (State.AllocateReg(IntRegs)) in CC_Xtensa_Custom()
378 Register = State.AllocateReg(IntRegs); in CC_Xtensa_Custom()
383 Register = State.AllocateReg(IntRegs); in CC_Xtensa_Custom()
387 while ((Register = State.AllocateReg(IntRegs))) in CC_Xtensa_Custom()
392 Register = State.AllocateReg(IntRegs); in CC_Xtensa_Custom()
395 Register = State.AllocateReg(IntRegs); in CC_Xtensa_Custom()
396 State.AllocateReg(IntRegs); in CC_Xtensa_Custom()
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsISelLowering.cpp3101 Reg = State.AllocateReg(FloatVectorIntRegs); in CC_MipsO32()
3103 State.AllocateReg(Mips::A1); in CC_MipsO32()
3105 State.AllocateReg(Mips::A3); in CC_MipsO32()
3109 Reg = State.AllocateReg(IntRegs); in CC_MipsO32()
3113 Reg = State.AllocateReg(IntRegs); in CC_MipsO32()
3117 Reg = State.AllocateReg(IntRegs); in CC_MipsO32()
3122 Reg = State.AllocateReg(IntRegs); in CC_MipsO32()
3124 Reg = State.AllocateReg(IntRegs); in CC_MipsO32()
3131 MCRegister HiReg = State.AllocateReg(IntRegs); in CC_MipsO32()
3140 Reg = State.AllocateReg(F32Regs); in CC_MipsO32()
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/freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchISelLowering.cpp6663 if (Register Reg = State.AllocateReg(ArgGPRs)) { in CC_LoongArchAssign2GRLen()
6680 if (Register Reg = State.AllocateReg(ArgGPRs)) { in CC_LoongArchAssign2GRLen()
6739 State.AllocateReg(ArgGPRs); in CC_LoongArch()
6767 MCRegister Reg = State.AllocateReg(ArgGPRs); in CC_LoongArch()
6776 MCRegister HiReg = State.AllocateReg(ArgGPRs); in CC_LoongArch()
6822 Reg = State.AllocateReg(ArgFPR32s); in CC_LoongArch()
6824 Reg = State.AllocateReg(ArgFPR64s); in CC_LoongArch()
6826 Reg = State.AllocateReg(ArgVRs); in CC_LoongArch()
6828 Reg = State.AllocateReg(ArgXRs); in CC_LoongArch()
6830 Reg = State.AllocateReg(ArgGPRs); in CC_LoongArch()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/AVR/
H A DAVRISelLowering.cpp1237 Reg = CCInfo.AllocateReg(RegList8[RegIdx]); in analyzeArguments()
1239 Reg = CCInfo.AllocateReg(RegList16[RegIdx]); in analyzeArguments()
1307 Reg = CCInfo.AllocateReg(RegList8[RegIdx]); in analyzeReturnValues()
1309 Reg = CCInfo.AllocateReg(RegList16[RegIdx]); in analyzeReturnValues()
/freebsd/contrib/llvm-project/llvm/lib/Target/MSP430/
H A DMSP430ISelLowering.cpp409 MCRegister Reg = State.AllocateReg(RegList); in AnalyzeArguments()
417 MCRegister Reg = State.AllocateReg(RegList); in AnalyzeArguments()
/freebsd/contrib/llvm-project/llvm/lib/Target/Sparc/
H A DSparcISelLowering.cpp67 if (Register Reg = State.AllocateReg(RegList)) { in CC_Sparc_Assign_Split_64()
77 if (Register Reg = State.AllocateReg(RegList)) in CC_Sparc_Assign_Split_64()
94 if (Register Reg = State.AllocateReg(RegList)) in CC_Sparc_Assign_Ret_Split_64()
100 if (Register Reg = State.AllocateReg(RegList)) in CC_Sparc_Assign_Ret_Split_64()
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelLowering.cpp150 State.AllocateReg(ArgRegs[RegNum]); in CC_SkipOdd()