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Searched refs:AfterLegalizeVectorOps (Results 1 – 6 of 6) sorted by relevance

/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DDAGCombine.h18 AfterLegalizeVectorOps, enumerator
H A DTargetLowering.h4391 bool isBeforeLegalizeOps() const { return Level < AfterLegalizeVectorOps; } in isBeforeLegalizeOps()
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DR600ISelLowering.cpp815 DAGCombinerInfo DCI(DAG, AfterLegalizeVectorOps, true, nullptr); in LowerSELECT_CC()
H A DSIISelLowering.cpp7829 DAGCombinerInfo DCI(DAG, AfterLegalizeVectorOps, true, nullptr); in lowerEXTRACT_VECTOR_ELT()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DDAGCombiner.cpp1787 LegalOperations = Level >= AfterLegalizeVectorOps; in Run()
4701 (!VT.isVector() || Level <= AfterLegalizeVectorOps)) { in visitMUL()
16121 if (Level == AfterLegalizeVectorOps && VT.isVector() && in visitTRUNCATE()
23433 if (Level != AfterLegalizeVectorOps && Level != AfterLegalizeTypes) in refineExtractVectorEltIntoMultipleNarrowExtractVectorElts()
23947 if (Level != AfterLegalizeVectorOps && Level != AfterLegalizeTypes) in reduceBuildVecExtToExtBuildVec()
25376 if (Level <= AfterLegalizeVectorOps && TLI.isTypeLegal(VT)) { in visitCONCAT_VECTORS()
27010 Level < AfterLegalizeVectorOps && in visitVECTOR_SHUFFLE()
27046 if (Level < AfterLegalizeVectorOps && TLI.isTypeLegal(VT) && in visitVECTOR_SHUFFLE()
27169 N1.isUndef() && Level < AfterLegalizeVectorOps && in visitVECTOR_SHUFFLE()
H A DSelectionDAGISel.cpp1047 CurDAG->Combine(AfterLegalizeVectorOps, getBatchAA(), OptLevel); in CodeGenAndEmitDAG()