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Searched refs:AddrIndexReg (Results 1 – 20 of 20) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86InsertPrefetch.cpp83 Register IndexReg = MI.getOperand(Op + X86::AddrIndexReg).getReg(); in IsMemOpCompatibleWithPrefetch()
224 X86::AddrIndexReg == 2 && X86::AddrDisp == 3 && in runOnMachineFunction()
235 Current->getOperand(MemOpOffset + X86::AddrIndexReg).getReg()) in runOnMachineFunction()
H A DX86LowerTileCopy.cpp141 MachineOperand *MO = &NewMI->getOperand(X86::AddrIndexReg); in runOnMachineFunction()
148 MO = &NewMI->getOperand(1 + X86::AddrIndexReg); in runOnMachineFunction()
H A DX86FixupLEAs.cpp458 Register IndexReg = LeaI->getOperand(1 + X86::AddrIndexReg).getReg(); in checkRegUsage()
507 Register IndexReg = I->getOperand(1 + X86::AddrIndexReg).getReg(); in optLEAALU()
555 const MachineOperand &Index = MI.getOperand(1 + X86::AddrIndexReg); in optTwoAddrLEA()
660 MachineOperand &q = MI.getOperand(AddrOffset + X86::AddrIndexReg); in processInstruction()
695 const MachineOperand &Index = MI.getOperand(1 + X86::AddrIndexReg); in processInstructionForSlowLEA()
747 const MachineOperand &Index = MI.getOperand(1 + X86::AddrIndexReg); in processInstrForSlow3OpLEA()
H A DX86AsmPrinter.cpp421 const MachineOperand &IndexReg = MI->getOperand(OpNo + X86::AddrIndexReg); in PrintLeaMemReference()
460 PrintModifiedOperand(MI, OpNo + X86::AddrIndexReg, O, Modifier); in PrintLeaMemReference()
517 const MachineOperand &IndexReg = MI->getOperand(OpNo + X86::AddrIndexReg); in PrintIntelMemReference()
549 PrintOperand(MI, OpNo + X86::AddrIndexReg, O); in PrintIntelMemReference()
H A DX86OptimizeLEAs.cpp196 &MI.getOperand(N + X86::AddrIndexReg), in getMemOpKey()
560 MI.getOperand(MemOpNo + X86::AddrIndexReg) in removeRedundantAddrCalc()
H A DX86ExpandPseudo.cpp677 MIBLo.getInstr()->getOperand(1 + X86::AddrIndexReg); in expandMI()
723 MachineOperand &Stride = MIBLo.getInstr()->getOperand(X86::AddrIndexReg); in expandMI()
926 Register Index = MI.getOperand(MemOpNo + X86::AddrIndexReg).getReg(); in expandMI()
H A DX86CallFrameOptimization.cpp429 (I->getOperand(X86::AddrIndexReg).getReg() != X86::NoRegister) || in collectCallInfo()
H A DX86SpeculativeLoadHardening.cpp1331 MI.getOperand(MemRefBeginIdx + X86::AddrIndexReg); in tracePredStateThroughBlocksAndHarden()
1402 MI.getOperand(MemRefBeginIdx + X86::AddrIndexReg); in tracePredStateThroughBlocksAndHarden()
1802 UseMI.getOperand(MemRefBeginIdx + X86::AddrIndexReg); in sinkPostLoadHardenedInst()
H A DX86InstrInfo.h163 MI.getOperand(Op + X86::AddrIndexReg).isReg() && in isLeaMem()
H A DX86AvoidStoreForwardingBlocks.cpp316 const MachineOperand &Index = MI->getOperand(AddrOffset + X86::AddrIndexReg); in isRelevantAddressingMode()
H A DX86InstrInfo.cpp466 MI.getOperand(Op + X86::AddrIndexReg).isReg() && in isFrameOperand()
469 MI.getOperand(Op + X86::AddrIndexReg).getReg() == 0 && in isFrameOperand()
916 MI.getOperand(1 + X86::AddrIndexReg).isReg() && in isReallyTriviallyReMaterializable()
917 MI.getOperand(1 + X86::AddrIndexReg).getReg() == 0 && in isReallyTriviallyReMaterializable()
936 MI.getOperand(1 + X86::AddrIndexReg).isReg() && in isReallyTriviallyReMaterializable()
937 MI.getOperand(1 + X86::AddrIndexReg).getReg() == 0 && in isReallyTriviallyReMaterializable()
3667 const MachineOperand &Index = MI.getOperand(OpNo + X86::AddrIndexReg); in getConstantFromPool()
4574 AM.ScaledReg = MemI.getOperand(MemRefBegin + X86::AddrIndexReg).getReg(); in getAddrModeFromMemoryOp()
4698 if (MemOp.getOperand(MemRefBegin + X86::AddrIndexReg).getReg() != in getMemOperandsWithOffsetWidth()
4767 MachineOperand &MO = NewMI->getOperand(X86::AddrIndexReg); in loadStoreTileReg()
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H A DX86LoadValueInjectionLoadHardening.cpp781 MI.getOperand(MemRefBeginIdx + X86::AddrIndexReg); in instrUsesRegToAccessMemory()
H A DX86FastISel.cpp220 X86::AddrIndexReg); in addFullAddress()
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/MCTargetDesc/
H A DX86MCCodeEmitter.cpp623 const MCOperand &IndexReg = MI.getOperand(Op + X86::AddrIndexReg); in emitMemModRMByte()
1082 Prefix.setXX2(MI, MemOperand + X86::AddrIndexReg); in emitVEXOpcodePrefix()
1101 Prefix.setXX2(MI, MemOperand + X86::AddrIndexReg); in emitVEXOpcodePrefix()
1102 Prefix.setV2(MI, MemOperand + X86::AddrIndexReg, HasVEX_4V); in emitVEXOpcodePrefix()
1148 Prefix.setXX2(MI, MemOperand + X86::AddrIndexReg); in emitVEXOpcodePrefix()
1149 Prefix.setV2(MI, MemOperand + X86::AddrIndexReg, HasVEX_4V); in emitVEXOpcodePrefix()
1162 Prefix.setXX2(MI, MemOperand + X86::AddrIndexReg); in emitVEXOpcodePrefix()
1171 Prefix.setXX2(MI, MemOperand + X86::AddrIndexReg); in emitVEXOpcodePrefix()
1193 Prefix.setXX2(MI, MemOperand + X86::AddrIndexReg); in emitVEXOpcodePrefix()
1194 Prefix.setV2(MI, MemOperand + X86::AddrIndexReg, HasVEX_4V); in emitVEXOpcodePrefix()
[all …]
H A DX86MCTargetDesc.cpp79 const MCOperand &Index = MI.getOperand(Op + X86::AddrIndexReg); in isMemOperand()
89 const MCOperand &Index = MI.getOperand(Op + X86::AddrIndexReg); in is16BitMemOperand()
99 const MCOperand &Index = MI.getOperand(Op + X86::AddrIndexReg); in is32BitMemOperand()
665 const MCOperand &IndexReg = Inst.getOperand(MemOpStart + X86::AddrIndexReg); in evaluateMemoryOperandAddress()
691 const MCOperand &IndexReg = Inst.getOperand(MemOpStart + X86::AddrIndexReg); in getMemoryOperandRelocationOffset()
H A DX86IntelInstPrinter.cpp393 const MCOperand &IndexReg = MI->getOperand(Op+X86::AddrIndexReg); in printMemReference()
412 printOperand(MI, Op+X86::AddrIndexReg, O); in printMemReference()
H A DX86ATTInstPrinter.cpp451 const MCOperand &IndexReg = MI->getOperand(Op + X86::AddrIndexReg); in printMemReference()
475 printOperand(MI, Op + X86::AddrIndexReg, O); in printMemReference()
H A DX86EncodingOptimization.cpp383 MI.getOperand(AddrBase + X86::AddrIndexReg).getReg())) in optimizeMOV()
H A DX86BaseInfo.h31 AddrIndexReg = 2, enumerator
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/AsmParser/
H A DX86AsmParser.cpp3957 Inst.getOperand(4 + X86::AddrIndexReg).getReg()); in validateInstruction()
3965 Inst.getOperand(3 + X86::AddrIndexReg).getReg()); in validateInstruction()