Searched refs:AddrIdx (Results 1 – 4 of 4) sorted by relevance
| /freebsd/contrib/llvm-project/llvm/lib/Target/Mips/MCTargetDesc/ |
| H A D | MipsNaClELFStreamer.cpp | 124 void sandboxLoadStoreStackChange(const MCInst &MI, unsigned AddrIdx, in sandboxLoadStoreStackChange() argument
130 unsigned BaseReg = MI.getOperand(AddrIdx).getReg(); in sandboxLoadStoreStackChange()
157 unsigned AddrIdx = 0; in emitInstruction() local
159 bool IsMemAccess = isBasePlusOffsetMemoryAccess(Inst.getOpcode(), &AddrIdx, in emitInstruction()
164 && baseRegNeedsLoadStoreMask(Inst.getOperand(AddrIdx) in emitInstruction()
170 sandboxLoadStoreStackChange(Inst, AddrIdx, STI, MaskBefore, MaskAfter); in emitInstruction()
210 bool isBasePlusOffsetMemoryAccess(unsigned Opcode, unsigned *AddrIdx, in isBasePlusOffsetMemoryAccess() argument
231 *AddrIdx = 1; in isBasePlusOffsetMemoryAccess()
242 *AddrIdx = 1; in isBasePlusOffsetMemoryAccess()
250 *AddrIdx = 2; in isBasePlusOffsetMemoryAccess()
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| H A D | MipsMCNaCl.h | 20 bool isBasePlusOffsetMemoryAccess(unsigned Opcode, unsigned *AddrIdx,
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SILoadStoreOptimizer.cpp | 120 int AddrIdx[MaxAddressRegs]; member
131 const MachineOperand &AddrRegNext = MI.getOperand(AddrIdx[i]); in hasSameBaseAddress()
822 AddrIdx[NumAddresses++] = in setMI()
825 AddrIdx[NumAddresses++] = in setMI()
828 AddrIdx[NumAddresses++] = in setMI()
831 AddrIdx[NumAddresses++] = AMDGPU::getNamedOperandIdx( in setMI()
834 AddrIdx[NumAddresses++] = in setMI()
837 AddrIdx[NumAddresses++] = in setMI()
840 AddrIdx[NumAddresses++] = in setMI()
843 AddrIdx[NumAddresses++] = AMDGPU::getNamedOperandIdx( in setMI()
[all …]
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsDelaySlotFiller.cpp | 737 unsigned AddrIdx; in searchRange() local
738 if ((isBasePlusOffsetMemoryAccess(CurrI->getOpcode(), &AddrIdx) && in searchRange()
739 baseRegNeedsLoadStoreMask(CurrI->getOperand(AddrIdx).getReg())) || in searchRange()
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