Home
last modified time | relevance | path

Searched refs:AddrBaseReg (Results 1 – 19 of 19) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86InsertPrefetch.cpp82 Register BaseReg = MI.getOperand(Op + X86::AddrBaseReg).getReg(); in IsMemOpCompatibleWithPrefetch()
223 static_assert(X86::AddrBaseReg == 0 && X86::AddrScaleAmt == 1 && in runOnMachineFunction()
231 MIB.addReg(Current->getOperand(MemOpOffset + X86::AddrBaseReg).getReg()) in runOnMachineFunction()
H A DX86OptimizeLEAs.cpp194 return MemOpKey(&MI.getOperand(N + X86::AddrBaseReg), in getMemOpKey()
363 if (TII->getRegClass(Desc, MemOpNo + X86::AddrBaseReg, TRI, *MF) != in chooseBestLEA()
458 if (!isIdenticalOp(MI.getOperand(MemOpNo + X86::AddrBaseReg), MO)) in isReplaceable()
464 if (i != (unsigned)(MemOpNo + X86::AddrBaseReg) && in isReplaceable()
557 MI.getOperand(MemOpNo + X86::AddrBaseReg) in removeRedundantAddrCalc()
H A DX86FixupLEAs.cpp457 Register BaseReg = LeaI->getOperand(1 + X86::AddrBaseReg).getReg(); in checkRegUsage()
506 Register BaseReg = I->getOperand(1 + X86::AddrBaseReg).getReg(); in optLEAALU()
553 const MachineOperand &Base = MI.getOperand(1 + X86::AddrBaseReg); in optTwoAddrLEA()
656 MachineOperand &p = MI.getOperand(AddrOffset + X86::AddrBaseReg); in processInstruction()
693 const MachineOperand &Base = MI.getOperand(1 + X86::AddrBaseReg); in processInstructionForSlowLEA()
745 const MachineOperand &Base = MI.getOperand(1 + X86::AddrBaseReg); in processInstrForSlow3OpLEA()
H A DX86AsmPrinter.cpp420 const MachineOperand &BaseReg = MI->getOperand(OpNo + X86::AddrBaseReg); in PrintLeaMemReference()
456 PrintModifiedOperand(MI, OpNo + X86::AddrBaseReg, O, Modifier); in PrintLeaMemReference()
515 const MachineOperand &BaseReg = MI->getOperand(OpNo + X86::AddrBaseReg); in PrintIntelMemReference()
541 PrintOperand(MI, OpNo + X86::AddrBaseReg, O); in PrintIntelMemReference()
H A DX86CallFrameOptimization.cpp425 if (!I->getOperand(X86::AddrBaseReg).isReg() || in collectCallInfo()
426 (I->getOperand(X86::AddrBaseReg).getReg() != StackPtr) || in collectCallInfo()
H A DX86SpeculativeLoadHardening.cpp1329 MI.getOperand(MemRefBeginIdx + X86::AddrBaseReg); in tracePredStateThroughBlocksAndHarden()
1400 MI.getOperand(MemRefBeginIdx + X86::AddrBaseReg); in tracePredStateThroughBlocksAndHarden()
1800 UseMI.getOperand(MemRefBeginIdx + X86::AddrBaseReg); in sinkPostLoadHardenedInst()
H A DX86InstrInfo.h161 MI.getOperand(Op + X86::AddrBaseReg).isReg() && in isLeaMem()
H A DX86AvoidStoreForwardingBlocks.cpp300 return MI->getOperand(AddrOffset + X86::AddrBaseReg); in getBaseOperand()
H A DX86LoadValueInjectionLoadHardening.cpp779 MI.getOperand(MemRefBeginIdx + X86::AddrBaseReg); in instrUsesRegToAccessMemory()
H A DX86InstrInfo.cpp464 if (MI.getOperand(Op + X86::AddrBaseReg).isFI() && in isFrameOperand()
471 FrameIndex = MI.getOperand(Op + X86::AddrBaseReg).getIndex(); in isFrameOperand()
914 if (MI.getOperand(1 + X86::AddrBaseReg).isReg() && in isReallyTriviallyReMaterializable()
919 Register BaseReg = MI.getOperand(1 + X86::AddrBaseReg).getReg(); in isReallyTriviallyReMaterializable()
940 if (!MI.getOperand(1 + X86::AddrBaseReg).isReg()) in isReallyTriviallyReMaterializable()
942 Register BaseReg = MI.getOperand(1 + X86::AddrBaseReg).getReg(); in isReallyTriviallyReMaterializable()
4563 auto &BaseOp = MemI.getOperand(MemRefBegin + X86::AddrBaseReg); in getAddrModeFromMemoryOp()
4691 &MemOp.getOperand(MemRefBegin + X86::AddrBaseReg); in getMemOperandsWithOffsetWidth()
8853 if (!HasSameOp(X86::AddrBaseReg) || !HasSameOp(X86::AddrScaleAmt) || in areLoadsFromSameBasePtr()
H A DX86ExpandPseudo.cpp921 Register Base = MI.getOperand(MemOpNo + X86::AddrBaseReg).getReg(); in expandMI()
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/MCTargetDesc/
H A DX86MCCodeEmitter.cpp621 const MCOperand &Base = MI.getOperand(Op + X86::AddrBaseReg); in emitMemModRMByte()
1081 Prefix.setBB2(MI, MemOperand + X86::AddrBaseReg); in emitVEXOpcodePrefix()
1100 Prefix.setBB2(MI, MemOperand + X86::AddrBaseReg); in emitVEXOpcodePrefix()
1147 Prefix.setBB2(MI, MemOperand + X86::AddrBaseReg); in emitVEXOpcodePrefix()
1161 Prefix.setBB2(MI, MemOperand + X86::AddrBaseReg); in emitVEXOpcodePrefix()
1170 Prefix.setBB2(MI, MemOperand + X86::AddrBaseReg); in emitVEXOpcodePrefix()
1192 Prefix.setBB2(MI, MemOperand + X86::AddrBaseReg); in emitVEXOpcodePrefix()
1410 Prefix.setBB2(MI, MemOperand + X86::AddrBaseReg); in emitREXPrefix()
1419 Prefix.setBB2(MI, MemOperand + X86::AddrBaseReg); in emitREXPrefix()
1434 Prefix.setBB2(MI, MemOperand + X86::AddrBaseReg); in emitREXPrefix()
H A DX86MCTargetDesc.cpp78 const MCOperand &Base = MI.getOperand(Op + X86::AddrBaseReg); in isMemOperand()
88 const MCOperand &Base = MI.getOperand(Op + X86::AddrBaseReg); in is16BitMemOperand()
98 const MCOperand &Base = MI.getOperand(Op + X86::AddrBaseReg); in is32BitMemOperand()
664 const MCOperand &BaseReg = Inst.getOperand(MemOpStart + X86::AddrBaseReg); in evaluateMemoryOperandAddress()
690 const MCOperand &BaseReg = Inst.getOperand(MemOpStart + X86::AddrBaseReg); in getMemoryOperandRelocationOffset()
H A DX86IntelInstPrinter.cpp391 const MCOperand &BaseReg = MI->getOperand(Op+X86::AddrBaseReg); in printMemReference()
404 printOperand(MI, Op+X86::AddrBaseReg, O); in printMemReference()
H A DX86ATTInstPrinter.cpp450 const MCOperand &BaseReg = MI->getOperand(Op + X86::AddrBaseReg); in printMemReference()
471 printOperand(MI, Op + X86::AddrBaseReg, O); in printMemReference()
H A DX86AsmBackend.cpp256 unsigned BaseRegNum = MemoryOperand + CurOp + X86::AddrBaseReg; in isRIPRelative()
332 unsigned BaseRegNum = MemoryOperand + X86::AddrBaseReg; in determinePaddingPrefix()
H A DX86EncodingOptimization.cpp381 if (Absolute && (MI.getOperand(AddrBase + X86::AddrBaseReg).getReg() || in optimizeMOV()
H A DX86BaseInfo.h29 AddrBaseReg = 0, enumerator
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/AsmParser/
H A DX86AsmParser.cpp4007 const MCOperand &MO = Inst.getOperand(X86::AddrBaseReg); in validateInstruction()