Searched refs:AddSubOpc (Results 1 – 6 of 6) sorted by relevance
| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | MLxExpansionPass.cpp | 68 unsigned MulOpc, unsigned AddSubOpc,
270 unsigned MulOpc, unsigned AddSubOpc, in ExpandFPMLxInstruction() argument
285 const MCInstrDesc &MCID2 = TII->get(AddSubOpc); in ExpandFPMLxInstruction()
354 unsigned MulOpc, AddSubOpc; in ExpandFPMLxInstructions() local
357 MulOpc, AddSubOpc, NegAcc, HasLane) || in ExpandFPMLxInstructions()
361 ExpandFPMLxInstruction(MBB, MI, MulOpc, AddSubOpc, NegAcc, HasLane); in ExpandFPMLxInstructions()
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| H A D | ARMBaseInstrInfo.h | 515 unsigned &AddSubOpc, bool &NegAcc,
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| H A D | ARMBaseInstrInfo.cpp | 88 uint16_t AddSubOpc; // Expanded add / sub opcode member
122 MLxHazardOpcodes.insert(ARM_MLxTable[i].AddSubOpc); in ARMBaseInstrInfo()
5007 unsigned &AddSubOpc, in isFpMLxInstruction() argument
5015 AddSubOpc = Entry.AddSubOpc; in isFpMLxInstruction()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64PostLegalizerCombiner.cpp | 185 unsigned ShiftAmt, AddSubOpc; in matchAArch64MulConstCombine() local
199 AddSubOpc = TargetOpcode::G_ADD; in matchAArch64MulConstCombine()
202 AddSubOpc = TargetOpcode::G_SUB; in matchAArch64MulConstCombine()
212 AddSubOpc = TargetOpcode::G_SUB; in matchAArch64MulConstCombine()
216 AddSubOpc = TargetOpcode::G_ADD; in matchAArch64MulConstCombine()
231 auto Res = B.buildInstr(AddSubOpc, {Ty}, {AddSubLHS, AddSubRHS}); in matchAArch64MulConstCombine()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 14065 unsigned AddSubOpc; in performMULCombine()
14072 AddSubOpc = V->getOpcode(); in performMULCombine()
14073 if ((AddSubOpc == ISD::ADD || AddSubOpc == ISD::SUB) && V->hasOneUse()) { in performMULCombine()
14076 if (AddSubOpc == ISD::SUB) in performMULCombine()
14086 return DAG.getNode(AddSubOpc, DL, VT, N1, MulVal); in performMULCombine()
14091 return DAG.getNode(AddSubOpc, DL, VT, N0, MulVal); in performMULCombine()
14062 unsigned AddSubOpc; performMULCombine() local
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 18265 unsigned AddSubOpc; in performMulCombine() local
18268 AddSubOpc = V->getOpcode(); in performMulCombine()
18269 if ((AddSubOpc == ISD::ADD || AddSubOpc == ISD::SUB) && V->hasOneUse()) { in performMulCombine()
18272 if (AddSubOpc == ISD::SUB) in performMulCombine()
18282 return DAG.getNode(AddSubOpc, DL, VT, N1, MulVal); in performMulCombine()
18287 return DAG.getNode(AddSubOpc, DL, VT, N0, MulVal); in performMulCombine()
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