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Searched refs:AddSub (Results 1 – 10 of 10) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/X86/MCTargetDesc/
H A DX86BaseInfo.h111 AddSub, // ADD, SUB enumerator
237 return FirstMacroFusionInstKind::AddSub; in classifyFirstOpcodeInMacroFusion()
297 case X86::FirstMacroFusionInstKind::AddSub: in isMacroFused()
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMISelDAGToDAG.cpp728 ARM_AM::AddrOpc AddSub = ARM_AM::add; in SelectLdStSOReg() local
730 AddSub = ARM_AM::sub; in SelectLdStSOReg()
736 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt, in SelectLdStSOReg()
759 ARM_AM::AddrOpc AddSub = N.getOpcode() == ISD::SUB ? ARM_AM::sub:ARM_AM::add; in SelectLdStSOReg() local
822 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt, ShOpcVal), in SelectLdStSOReg()
833 ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC) in SelectAddrMode2OffsetReg() local
858 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt, ShOpcVal), in SelectAddrMode2OffsetReg()
869 ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC) in SelectAddrMode2OffsetImmPre() local
873 if (AddSub == ARM_AM::sub) Val *= -1; in SelectAddrMode2OffsetImmPre()
889 ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC) in SelectAddrMode2OffsetImm() local
[all …]
H A DARMLoadStoreOptimizer.cpp1519 ARM_AM::AddrOpc AddSub = Offset < 0 ? ARM_AM::sub : ARM_AM::add; in MergeBaseUpdateLoadStore() local
1553 int Imm = ARM_AM::getAM2Opc(AddSub, abs(Offset), ARM_AM::no_shift); in MergeBaseUpdateLoadStore()
1583 int Imm = ARM_AM::getAM2Opc(AddSub, abs(Offset), ARM_AM::no_shift); in MergeBaseUpdateLoadStore()
2300 ARM_AM::AddrOpc AddSub = ARM_AM::add; in CanFormLdStDWord() local
2302 AddSub = ARM_AM::sub; in CanFormLdStDWord()
2308 Offset = ARM_AM::getAM3Opc(AddSub, OffImm); in CanFormLdStDWord()
/freebsd/contrib/llvm-project/llvm/lib/Transforms/InstCombine/
H A DInstCombineCalls.cpp1185 BinaryOperator *AddSub; in matchSAddSubSat() local
1188 if (!match(MinMax2, m_SMax(m_BinOp(AddSub), m_APInt(MinValue)))) in matchSAddSubSat()
1192 if (!match(MinMax2, m_SMin(m_BinOp(AddSub), m_APInt(MaxValue)))) in matchSAddSubSat()
1209 if (!MinMax2->hasOneUse() || !AddSub->hasOneUse()) in matchSAddSubSat()
1216 if (AddSub->getOpcode() == Instruction::Add) in matchSAddSubSat()
1218 else if (AddSub->getOpcode() == Instruction::Sub) in matchSAddSubSat()
1225 if (ComputeMaxSignificantBits(AddSub->getOperand(0), AddSub) > NewBitWidth || in matchSAddSubSat()
1226 ComputeMaxSignificantBits(AddSub->getOperand(1), AddSub) > NewBitWidth) in matchSAddSubSat()
1230 Value *AT = Builder.CreateTrunc(AddSub->getOperand(0), NewTy); in matchSAddSubSat()
1231 Value *BT = Builder.CreateTrunc(AddSub->getOperand(1), NewTy); in matchSAddSubSat()
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/AsmParser/
H A DARMAsmParser.cpp3011 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add; in addAddrMode2Operands() local
3017 Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift); in addAddrMode2Operands()
3036 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add; in addAM2OffsetImmOperands() local
3040 Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift); in addAM2OffsetImmOperands()
3064 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add; in addAddrMode3Operands() local
3070 Val = ARM_AM::getAM3Opc(AddSub, Val); in addAddrMode3Operands()
3096 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add; in addAM3OffsetOperands() local
3100 Val = ARM_AM::getAM3Opc(AddSub, Val); in addAM3OffsetOperands()
3122 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add; in addAddrMode5Operands() local
3128 Val = ARM_AM::getAM5Opc(AddSub, Val); in addAddrMode5Operands()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DSVEInstrFormats.td293 def SVEAddSubImmOperand8 : SVEShiftedImmOperand<8, "AddSub", "isSVEAddSubImm<int8_t>">;
294 def SVEAddSubImmOperand16 : SVEShiftedImmOperand<16, "AddSub", "isSVEAddSubImm<int16_t>">;
295 def SVEAddSubImmOperand32 : SVEShiftedImmOperand<32, "AddSub", "isSVEAddSubImm<int32_t>">;
296 def SVEAddSubImmOperand64 : SVEShiftedImmOperand<64, "AddSub", "isSVEAddSubImm<int64_t>">;
H A DAArch64InstrInfo.td2632 defm ADD : AddSub<0, "add", "sub", add>;
2633 defm SUB : AddSub<1, "sub", "add">;
H A DAArch64InstrFormats.td3036 multiclass AddSub<bit isSub, string mnemonic, string alias,
/freebsd/contrib/llvm-project/llvm/lib/Transforms/Vectorize/
H A DSLPVectorizer.cpp1220 constexpr std::array<unsigned, 4> AddSub = { in isAddSubLikeOp() local
1223 return is_contained(AddSub, getOpcode()) && in isAddSubLikeOp()
1224 is_contained(AddSub, getAltOpcode()); in isAddSubLikeOp()
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp9284 if (SDValue AddSub = lowerToAddSubOrFMAddSub(BV, dl, Subtarget, DAG)) in LowerBUILD_VECTOR() local
9285 return AddSub; in LowerBUILD_VECTOR()
43360 if (SDValue AddSub = in combineShuffle() local
43362 return AddSub; in combineShuffle()