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Searched refs:AddMI (Results 1 – 7 of 7) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/MCTargetDesc/
H A DHexagonMCShuffler.cpp55 void HexagonMCShuffler::init(MCInst &MCB, MCInst const &AddMI, in init() argument
59 append(AddMI, nullptr, HexagonMCInstrInfo::getUnits(MCII, STI, AddMI)); in init()
72 append(AddMI, nullptr, HexagonMCInstrInfo::getUnits(MCII, STI, AddMI)); in init()
181 MCInst const &AddMI, int fixupCount) { in HexagonMCShuffle() argument
216 HexagonMCShuffler MCS(Context, false, MCII, STI, MCB, AddMI, false); in HexagonMCShuffle()
H A DHexagonMCShuffler.h40 MCInst &MCB, MCInst const &AddMI, bool InsertAtFront) in HexagonMCShuffler() argument
42 init(MCB, AddMI, InsertAtFront); in HexagonMCShuffler()
53 void init(MCInst &MCB, MCInst const &AddMI, bool InsertAtFront);
63 MCInst const &AddMI, int fixupCount);
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonOptAddrMode.cpp92 bool processAddBases(NodeAddr<StmtNode *> AddSN, MachineInstr *AddMI);
95 MachineInstr *AddMI,
101 bool processAddUses(NodeAddr<StmtNode *> AddSN, MachineInstr *AddMI,
103 bool updateAddUses(MachineInstr *AddMI, MachineInstr *UseMI);
465 MachineInstr *AddMI, in findFirstReachedInst() argument
480 MachineBasicBlock *CurrentMBB = AddMI->getParent(); in findFirstReachedInst()
522 MachineInstr *AddMI) { in processAddBases() argument
526 LLVM_DEBUG(dbgs() << "\n\t\t[Processing Addi]: " << *AddMI << "\n"); in processAddBases()
540 if (Processed(AddMI, ProcessedAddiInsts)) in processAddBases()
542 ProcessedAddiInsts.insert(AddMI); in processAddBases()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/Sparc/
H A DDelaySlotFiller.cpp394 MachineBasicBlock::iterator AddMI, in combineRestoreADD() argument
402 Register reg = AddMI->getOperand(0).getReg(); in combineRestoreADD()
410 AddMI->setDesc(TII->get((AddMI->getOpcode() == SP::ADDrr) in combineRestoreADD()
415 AddMI->getOperand(0).setReg(reg - SP::I0 + SP::O0); in combineRestoreADD()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64CollectLOH.cpp409 const MachineInstr *AddMI = Info.MI0; in handleADRP() local
411 int OpIdx = mapRegToGPRIndex(AddMI->getOperand(0).getReg()); in handleADRP()
H A DAArch64InstrInfo.cpp7730 MachineInstr *AddMI = MRI.getUniqueVRegDef(Root.getOperand(2).getReg()); in genSubAdd2SubSub() local
7735 Register RegB = AddMI->getOperand(IdxOpd1).getReg(); in genSubAdd2SubSub()
7736 bool RegBIsKill = AddMI->getOperand(IdxOpd1).isKill(); in genSubAdd2SubSub()
7737 Register RegC = AddMI->getOperand(IdxOtherOpd).getReg(); in genSubAdd2SubSub()
7738 bool RegCIsKill = AddMI->getOperand(IdxOtherOpd).isKill(); in genSubAdd2SubSub()
7751 uint32_t Flags = Root.mergeFlagsWith(*AddMI); in genSubAdd2SubSub()
7769 DelInstrs.push_back(AddMI); in genSubAdd2SubSub()
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVInstrInfo.cpp2557 const MachineInstr *AddMI = canCombine(MBB, Root.getOperand(2), RISCV::ADD); in getSHXADDPatterns() local
2558 if (!AddMI) in getSHXADDPatterns()
2562 if (canCombineShiftIntoShXAdd(MBB, AddMI->getOperand(1), ShiftAmt)) { in getSHXADDPatterns()
2566 if (canCombineShiftIntoShXAdd(MBB, AddMI->getOperand(2), ShiftAmt)) { in getSHXADDPatterns()
2692 MachineInstr *AddMI = MRI.getUniqueVRegDef(Root.getOperand(2).getReg()); in genShXAddAddShift() local
2694 MRI.getUniqueVRegDef(AddMI->getOperand(AddOpIdx).getReg()); in genShXAddAddShift()
2717 const MachineOperand &X = AddMI->getOperand(3 - AddOpIdx); in genShXAddAddShift()
2735 DelInstrs.push_back(AddMI); in genShXAddAddShift()