| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| H A D | HexagonMCShuffler.cpp | 55 void HexagonMCShuffler::init(MCInst &MCB, MCInst const &AddMI, in init() argument
59 append(AddMI, nullptr, HexagonMCInstrInfo::getUnits(MCII, STI, AddMI)); in init()
72 append(AddMI, nullptr, HexagonMCInstrInfo::getUnits(MCII, STI, AddMI)); in init()
181 MCInst const &AddMI, int fixupCount) { in HexagonMCShuffle() argument
216 HexagonMCShuffler MCS(Context, false, MCII, STI, MCB, AddMI, false); in HexagonMCShuffle()
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| H A D | HexagonMCShuffler.h | 40 MCInst &MCB, MCInst const &AddMI, bool InsertAtFront) in HexagonMCShuffler() argument
42 init(MCB, AddMI, InsertAtFront); in HexagonMCShuffler()
53 void init(MCInst &MCB, MCInst const &AddMI, bool InsertAtFront);
63 MCInst const &AddMI, int fixupCount);
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonOptAddrMode.cpp | 96 bool processAddUses(NodeAddr<StmtNode *> AddSN, MachineInstr *AddMI,
98 bool updateAddUses(MachineInstr *AddMI, MachineInstr *UseMI);
418 MachineInstr *AddMI, in processAddUses() argument
421 Register AddDefR = AddMI->getOperand(0).getReg(); in processAddUses()
422 Register BaseReg = AddMI->getOperand(1).getReg(); in processAddUses()
441 int64_t newOffset = OffsetOp.getImm() + AddMI->getOperand(2).getImm(); in processAddUses()
452 if (!isSafeToExtLR(AddSN, AddMI, BaseReg, UNodeList)) in processAddUses()
477 Changed |= updateAddUses(AddMI, UseMI); in processAddUses()
487 Deleted.insert(AddMI); in processAddUses()
492 bool HexagonOptAddrMode::updateAddUses(MachineInstr *AddMI, in updateAddUses() argument
[all …]
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64CollectLOH.cpp | 398 const MachineInstr *AddMI = Info.MI0; in handleADRP()
400 int OpIdx = mapRegToGPRIndex(AddMI->getOperand(0).getReg()); in handleADRP()
435 MachineInstr *AddMI = const_cast<MachineInstr *>(Info.MI1); in handleADRP()
437 auto AddIt = MachineBasicBlock::iterator(AddMI); in handleADRP()
438 auto EndIt = AddMI->getParent()->end(); in handleADRP()
439 if (AddMI->getIterator() == EndIt || LdrMI != &*next_nodbg(AddIt, EndIt)) in handleADRP() local
402 const MachineInstr *AddMI = Info.MI0; handleADRP() local
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| H A D | AArch64InstrInfo.cpp | 6935 MachineInstr *AddMI = MRI.getUniqueVRegDef(Root.getOperand(2).getReg()); in genSubAdd2SubSub() local
6940 Register RegB = AddMI->getOperand(IdxOpd1).getReg(); in genSubAdd2SubSub()
6941 bool RegBIsKill = AddMI->getOperand(IdxOpd1).isKill(); in genSubAdd2SubSub()
6942 Register RegC = AddMI->getOperand(IdxOtherOpd).getReg(); in genSubAdd2SubSub()
6943 bool RegCIsKill = AddMI->getOperand(IdxOtherOpd).isKill(); in genSubAdd2SubSub()
6955 uint32_t Flags = Root.mergeFlagsWith(*AddMI); in genSubAdd2SubSub()
6973 DelInstrs.push_back(AddMI); in genSubAdd2SubSub()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Sparc/ |
| H A D | DelaySlotFiller.cpp | 377 MachineBasicBlock::iterator AddMI, in combineRestoreADD() argument
385 Register reg = AddMI->getOperand(0).getReg(); in combineRestoreADD()
393 AddMI->setDesc(TII->get((AddMI->getOpcode() == SP::ADDrr) in combineRestoreADD()
398 AddMI->getOperand(0).setReg(reg - SP::I0 + SP::O0); in combineRestoreADD()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVInstrInfo.cpp | 2138 const MachineInstr *AddMI = canCombine(MBB, Root.getOperand(2), RISCV::ADD); in getSHXADDPatterns() local
2139 if (!AddMI) in getSHXADDPatterns()
2143 if (canCombineShiftIntoShXAdd(MBB, AddMI->getOperand(1), ShiftAmt)) { in getSHXADDPatterns()
2147 if (canCombineShiftIntoShXAdd(MBB, AddMI->getOperand(2), ShiftAmt)) { in getSHXADDPatterns()
2273 MachineInstr *AddMI = MRI.getUniqueVRegDef(Root.getOperand(2).getReg()); in genShXAddAddShift() local
2275 MRI.getUniqueVRegDef(AddMI->getOperand(AddOpIdx).getReg()); in genShXAddAddShift()
2298 const MachineOperand &X = AddMI->getOperand(3 - AddOpIdx); in genShXAddAddShift()
2316 DelInstrs.push_back(AddMI); in genShXAddAddShift()
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