Searched refs:Add2 (Results 1 – 4 of 4) sorted by relevance
| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | TargetLowering.cpp | 978 SDValue Add2; in combineShiftToAVG() local
985 Add2 = A; in combineShiftToAVG()
992 Add2 = A; in combineShiftToAVG()
1074 (!Add2 || DAG.willNotOverflowAdd(IsSigned, Add2.getOperand(0), in combineShiftToAVG()
1075 Add2.getOperand(1)))) in combineShiftToAVG()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| H A D | CombinerHelper.cpp | 1712 Register Add2 = MI.getOperand(1).getReg(); in matchPtrAddImmedChain() local
1718 MachineInstr *Add2Def = MRI.getVRegDef(Add2); in matchPtrAddImmedChain()
1749 unsigned AS = MRI.getType(Add2).getAddressSpace(); in matchPtrAddImmedChain()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPULegalizerInfo.cpp | 4593 auto Add2 = B.buildMergeLikeInstr(S64, {Add2_Lo, Add2_Hi}); in legalizeUnsignedDIV_REM64Impl() local
4599 auto MulHi3 = B.buildUMulH(S64, Numer, Add2); in legalizeUnsignedDIV_REM64Impl()
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| H A D | AMDGPUISelLowering.cpp | 2118 SDValue Add2 = DAG.getBitcast(VT, in LowerUDIVREM64() local
2121 SDValue Mulhi3 = DAG.getNode(ISD::MULHU, DL, VT, LHS, Add2); in LowerUDIVREM64()
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