| /freebsd/contrib/llvm-project/clang/include/clang/StaticAnalyzer/Core/PathSensitive/ |
| H A D | BasicValueFactory.h | 218 const llvm::APSInt &Add1(const llvm::APSInt &V) { in Add1() function
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | ExpandLargeFpConvert.cpp | 178 Value *Add1 = Builder.CreateAdd( in expandFPToI() local
182 Add1, ConstantInt::getSigned(IntTy, -static_cast<int64_t>(BitWidth))); in expandFPToI()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelDAGToDAG.cpp | 4306 SDValue Add1 = ShiftAmt->getOperand(1); in tryShiftAmountMod() local
4308 auto *Add1C = dyn_cast<ConstantSDNode>(Add1); in tryShiftAmountMod()
4330 Add0C == nullptr ? Add0 : Add1, AllOnes); in tryShiftAmountMod()
4340 X = Add1; in tryShiftAmountMod()
4345 if (Add1.getOpcode() == ISD::TRUNCATE) { in tryShiftAmountMod()
4346 Add1 = Add1.getOperand(0); in tryShiftAmountMod()
4347 SubVT = Add1.getValueType(); in tryShiftAmountMod()
4354 X = CurDAG->getNode(ISD::ADD, DL, SubVT, Add1, Add0); in tryShiftAmountMod()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelDAGToDAG.cpp | 3772 SDValue Add1 = ShiftAmt->getOperand(1); in tryShiftAmountMod() local
3775 if (isIntImmediate(Add1, Add1Imm) && (Add1Imm % Size == 0)) { in tryShiftAmountMod()
3798 CurDAG->getMachineNode(NegOpc, DL, SubVT, Zero, Add1); in tryShiftAmountMod()
3818 CurDAG->getMachineNode(NotOpc, DL, SubVT, Zero, Add1); in tryShiftAmountMod()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPULegalizerInfo.cpp | 4582 auto Add1 = B.buildMergeLikeInstr(S64, {Add1_Lo, Add1_Hi}); in legalizeUnsignedDIV_REM64Impl() local
4584 auto MulLo2 = B.buildMul(S64, NegDenom, Add1); in legalizeUnsignedDIV_REM64Impl()
4585 auto MulHi2 = B.buildUMulH(S64, Add1, MulLo2); in legalizeUnsignedDIV_REM64Impl()
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| H A D | AMDGPUISelLowering.cpp | 2105 SDValue Add1 = DAG.getBitcast(VT, in LowerUDIVREM64() local
2109 SDValue Mullo2 = DAG.getNode(ISD::MUL, DL, VT, Neg_RHS, Add1); in LowerUDIVREM64()
2110 SDValue Mulhi2 = DAG.getNode(ISD::MULHU, DL, VT, Add1, Mullo2); in LowerUDIVREM64()
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| H A D | SIISelLowering.cpp | 13641 SDValue Add1 = DAG.getNode(Opc, SL, VT, Op0, Op1); in reassociateScalarOps() local
13642 return DAG.getNode(Opc, SL, VT, Add1, Op2); in reassociateScalarOps()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsISelLowering.cpp | 1112 SDValue Add1 = DAG.getNode(ISD::ADD, DL, ValTy, N->getOperand(0), in performADDCombine() local
1114 return DAG.getNode(ISD::ADD, DL, ValTy, Add1, Lo); in performADDCombine()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 13613 SDValue Add1 = in TryDistrubutionADDVecReduce() local
13615 return DAG.getNode(ISD::ADD, dl, VT, Add1, N1.getOperand(N1RedOp)); in TryDistrubutionADDVecReduce()
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