| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/MCTargetDesc/ |
| H A D | ARMMCTargetDesc.cpp | 737 uint32_t Add1 = in findPltEntries() local
739 if ((Add1 & 0xe28fc600) != 0xe28fc600) in findPltEntries()
751 uint64_t Offset = (PltSectionVA + Byte + 8) + ((Add1 & 0xff) << 20) + in findPltEntries()
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| /freebsd/contrib/llvm-project/clang/include/clang/StaticAnalyzer/Core/PathSensitive/ |
| H A D | BasicValueFactory.h | 210 APSIntPtr Add1(const llvm::APSInt &V) { in Add1() function
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | ExpandFp.cpp | 180 Value *Add1 = Builder.CreateAdd( in expandFPToI() local
184 Add1, ConstantInt::getSigned(IntTy, -static_cast<int64_t>(BitWidth))); in expandFPToI()
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| /freebsd/contrib/llvm-project/llvm/lib/Transforms/InstCombine/ |
| H A D | InstCombineAddSub.cpp | 2854 Value *Z, *Add0, *Add1; in visitSub() local
2856 match(Op1, m_SExtLike(m_Value(Add1))) && in visitSub()
2858 match(Add1, m_c_NSWAdd(m_Specific(X), m_Value(Z)))) || in visitSub()
2860 match(Add1, m_c_NSWAdd(m_Specific(X), m_Value(Z)))))) { in visitSub()
2876 NumOfDeadInstrs += Add1->hasOneUse() ? 1 : 0; in visitSub()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelDAGToDAG.cpp | 4372 SDValue Add1 = ShiftAmt->getOperand(1); in tryShiftAmountMod() local
4374 auto *Add1C = dyn_cast<ConstantSDNode>(Add1); in tryShiftAmountMod()
4396 Add0C == nullptr ? Add0 : Add1, AllOnes); in tryShiftAmountMod()
4406 X = Add1; in tryShiftAmountMod()
4411 if (Add1.getOpcode() == ISD::TRUNCATE) { in tryShiftAmountMod()
4412 Add1 = Add1.getOperand(0); in tryShiftAmountMod()
4413 SubVT = Add1.getValueType(); in tryShiftAmountMod()
4420 X = CurDAG->getNode(ISD::ADD, DL, SubVT, Add1, Add0); in tryShiftAmountMod()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelDAGToDAG.cpp | 3874 SDValue Add1 = ShiftAmt->getOperand(1); in tryShiftAmountMod() local
3877 if (isIntImmediate(Add1, Add1Imm) && (Add1Imm % Size == 0)) { in tryShiftAmountMod()
3900 CurDAG->getMachineNode(NegOpc, DL, SubVT, Zero, Add1); in tryShiftAmountMod()
3920 CurDAG->getMachineNode(NotOpc, DL, SubVT, Zero, Add1); in tryShiftAmountMod()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUISelLowering.cpp | 2162 SDValue Add1 = DAG.getBitcast(VT, in LowerUDIVREM64() local
2166 SDValue Mullo2 = DAG.getNode(ISD::MUL, DL, VT, Neg_RHS, Add1); in LowerUDIVREM64()
2167 SDValue Mulhi2 = DAG.getNode(ISD::MULHU, DL, VT, Add1, Mullo2); in LowerUDIVREM64()
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| H A D | AMDGPULegalizerInfo.cpp | 4640 auto Add1 = B.buildMergeLikeInstr(S64, {Add1_Lo, Add1_Hi}); in legalizeUnsignedDIV_REM64Impl() local
4642 auto MulLo2 = B.buildMul(S64, NegDenom, Add1); in legalizeUnsignedDIV_REM64Impl()
4643 auto MulHi2 = B.buildUMulH(S64, Add1, MulLo2); in legalizeUnsignedDIV_REM64Impl()
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| H A D | SIISelLowering.cpp | 14454 SDValue Add1 = DAG.getNode(Opc, SL, VT, Op0, Op1); in reassociateScalarOps() local
14455 return DAG.getNode(Opc, SL, VT, Add1, Op2); in reassociateScalarOps()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsISelLowering.cpp | 1171 SDValue Add1 = DAG.getNode(ISD::ADD, DL, ValTy, Index, Other); in performADDCombine() local
1172 return DAG.getNode(ISD::ADD, DL, ValTy, Add1, Lo); in performADDCombine()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 13680 SDValue Add1 = in TryDistrubutionADDVecReduce() local
13682 return DAG.getNode(ISD::ADD, dl, VT, Add1, N1.getOperand(N1RedOp)); in TryDistrubutionADDVecReduce()
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