| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | ISDOpcodes.h | 707 AVGCEILU, enumerator
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| H A D | TargetLowering.h | 2999 case ISD::AVGCEILU: in isCommutativeBinOp()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86IntrinsicsInfo.h | 721 X86_INTRINSIC_DATA(avx2_pavg_b, INTR_TYPE_2OP, ISD::AVGCEILU, 0),
722 X86_INTRINSIC_DATA(avx2_pavg_w, INTR_TYPE_2OP, ISD::AVGCEILU, 0),
1267 X86_INTRINSIC_DATA(avx512_pavg_b_512, INTR_TYPE_2OP, ISD::AVGCEILU, 0),
1268 X86_INTRINSIC_DATA(avx512_pavg_w_512, INTR_TYPE_2OP, ISD::AVGCEILU, 0),
1966 X86_INTRINSIC_DATA(sse2_pavg_b, INTR_TYPE_2OP, ISD::AVGCEILU, 0),
1967 X86_INTRINSIC_DATA(sse2_pavg_w, INTR_TYPE_2OP, ISD::AVGCEILU, 0),
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| H A D | X86ISelLowering.cpp | 1132 setOperationAction(ISD::AVGCEILU, MVT::v16i8, Legal); in X86TargetLowering()
1133 setOperationAction(ISD::AVGCEILU, MVT::v8i16, Legal); in X86TargetLowering()
1597 setOperationAction(ISD::AVGCEILU, MVT::v16i16, HasInt256 ? Legal : Custom); in X86TargetLowering()
1598 setOperationAction(ISD::AVGCEILU, MVT::v32i8, HasInt256 ? Legal : Custom); in X86TargetLowering()
1947 setOperationAction(ISD::AVGCEILU, MVT::v32i16, HasBWI ? Legal : Custom); in X86TargetLowering()
1948 setOperationAction(ISD::AVGCEILU, MVT::v64i8, HasBWI ? Legal : Custom); in X86TargetLowering()
2653 ISD::AVGCEILU, in X86TargetLowering()
33720 case ISD::AVGCEILU: return LowerAVG(Op, Subtarget, DAG); in LowerOperation()
55003 DAG.getNode(ISD::AVGCEILU, DL, VT, N0, N1), SignMask); in combineAVG()
60528 case ISD::AVGCEILU: in PerformDAGCombine()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAGDumper.cpp | 280 case ISD::AVGCEILU: return "avgceilu"; in getOperationName()
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| H A D | LegalizeVectorOps.cpp | 384 case ISD::AVGCEILU: in LegalizeOp()
1059 case ISD::AVGCEILU: in Expand()
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| H A D | LegalizeVectorTypes.cpp | 147 case ISD::AVGCEILU: in ScalarizeVectorResult()
1297 case ISD::AVGCEILU: in SplitVectorResult()
4774 case ISD::AVGCEILU: in WidenVectorResult()
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| H A D | DAGCombiner.cpp | 1929 case ISD::AVGCEILU: return visitAVG(N); in visit()
2653 if ((!LegalOperations || hasOperation(ISD::AVGCEILU, VT)) && in foldSubToAvg()
2656 return DAG.getNode(ISD::AVGCEILU, DL, VT, A, B); in foldSubToAvg()
5596 (!LegalOperations || hasOperation(ISD::AVGCEILU, VT))) { in visitAVG()
5599 ISD::AVGCEILU, DL, VT, N0, in visitAVG()
5603 ISD::AVGCEILU, DL, VT, N1, in visitAVG()
5609 if ((Opcode == ISD::AVGFLOORU && hasOperation(ISD::AVGCEILU, VT)) || in visitAVG()
5624 return DAG.getNode(ISD::AVGCEILU, DL, VT, X, Y); in visitAVG()
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| H A D | LegalizeIntegerTypes.cpp | 224 case ISD::AVGCEILU: in PromoteIntegerResult()
3093 case ISD::AVGCEILU: in ExpandIntegerResult()
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| H A D | SelectionDAG.cpp | 3762 case ISD::AVGCEILU: { in computeKnownBits()
6712 case ISD::AVGCEILU: in FoldValue()
7552 case ISD::AVGCEILU: in getNode()
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| H A D | TargetLowering.cpp | 1108 unsigned AVGOpc = IsCeil ? (IsSigned ? ISD::AVGCEILS : ISD::AVGCEILU) in combineShiftToAVG()
3737 case ISD::AVGCEILU: in SimplifyDemandedVectorElts()
9788 Opc == ISD::AVGFLOORU || Opc == ISD::AVGCEILU) && in expandAVG()
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| H A D | LegalizeDAG.cpp | 3101 case ISD::AVGCEILU: in ExpandNode()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | TargetLoweringBase.cpp | 841 {ISD::AVGFLOORS, ISD::AVGFLOORU, ISD::AVGCEILS, ISD::AVGCEILU}, VT, in initActions()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/Target/ |
| H A D | TargetSelectionDAG.td | 419 def avgceilu : SDNode<"ISD::AVGCEILU" , SDTIntBinOp, [SDNPCommutative]>;
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 898 ISD::AVGCEILU, ISD::SADDSAT, ISD::UADDSAT, in RISCVTargetLowering()
1368 ISD::AVGCEILU, ISD::SADDSAT, ISD::UADDSAT, in RISCVTargetLowering()
6988 OP_CASE(AVGCEILU) in getRISCVVLOp()
8147 case ISD::AVGCEILU: in LowerOperation()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 1338 setOperationAction(ISD::AVGCEILU, VT, Legal); in AArch64TargetLowering()
1582 setOperationAction(ISD::AVGCEILU, VT, Custom); in AArch64TargetLowering()
6310 : (IsRoundingAdd ? ISD::AVGCEILU : ISD::AVGFLOORU); in LowerINTRINSIC_WO_CHAIN()
7494 case ISD::AVGCEILU: in LowerOperation()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 296 setOperationAction(ISD::AVGCEILU, VT, Legal); in addMVEVectorTypes()
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