Searched refs:AVGCEILS (Results 1 – 16 of 16) sorted by relevance
| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | ISDOpcodes.h | 684 AVGCEILS, enumerator
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| H A D | TargetLowering.h | 2912 case ISD::AVGCEILS: in isCommutativeBinOp()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAGDumper.cpp | 264 case ISD::AVGCEILS: return "avgceils"; in getOperationName()
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| H A D | LegalizeVectorOps.cpp | 372 case ISD::AVGCEILS: in LegalizeOp()
934 case ISD::AVGCEILS: in Expand()
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| H A D | LegalizeVectorTypes.cpp | 135 case ISD::AVGCEILS: in ScalarizeVectorResult()
1236 case ISD::AVGCEILS: in SplitVectorResult()
4401 case ISD::AVGCEILS: in WidenVectorResult()
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| H A D | SelectionDAG.cpp | 3531 case ISD::AVGCEILS: { in computeKnownBits()
4828 case ISD::AVGCEILS: in ComputeNumSignBits()
6296 case ISD::AVGCEILS: in FoldValue()
7006 case ISD::AVGCEILS: in getNode()
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| H A D | TargetLowering.cpp | 1053 unsigned AVGOpc = IsCeil ? (IsSigned ? ISD::AVGCEILS : ISD::AVGCEILU) in combineShiftToAVG()
3582 case ISD::AVGCEILS: in SimplifyDemandedVectorElts()
9307 bool IsSigned = Opc == ISD::AVGCEILS || Opc == ISD::AVGFLOORS; in expandAVG()
9312 assert((Opc == ISD::AVGFLOORS || Opc == ISD::AVGCEILS || in expandAVG()
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| H A D | LegalizeIntegerTypes.cpp | 195 case ISD::AVGCEILS: in PromoteIntegerResult()
2909 case ISD::AVGCEILS: in ExpandIntegerResult()
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| H A D | LegalizeDAG.cpp | 3070 case ISD::AVGCEILS: in ExpandNode()
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| H A D | DAGCombiner.cpp | 1870 case ISD::AVGCEILS: in visit()
2575 if ((!LegalOperations || hasOperation(ISD::AVGCEILS, VT)) && in foldSubToAvg()
2579 return DAG.getNode(ISD::AVGCEILS, DL, VT, A, B); in foldSubToAvg()
5197 bool IsSigned = Opcode == ISD::AVGCEILS || Opcode == ISD::AVGFLOORS; in visitAVG()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | TargetLoweringBase.cpp | 750 {ISD::AVGFLOORS, ISD::AVGFLOORU, ISD::AVGCEILS, ISD::AVGCEILU}, VT, in initActions()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/Target/ |
| H A D | TargetSelectionDAG.td | 401 def avgceils : SDNode<"ISD::AVGCEILS" , SDTIntBinOp, [SDNPCommutative]>;
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 849 setOperationAction({ISD::AVGFLOORS, ISD::AVGFLOORU, ISD::AVGCEILS, in RISCVTargetLowering()
1248 setOperationAction({ISD::AVGFLOORS, ISD::AVGFLOORU, ISD::AVGCEILS, in RISCVTargetLowering()
5980 OP_CASE(AVGCEILS) in getRISCVVLOp()
7027 case ISD::AVGCEILS: in LowerOperation()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 1285 setOperationAction(ISD::AVGCEILS, VT, Legal); in AArch64TargetLowering()
1489 setOperationAction(ISD::AVGCEILS, VT, Custom); in AArch64TargetLowering()
6005 ? (IsRoundingAdd ? ISD::AVGCEILS : ISD::AVGFLOORS) in LowerINTRINSIC_WO_CHAIN()
7020 case ISD::AVGCEILS: in LowerOperation()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 2522 ISD::AVGCEILS, in X86TargetLowering()
53171 if (Opcode == ISD::AVGCEILS && VT.isVector() && SVT == MVT::i8) { in combineAVG()
57785 case ISD::AVGCEILS: in PerformDAGCombine()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 290 setOperationAction(ISD::AVGCEILS, VT, Legal); in addMVEVectorTypes()
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