| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVMergeBaseOffset.cpp | 86 if (Hi.getOpcode() != RISCV::LUI && Hi.getOpcode() != RISCV::AUIPC && in INITIALIZE_PASS()
92 Hi.getOpcode() == RISCV::AUIPC ? RISCVII::MO_PCREL_HI : RISCVII::MO_HI; in INITIALIZE_PASS()
121 assert(Hi.getOpcode() == RISCV::AUIPC); in INITIALIZE_PASS()
151 if (Hi.getOpcode() == RISCV::AUIPC && Hi.getOperand(1).isGlobal()) { in foldOffset()
161 if (Hi.getOpcode() != RISCV::AUIPC) in foldOffset()
513 if (Hi.getOpcode() != RISCV::AUIPC) in foldIntoMemoryOps()
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| H A D | RISCVIndirectBranchTracking.cpp | 60 BuildMI(MBB, I, MBB.findDebugLoc(I), TII->get(RISCV::AUIPC), RISCV::X0) in emitLpad()
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| H A D | RISCVExpandPseudoInsts.cpp | 578 BuildMI(MBB, MBBI, DL, TII->get(RISCV::AUIPC), ScratchReg).add(Symbol); in expandAuipcInstPair()
644 BuildMI(MBB, MBBI, DL, TII->get(RISCV::AUIPC), ScratchReg).add(Symbol); in expandLoadTLSDescAddress()
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| H A D | RISCVRegisterInfo.cpp | 1033 (I->getOpcode() == RISCV::AUIPC && in getRegAllocationHints()
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| H A D | RISCVInstrInfo.td | 139 // Represents an AUIPC+ADDI pair. Selected to PseudoLLA.
384 let ParserMatchClass = UImmAsmOperand<20, "AUIPC">;
737 def AUIPC : RVInstU<OPC_AUIPC, (outs GPR:$rd), (ins uimm20_auipc:$imm20),
1214 def : InstAlias<"lpad $imm20", (AUIPC X0, uimm20:$imm20)>;
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| H A D | RISCVInstrFormats.td | 147 def OPC_AUIPC : RISCVOpcode<"AUIPC", 0b0010111>;
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| H A D | RISCVInstrInfoXqci.td | 1255 // Load/Store pseudos with QC.E.* Mnemonics. These expand to an AUIPC +
1257 // and is shorter than e.g. an AUIPC + Xqcilo Load/Store sequence. These
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| H A D | RISCVISelLowering.cpp | 8468 GetEncoding(MCInstBuilder(RISCV::AUIPC).addReg(RISCV::X7).addImm(0)), in lowerINIT_TRAMPOLINE()
8492 GetEncoding(MCInstBuilder(RISCV::AUIPC).addReg(RISCV::X0).addImm(0)), in lowerINIT_TRAMPOLINE()
8495 GetEncoding(MCInstBuilder(RISCV::AUIPC).addReg(RISCV::X28).addImm(0)), in lowerINIT_TRAMPOLINE()
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| /freebsd/contrib/llvm-project/lldb/source/Plugins/Instruction/RISCV/ |
| H A D | RISCVInstructions.h | 110 U_TYPE_INST(AUIPC);
276 LUI, AUIPC, JAL, JALR, B, LB, LH, LW, LBU, LHU, SB, SH, SW, ADDI, SLTI,
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| H A D | EmulateInstructionRISCV.cpp | 425 {"AUIPC", 0x7F, 0x17, DecodeUType<AUIPC>},
683 bool operator()(AUIPC inst) { in operator ()()
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| /freebsd/contrib/llvm-project/lld/ELF/Arch/ |
| H A D | RISCV.cpp | 65 AUIPC = 0x17, enumerator
235 write32le(buf + 0, utype(AUIPC, X_T2, hi20(offset))); in writePltHeader()
252 write32le(buf + 0, utype(AUIPC, X_T3, hi20(offset))); in writePlt()
556 write32le(loc, utype(AUIPC, X_A0, hi20(val))); // auipc a0,<hi20> in tlsdescToIe()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/MCTargetDesc/ |
| H A D | RISCVMCTargetDesc.cpp | 197 case RISCV::AUIPC: in updateState()
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| H A D | RISCVMCCodeEmitter.cpp | 180 TmpInst = MCInstBuilder(RISCV::AUIPC).addReg(Ra).addExpr(CallExpr); in expandFunctionCall()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsScheduleI6400.td | 111 AUIPC, BITSWAP, CFC1, CLO_R6, CLZ_R6, CTC1, DADD, DADDiu,
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| H A D | Mips32r6InstrInfo.td | 881 def AUIPC : R6MMR6Rel, AUIPC_ENC, AUIPC_DESC, ISA_MIPS32R6;
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| H A D | MipsScheduleGeneric.td | 60 AUIPC, BITSWAP, CLO_R6, CLZ_R6, LSA_R6,
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/AsmParser/ |
| H A D | RISCVAsmParser.cpp | 3471 MCInstBuilder(RISCV::AUIPC).addReg(TmpReg).addExpr(SymbolHi)); in emitAuipcInstPair()
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