1 /* SPDX-License-Identifier: BSD-3-Clause-Clear */ 2 /* 3 * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved. 4 * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved. 5 */ 6 7 #ifndef ATH11K_QMI_H 8 #define ATH11K_QMI_H 9 10 #if defined(__FreeBSD__) 11 #include <linux/types.h> 12 #include <linux/list.h> 13 #endif 14 #include <linux/mutex.h> 15 #include <linux/soc/qcom/qmi.h> 16 17 #define ATH11K_HOST_VERSION_STRING "WIN" 18 #define ATH11K_QMI_WLANFW_TIMEOUT_MS 10000 19 #define ATH11K_QMI_MAX_BDF_FILE_NAME_SIZE 64 20 #define ATH11K_QMI_CALDB_ADDRESS 0x4BA00000 21 #define ATH11K_QMI_WLANFW_MAX_BUILD_ID_LEN_V01 128 22 #define ATH11K_QMI_WLFW_SERVICE_ID_V01 0x45 23 #define ATH11K_QMI_WLFW_SERVICE_VERS_V01 0x01 24 #define ATH11K_QMI_WLFW_SERVICE_INS_ID_V01 0x02 25 #define ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_QCA6390 0x01 26 #define ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_IPQ8074 0x02 27 #define ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_QCN9074 0x07 28 #define ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_WCN6750 0x03 29 #define ATH11K_QMI_WLANFW_MAX_TIMESTAMP_LEN_V01 32 30 #define ATH11K_QMI_RESP_LEN_MAX 8192 31 #define ATH11K_QMI_WLANFW_MAX_NUM_MEM_SEG_V01 52 32 #define ATH11K_QMI_CALDB_SIZE 0x480000 33 #define ATH11K_QMI_BDF_EXT_STR_LENGTH 0x20 34 #define ATH11K_QMI_FW_MEM_REQ_SEGMENT_CNT 5 35 36 #define QMI_WLFW_REQUEST_MEM_IND_V01 0x0035 37 #define QMI_WLFW_FW_MEM_READY_IND_V01 0x0037 38 #define QMI_WLFW_COLD_BOOT_CAL_DONE_IND_V01 0x003E 39 #define QMI_WLFW_FW_READY_IND_V01 0x0021 40 #define QMI_WLFW_FW_INIT_DONE_IND_V01 0x0038 41 42 #define QMI_WLANFW_MAX_DATA_SIZE_V01 6144 43 #define ATH11K_FIRMWARE_MODE_OFF 4 44 #define ATH11K_COLD_BOOT_FW_RESET_DELAY (60 * HZ) 45 46 #define ATH11K_QMI_DEVICE_BAR_SIZE 0x200000 47 48 struct ath11k_base; 49 50 enum ath11k_qmi_file_type { 51 ATH11K_QMI_FILE_TYPE_BDF_GOLDEN, 52 ATH11K_QMI_FILE_TYPE_CALDATA = 2, 53 ATH11K_QMI_FILE_TYPE_EEPROM, 54 ATH11K_QMI_MAX_FILE_TYPE, 55 }; 56 57 enum ath11k_qmi_bdf_type { 58 ATH11K_QMI_BDF_TYPE_BIN = 0, 59 ATH11K_QMI_BDF_TYPE_ELF = 1, 60 ATH11K_QMI_BDF_TYPE_REGDB = 4, 61 }; 62 63 enum ath11k_qmi_event_type { 64 ATH11K_QMI_EVENT_SERVER_ARRIVE, 65 ATH11K_QMI_EVENT_SERVER_EXIT, 66 ATH11K_QMI_EVENT_REQUEST_MEM, 67 ATH11K_QMI_EVENT_FW_MEM_READY, 68 ATH11K_QMI_EVENT_FW_READY, 69 ATH11K_QMI_EVENT_COLD_BOOT_CAL_START, 70 ATH11K_QMI_EVENT_COLD_BOOT_CAL_DONE, 71 ATH11K_QMI_EVENT_REGISTER_DRIVER, 72 ATH11K_QMI_EVENT_UNREGISTER_DRIVER, 73 ATH11K_QMI_EVENT_RECOVERY, 74 ATH11K_QMI_EVENT_FORCE_FW_ASSERT, 75 ATH11K_QMI_EVENT_POWER_UP, 76 ATH11K_QMI_EVENT_POWER_DOWN, 77 ATH11K_QMI_EVENT_FW_INIT_DONE, 78 ATH11K_QMI_EVENT_MAX, 79 }; 80 81 struct ath11k_qmi_driver_event { 82 struct list_head list; 83 enum ath11k_qmi_event_type type; 84 void *data; 85 }; 86 87 struct ath11k_qmi_ce_cfg { 88 const struct ce_pipe_config *tgt_ce; 89 int tgt_ce_len; 90 const struct service_to_pipe *svc_to_ce_map; 91 int svc_to_ce_map_len; 92 const u8 *shadow_reg; 93 int shadow_reg_len; 94 u32 *shadow_reg_v2; 95 int shadow_reg_v2_len; 96 }; 97 98 struct ath11k_qmi_event_msg { 99 struct list_head list; 100 enum ath11k_qmi_event_type type; 101 }; 102 103 struct target_mem_chunk { 104 u32 size; 105 u32 type; 106 u32 prev_size; 107 u32 prev_type; 108 dma_addr_t paddr; 109 u32 *vaddr; 110 void __iomem *iaddr; 111 }; 112 113 struct target_info { 114 u32 chip_id; 115 u32 chip_family; 116 u32 board_id; 117 u32 soc_id; 118 u32 fw_version; 119 u32 eeprom_caldata; 120 char fw_build_timestamp[ATH11K_QMI_WLANFW_MAX_TIMESTAMP_LEN_V01 + 1]; 121 char fw_build_id[ATH11K_QMI_WLANFW_MAX_BUILD_ID_LEN_V01 + 1]; 122 char bdf_ext[ATH11K_QMI_BDF_EXT_STR_LENGTH]; 123 }; 124 125 struct m3_mem_region { 126 u32 size; 127 dma_addr_t paddr; 128 void *vaddr; 129 }; 130 131 struct ath11k_qmi { 132 struct ath11k_base *ab; 133 struct qmi_handle handle; 134 struct sockaddr_qrtr sq; 135 struct work_struct event_work; 136 struct workqueue_struct *event_wq; 137 struct list_head event_list; 138 spinlock_t event_lock; /* spinlock for qmi event list */ 139 struct ath11k_qmi_ce_cfg ce_cfg; 140 struct target_mem_chunk target_mem[ATH11K_QMI_WLANFW_MAX_NUM_MEM_SEG_V01]; 141 u32 mem_seg_count; 142 u32 target_mem_mode; 143 bool target_mem_delayed; 144 u8 cal_done; 145 struct target_info target; 146 struct m3_mem_region m3_mem; 147 unsigned int service_ins_id; 148 wait_queue_head_t cold_boot_waitq; 149 }; 150 151 #define QMI_WLANFW_HOST_CAP_REQ_MSG_V01_MAX_LEN 261 152 #define QMI_WLANFW_HOST_CAP_REQ_V01 0x0034 153 #define QMI_WLANFW_HOST_CAP_RESP_MSG_V01_MAX_LEN 7 154 #define QMI_WLFW_HOST_CAP_RESP_V01 0x0034 155 #define QMI_WLFW_MAX_NUM_GPIO_V01 32 156 #define QMI_IPQ8074_FW_MEM_MODE 0xFF 157 #define HOST_DDR_REGION_TYPE 0x1 158 #define BDF_MEM_REGION_TYPE 0x2 159 #define M3_DUMP_REGION_TYPE 0x3 160 #define CALDB_MEM_REGION_TYPE 0x4 161 162 struct qmi_wlanfw_host_cap_req_msg_v01 { 163 u8 num_clients_valid; 164 u32 num_clients; 165 u8 wake_msi_valid; 166 u32 wake_msi; 167 u8 gpios_valid; 168 u32 gpios_len; 169 u32 gpios[QMI_WLFW_MAX_NUM_GPIO_V01]; 170 u8 nm_modem_valid; 171 u8 nm_modem; 172 u8 bdf_support_valid; 173 u8 bdf_support; 174 u8 bdf_cache_support_valid; 175 u8 bdf_cache_support; 176 u8 m3_support_valid; 177 u8 m3_support; 178 u8 m3_cache_support_valid; 179 u8 m3_cache_support; 180 u8 cal_filesys_support_valid; 181 u8 cal_filesys_support; 182 u8 cal_cache_support_valid; 183 u8 cal_cache_support; 184 u8 cal_done_valid; 185 u8 cal_done; 186 u8 mem_bucket_valid; 187 u32 mem_bucket; 188 u8 mem_cfg_mode_valid; 189 u8 mem_cfg_mode; 190 }; 191 192 struct qmi_wlanfw_host_cap_resp_msg_v01 { 193 struct qmi_response_type_v01 resp; 194 }; 195 196 #define QMI_WLANFW_IND_REGISTER_REQ_MSG_V01_MAX_LEN 54 197 #define QMI_WLANFW_IND_REGISTER_REQ_V01 0x0020 198 #define QMI_WLANFW_IND_REGISTER_RESP_MSG_V01_MAX_LEN 18 199 #define QMI_WLANFW_IND_REGISTER_RESP_V01 0x0020 200 #define QMI_WLANFW_CLIENT_ID 0x4b4e454c 201 202 struct qmi_wlanfw_ind_register_req_msg_v01 { 203 u8 fw_ready_enable_valid; 204 u8 fw_ready_enable; 205 u8 initiate_cal_download_enable_valid; 206 u8 initiate_cal_download_enable; 207 u8 initiate_cal_update_enable_valid; 208 u8 initiate_cal_update_enable; 209 u8 msa_ready_enable_valid; 210 u8 msa_ready_enable; 211 u8 pin_connect_result_enable_valid; 212 u8 pin_connect_result_enable; 213 u8 client_id_valid; 214 u32 client_id; 215 u8 request_mem_enable_valid; 216 u8 request_mem_enable; 217 u8 fw_mem_ready_enable_valid; 218 u8 fw_mem_ready_enable; 219 u8 fw_init_done_enable_valid; 220 u8 fw_init_done_enable; 221 u8 rejuvenate_enable_valid; 222 u32 rejuvenate_enable; 223 u8 xo_cal_enable_valid; 224 u8 xo_cal_enable; 225 u8 cal_done_enable_valid; 226 u8 cal_done_enable; 227 }; 228 229 struct qmi_wlanfw_ind_register_resp_msg_v01 { 230 struct qmi_response_type_v01 resp; 231 u8 fw_status_valid; 232 u64 fw_status; 233 }; 234 235 #define QMI_WLANFW_REQUEST_MEM_IND_MSG_V01_MAX_LEN 1824 236 #define QMI_WLANFW_RESPOND_MEM_REQ_MSG_V01_MAX_LEN 888 237 #define QMI_WLANFW_RESPOND_MEM_RESP_MSG_V01_MAX_LEN 7 238 #define QMI_WLANFW_REQUEST_MEM_IND_V01 0x0035 239 #define QMI_WLANFW_RESPOND_MEM_REQ_V01 0x0036 240 #define QMI_WLANFW_RESPOND_MEM_RESP_V01 0x0036 241 #define QMI_WLANFW_MAX_NUM_MEM_CFG_V01 2 242 243 struct qmi_wlanfw_mem_cfg_s_v01 { 244 u64 offset; 245 u32 size; 246 u8 secure_flag; 247 }; 248 249 enum qmi_wlanfw_mem_type_enum_v01 { 250 WLANFW_MEM_TYPE_ENUM_MIN_VAL_V01 = INT_MIN, 251 QMI_WLANFW_MEM_TYPE_MSA_V01 = 0, 252 QMI_WLANFW_MEM_TYPE_DDR_V01 = 1, 253 QMI_WLANFW_MEM_BDF_V01 = 2, 254 QMI_WLANFW_MEM_M3_V01 = 3, 255 QMI_WLANFW_MEM_CAL_V01 = 4, 256 QMI_WLANFW_MEM_DPD_V01 = 5, 257 WLANFW_MEM_TYPE_ENUM_MAX_VAL_V01 = INT_MAX, 258 }; 259 260 struct qmi_wlanfw_mem_seg_s_v01 { 261 u32 size; 262 enum qmi_wlanfw_mem_type_enum_v01 type; 263 u32 mem_cfg_len; 264 struct qmi_wlanfw_mem_cfg_s_v01 mem_cfg[QMI_WLANFW_MAX_NUM_MEM_CFG_V01]; 265 }; 266 267 struct qmi_wlanfw_request_mem_ind_msg_v01 { 268 u32 mem_seg_len; 269 struct qmi_wlanfw_mem_seg_s_v01 mem_seg[ATH11K_QMI_WLANFW_MAX_NUM_MEM_SEG_V01]; 270 }; 271 272 struct qmi_wlanfw_mem_seg_resp_s_v01 { 273 u64 addr; 274 u32 size; 275 enum qmi_wlanfw_mem_type_enum_v01 type; 276 u8 restore; 277 }; 278 279 struct qmi_wlanfw_respond_mem_req_msg_v01 { 280 u32 mem_seg_len; 281 struct qmi_wlanfw_mem_seg_resp_s_v01 mem_seg[ATH11K_QMI_WLANFW_MAX_NUM_MEM_SEG_V01]; 282 }; 283 284 struct qmi_wlanfw_respond_mem_resp_msg_v01 { 285 struct qmi_response_type_v01 resp; 286 }; 287 288 struct qmi_wlanfw_fw_mem_ready_ind_msg_v01 { 289 char placeholder; 290 }; 291 292 struct qmi_wlanfw_fw_ready_ind_msg_v01 { 293 char placeholder; 294 }; 295 296 struct qmi_wlanfw_fw_cold_cal_done_ind_msg_v01 { 297 char placeholder; 298 }; 299 300 struct qmi_wlfw_fw_init_done_ind_msg_v01 { 301 char placeholder; 302 }; 303 304 #define QMI_WLANFW_CAP_REQ_MSG_V01_MAX_LEN 0 305 #define QMI_WLANFW_CAP_RESP_MSG_V01_MAX_LEN 235 306 #define QMI_WLANFW_CAP_REQ_V01 0x0024 307 #define QMI_WLANFW_CAP_RESP_V01 0x0024 308 #define QMI_WLANFW_DEVICE_INFO_REQ_V01 0x004C 309 #define QMI_WLANFW_DEVICE_INFO_REQ_MSG_V01_MAX_LEN 0 310 311 enum qmi_wlanfw_pipedir_enum_v01 { 312 QMI_WLFW_PIPEDIR_NONE_V01 = 0, 313 QMI_WLFW_PIPEDIR_IN_V01 = 1, 314 QMI_WLFW_PIPEDIR_OUT_V01 = 2, 315 QMI_WLFW_PIPEDIR_INOUT_V01 = 3, 316 }; 317 318 struct qmi_wlanfw_ce_tgt_pipe_cfg_s_v01 { 319 __le32 pipe_num; 320 __le32 pipe_dir; 321 __le32 nentries; 322 __le32 nbytes_max; 323 __le32 flags; 324 }; 325 326 struct qmi_wlanfw_ce_svc_pipe_cfg_s_v01 { 327 __le32 service_id; 328 __le32 pipe_dir; 329 __le32 pipe_num; 330 }; 331 332 struct qmi_wlanfw_shadow_reg_cfg_s_v01 { 333 u16 id; 334 u16 offset; 335 }; 336 337 struct qmi_wlanfw_shadow_reg_v2_cfg_s_v01 { 338 u32 addr; 339 }; 340 341 struct qmi_wlanfw_memory_region_info_s_v01 { 342 u64 region_addr; 343 u32 size; 344 u8 secure_flag; 345 }; 346 347 struct qmi_wlanfw_rf_chip_info_s_v01 { 348 u32 chip_id; 349 u32 chip_family; 350 }; 351 352 struct qmi_wlanfw_rf_board_info_s_v01 { 353 u32 board_id; 354 }; 355 356 struct qmi_wlanfw_soc_info_s_v01 { 357 u32 soc_id; 358 }; 359 360 struct qmi_wlanfw_fw_version_info_s_v01 { 361 u32 fw_version; 362 char fw_build_timestamp[ATH11K_QMI_WLANFW_MAX_TIMESTAMP_LEN_V01 + 1]; 363 }; 364 365 enum qmi_wlanfw_cal_temp_id_enum_v01 { 366 QMI_WLANFW_CAL_TEMP_IDX_0_V01 = 0, 367 QMI_WLANFW_CAL_TEMP_IDX_1_V01 = 1, 368 QMI_WLANFW_CAL_TEMP_IDX_2_V01 = 2, 369 QMI_WLANFW_CAL_TEMP_IDX_3_V01 = 3, 370 QMI_WLANFW_CAL_TEMP_IDX_4_V01 = 4, 371 QMI_WLANFW_CAL_TEMP_ID_MAX_V01 = 0xFF, 372 }; 373 374 struct qmi_wlanfw_cap_resp_msg_v01 { 375 struct qmi_response_type_v01 resp; 376 u8 chip_info_valid; 377 struct qmi_wlanfw_rf_chip_info_s_v01 chip_info; 378 u8 board_info_valid; 379 struct qmi_wlanfw_rf_board_info_s_v01 board_info; 380 u8 soc_info_valid; 381 struct qmi_wlanfw_soc_info_s_v01 soc_info; 382 u8 fw_version_info_valid; 383 struct qmi_wlanfw_fw_version_info_s_v01 fw_version_info; 384 u8 fw_build_id_valid; 385 char fw_build_id[ATH11K_QMI_WLANFW_MAX_BUILD_ID_LEN_V01 + 1]; 386 u8 num_macs_valid; 387 u8 num_macs; 388 u8 voltage_mv_valid; 389 u32 voltage_mv; 390 u8 time_freq_hz_valid; 391 u32 time_freq_hz; 392 u8 otp_version_valid; 393 u32 otp_version; 394 u8 eeprom_read_timeout_valid; 395 u32 eeprom_read_timeout; 396 }; 397 398 struct qmi_wlanfw_cap_req_msg_v01 { 399 char placeholder; 400 }; 401 402 struct qmi_wlanfw_device_info_req_msg_v01 { 403 char placeholder; 404 }; 405 406 struct qmi_wlanfw_device_info_resp_msg_v01 { 407 struct qmi_response_type_v01 resp; 408 u64 bar_addr; 409 u32 bar_size; 410 u8 bar_addr_valid; 411 u8 bar_size_valid; 412 }; 413 414 #define QMI_WLANFW_BDF_DOWNLOAD_REQ_MSG_V01_MAX_LEN 6182 415 #define QMI_WLANFW_BDF_DOWNLOAD_RESP_MSG_V01_MAX_LEN 7 416 #define QMI_WLANFW_BDF_DOWNLOAD_RESP_V01 0x0025 417 #define QMI_WLANFW_BDF_DOWNLOAD_REQ_V01 0x0025 418 /* TODO: Need to check with MCL and FW team that data can be pointer and 419 * can be last element in structure 420 */ 421 struct qmi_wlanfw_bdf_download_req_msg_v01 { 422 u8 valid; 423 u8 file_id_valid; 424 enum qmi_wlanfw_cal_temp_id_enum_v01 file_id; 425 u8 total_size_valid; 426 u32 total_size; 427 u8 seg_id_valid; 428 u32 seg_id; 429 u8 data_valid; 430 u32 data_len; 431 u8 data[QMI_WLANFW_MAX_DATA_SIZE_V01]; 432 u8 end_valid; 433 u8 end; 434 u8 bdf_type_valid; 435 u8 bdf_type; 436 437 }; 438 439 struct qmi_wlanfw_bdf_download_resp_msg_v01 { 440 struct qmi_response_type_v01 resp; 441 }; 442 443 #define QMI_WLANFW_M3_INFO_REQ_MSG_V01_MAX_MSG_LEN 18 444 #define QMI_WLANFW_M3_INFO_RESP_MSG_V01_MAX_MSG_LEN 7 445 #define QMI_WLANFW_M3_INFO_RESP_V01 0x003C 446 #define QMI_WLANFW_M3_INFO_REQ_V01 0x003C 447 448 struct qmi_wlanfw_m3_info_req_msg_v01 { 449 u64 addr; 450 u32 size; 451 }; 452 453 struct qmi_wlanfw_m3_info_resp_msg_v01 { 454 struct qmi_response_type_v01 resp; 455 }; 456 457 #define QMI_WLANFW_WLAN_MODE_REQ_MSG_V01_MAX_LEN 11 458 #define QMI_WLANFW_WLAN_MODE_RESP_MSG_V01_MAX_LEN 7 459 #define QMI_WLANFW_WLAN_CFG_REQ_MSG_V01_MAX_LEN 803 460 #define QMI_WLANFW_WLAN_CFG_RESP_MSG_V01_MAX_LEN 7 461 #define QMI_WLANFW_WLAN_INI_REQ_MSG_V01_MAX_LEN 4 462 #define QMI_WLANFW_WLAN_MODE_REQ_V01 0x0022 463 #define QMI_WLANFW_WLAN_MODE_RESP_V01 0x0022 464 #define QMI_WLANFW_WLAN_CFG_REQ_V01 0x0023 465 #define QMI_WLANFW_WLAN_CFG_RESP_V01 0x0023 466 #define QMI_WLANFW_WLAN_INI_REQ_V01 0x002F 467 #define QMI_WLANFW_MAX_STR_LEN_V01 16 468 #define QMI_WLANFW_MAX_NUM_CE_V01 12 469 #define QMI_WLANFW_MAX_NUM_SVC_V01 24 470 #define QMI_WLANFW_MAX_NUM_SHADOW_REG_V01 24 471 #define QMI_WLANFW_MAX_NUM_SHADOW_REG_V2_V01 36 472 473 struct qmi_wlanfw_wlan_mode_req_msg_v01 { 474 u32 mode; 475 u8 hw_debug_valid; 476 u8 hw_debug; 477 }; 478 479 struct qmi_wlanfw_wlan_mode_resp_msg_v01 { 480 struct qmi_response_type_v01 resp; 481 }; 482 483 struct qmi_wlanfw_wlan_cfg_req_msg_v01 { 484 u8 host_version_valid; 485 char host_version[QMI_WLANFW_MAX_STR_LEN_V01 + 1]; 486 u8 tgt_cfg_valid; 487 u32 tgt_cfg_len; 488 struct qmi_wlanfw_ce_tgt_pipe_cfg_s_v01 489 tgt_cfg[QMI_WLANFW_MAX_NUM_CE_V01]; 490 u8 svc_cfg_valid; 491 u32 svc_cfg_len; 492 struct qmi_wlanfw_ce_svc_pipe_cfg_s_v01 493 svc_cfg[QMI_WLANFW_MAX_NUM_SVC_V01]; 494 u8 shadow_reg_valid; 495 u32 shadow_reg_len; 496 struct qmi_wlanfw_shadow_reg_cfg_s_v01 497 shadow_reg[QMI_WLANFW_MAX_NUM_SHADOW_REG_V01]; 498 u8 shadow_reg_v2_valid; 499 u32 shadow_reg_v2_len; 500 struct qmi_wlanfw_shadow_reg_v2_cfg_s_v01 501 shadow_reg_v2[QMI_WLANFW_MAX_NUM_SHADOW_REG_V2_V01]; 502 }; 503 504 struct qmi_wlanfw_wlan_cfg_resp_msg_v01 { 505 struct qmi_response_type_v01 resp; 506 }; 507 508 struct qmi_wlanfw_wlan_ini_req_msg_v01 { 509 /* Must be set to true if enablefwlog is being passed */ 510 u8 enablefwlog_valid; 511 u8 enablefwlog; 512 }; 513 514 struct qmi_wlanfw_wlan_ini_resp_msg_v01 { 515 struct qmi_response_type_v01 resp; 516 }; 517 518 int ath11k_qmi_firmware_start(struct ath11k_base *ab, 519 u32 mode); 520 void ath11k_qmi_firmware_stop(struct ath11k_base *ab); 521 void ath11k_qmi_event_work(struct work_struct *work); 522 void ath11k_qmi_msg_recv_work(struct work_struct *work); 523 void ath11k_qmi_deinit_service(struct ath11k_base *ab); 524 int ath11k_qmi_init_service(struct ath11k_base *ab); 525 void ath11k_qmi_free_resource(struct ath11k_base *ab); 526 int ath11k_qmi_fwreset_from_cold_boot(struct ath11k_base *ab); 527 528 #endif 529