| /freebsd/contrib/llvm-project/compiler-rt/lib/builtins/hexagon/ |
| H A D | fastmath2_ldlib_asm.S | 89 lmanta = ASR(lmanta, expa)
90 lmantb = ASR(lmantb, expb)
188 lmanta = ASR(lmanta, expa)
189 lmantb = ASR(lmantb, expb)
|
| H A D | fastmath2_dlib_asm.S | 96 lmanta = ASR(lmanta, expa)
97 lmantb = ASR(lmantb, expb)
197 lmanta = ASR(lmanta, expa)
198 lmantb = ASR(lmantb, expb)
|
| H A D | fastmath_dlib_asm.S | 104 lmanta = ASR(lmanta, expa)
105 lmantb = ASR(lmantb, expb)
239 lmanta = ASR(lmanta, expa)
240 lmantb = ASR(lmantb, expb)
|
| H A D | dfdiv.S | 169 DIV_ITER1B(ASR,1,15,)
170 DIV_ITER1B(ASR,16,15,)
171 DIV_ITER1B(ASR,31,15,PROD=# ( 0 );)
|
| H A D | dfaddsub.S | 117 BTMP = ASR(BTMP,EXPDIFF)
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/M68k/ |
| H A D | M68kInstrShiftRotate.td | 15 /// SHL [~] ASR [~] LSR [~] SWAP [ ]
95 defm ASR : MxSROp<"asr", sra, MxRODI_R, MxROOP_AS>;
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/MCTargetDesc/ |
| H A D | AArch64AddressingModes.h | 36 ASR,
57 case AArch64_AM::ASR: return "asr"; in getShiftExtendName()
78 case 2: return AArch64_AM::ASR; in getShiftType()
106 case AArch64_AM::ASR: STEnc = 2; break; in getShifterImm()
37 ASR, global() enumerator
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/AVR/ |
| H A D | AVRISelLowering.h | 48 ASR, ///< Arithmetic shift right. enumerator
|
| H A D | AVRISelLowering.cpp | 242 NODE(ASR); in getTargetNodeName()
358 Opc8 = AVRISD::ASR; in LowerShifts()
|
| /freebsd/contrib/llvm-project/lldb/source/Plugins/Process/Utility/ |
| H A D | ARMUtils.h | 157 static inline uint32_t ASR(const uint32_t value, const uint32_t amount, in ASR() function
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64SchedA510.td | 683 (instregex "^(ASR|LSL|LSR)_WIDE_ZPmZ_[BHS]",
684 "^(ASR|LSL|LSR)_WIDE_ZZZ_[BHS]",
685 "^(ASR|LSL|LSR)_ZPmI_[BHSD]",
686 "^(ASR|LSL|LSR)_ZPZI_[BHSD]",
687 "^(ASR|LSL|LSR)_ZPmZ_[BHSD]",
688 "^(ASR|LSL|LSR)_ZPZZ_[BHSD]",
689 "^(ASR|LSL|LSR)_ZZI_[BHSD]",
|
| H A D | AArch64SchedNeoverseN2.td | 653 // Arithmetic, LSR/ASR/ROR shift or LSL shift > 4
1625 (instregex "^(ASR|LSL|LSR)_WIDE_ZPmZ_[BHS]",
1626 "^(ASR|LSL|LSR)_WIDE_ZZZ_[BHS]",
1627 "^(ASR|LSL|LSR)_ZPmI_[BHSD]",
1628 "^(ASR|LSL|LSR)_ZPmZ_[BHSD]",
1629 "^(ASR|LSL|LSR)_ZZI_[BHSD]",
1630 "^(ASR|LSL|LSR)_ZPZ[IZ]_[BHSD]",
|
| H A D | AArch64SchedNeoverseV1.td | 525 // Arithmetic, LSR/ASR/ROR shift or LSL shift > 4
532 // Arithmetic, flagset, LSR/ASR/ROR shift or LSL shift > 4
1390 (instregex "^(ASR|LSL|LSR)_WIDE_Z(Pm|Z)Z_[BHS]",
1391 "^(ASR|LSL|LSR)_ZPm[IZ]_[BHSD]",
1392 "^(ASR|LSL|LSR)_ZZI_[BHSD]",
1393 "^(ASR|LSL|LSR)_ZPZ[IZ]_[BHSD]",
|
| H A D | AArch64SchedPredicates.td | 56 def CheckShiftASR : CheckImmOperand_s<3, "AArch64_AM::ASR">;
|
| H A D | AArch64SchedNeoverseV2.td | 1124 // Arithmetic, LSR/ASR/ROR shift or LSL shift > 4
2135 (instregex "^(ASR|LSL|LSR)_WIDE_ZPmZ_[BHS]",
2136 "^(ASR|LSL|LSR)_WIDE_ZZZ_[BHS]",
2137 "^(ASR|LSL|LSR)_ZPmI_[BHSD]",
2138 "^(ASR|LSL|LSR)_ZPmZ_[BHSD]",
2139 "^(ASR|LSL|LSR)_ZZI_[BHSD]",
2140 "^(ASR|LSL|LSR)_ZPZ[IZ]_[BHSD]",
|
| H A D | AArch64FastISel.cpp | 1273 case Instruction::AShr: ShiftType = AArch64_AM::ASR; break; in emitAddSub()
3737 emitSubs_rs(VT, SMULHReg, MulReg, AArch64_AM::ASR, 63, in fastLowerIntrinsicCall()
4943 AArch64_AM::ASR, Lg2); in selectSDiv()
|
| /freebsd/contrib/llvm-project/llvm/lib/Transforms/Utils/ |
| H A D | FunctionComparator.cpp | 801 unsigned int ASR = GEPR->getPointerAddressSpace(); in cmpGEPs() local
803 if (int Res = cmpNumbers(ASL, ASR)) in cmpGEPs()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/Utils/ |
| H A D | AArch64BaseInfo.h | 608 ASR, enumerator
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/Sparc/ |
| H A D | SparcRegisterInfo.td | 380 // from the ASR (as ASR4) or the privileged register set.
383 (add Y, TICK, (sequence "ASR%u", 1, 31))>;
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMScheduleM7.td | 338 def : InstRW<[WriteALUsi], (instregex "(t|t2)(LSL|LSR|ASR|ROR)")>;
|
| H A D | ARMInstrThumb.td | 1077 // ASR immediate
1088 // ASR register
|
| H A D | ARMScheduleSwift.td | 154 // ASR,LSL,ROR,RRX
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/AsmParser/ |
| H A D | AArch64AsmParser.cpp | 1495 ST == AArch64_AM::ASR || ST == AArch64_AM::ROR || in isShifter()
1597 ST == AArch64_AM::ASR) && getShiftExtendAmount() < width; in isArithmeticShifter()
1608 ST == AArch64_AM::ASR || ST == AArch64_AM::ROR) && in isLogicalShifter()
3593 .Case("asr", AArch64_AM::ASR) in tryParseOptionalShiftExtend()
3616 ShOp == AArch64_AM::ASR || ShOp == AArch64_AM::ROR || in tryParseOptionalShiftExtend()
|
| /freebsd/share/misc/ |
| H A D | pci_vendors | 6729 1044 c032 ASR-2005S I2O Zero Channel
6730 1044 c035 ASR-2010S I2O Zero Channel
27011 1e5d ASR Microelectronics
37658 9005 028a ASR-2020ZCR
37660 9005 028b ASR-2025ZCR (Terminator)
37661 9005 028e ASR-2020SA (Skyhawk)
37662 9005 028f ASR-2025SA
37667 9005 0296 ASR-2240S
37668 9005 0297 ASR-4005SAS
37669 9005 0298 ASR-4000
[all …]
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/ARC/ |
| H A D | ARCInstrInfo.td | 304 defm ASR : ArcBinaryEXT5Inst<0b000010, "asr">;
|