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Searched refs:AR40XX_REG_WRITE (Results 1 – 9 of 9) sorted by relevance

/freebsd/sys/dev/etherswitch/ar40xx/
H A Dar40xx_hw_port.c81 AR40XX_REG_WRITE(sc, AR40XX_REG_PORT_STATUS(port), 0); in ar40xx_hw_port_init()
82 AR40XX_REG_WRITE(sc, AR40XX_REG_PORT_HEADER(port), 0); in ar40xx_hw_port_init()
83 AR40XX_REG_WRITE(sc, AR40XX_REG_PORT_VLAN0(port), 0); in ar40xx_hw_port_init()
104 AR40XX_REG_WRITE(sc, AR40XX_REG_PORT_STATUS(port), in ar40xx_hw_port_init()
115 AR40XX_REG_WRITE(sc, AR40XX_REG_PORT_VLAN1(port), reg); in ar40xx_hw_port_init()
119 AR40XX_REG_WRITE(sc, AR40XX_REG_PORT_LOOKUP(port), reg); in ar40xx_hw_port_init()
137 AR40XX_REG_WRITE(sc, AR40XX_REG_PORT_STATUS(port), 0); in ar40xx_hw_port_link_down()
160 AR40XX_REG_WRITE(sc, AR40XX_REG_PORT_STATUS(port), reg); in ar40xx_hw_port_link_up()
183 AR40XX_REG_WRITE(sc, AR40XX_REG_PORT_STATUS(0), reg); in ar40xx_hw_port_cpuport_setup()
187 AR40XX_REG_WRITE(sc, AR40XX_REG_PORT_STATUS(0), reg); in ar40xx_hw_port_cpuport_setup()
[all …]
H A Dar40xx_hw_atu.c95 AR40XX_REG_WRITE(sc, AR40XX_REG_ATU_FUNC, in ar40xx_hw_atu_flush_all()
126 AR40XX_REG_WRITE(sc, AR40XX_REG_ATU_FUNC, in ar40xx_hw_atu_flush_port()
153 AR40XX_REG_WRITE(sc, AR40XX_REG_ATU_FUNC, in ar40xx_hw_atu_fetch_entry()
155 AR40XX_REG_WRITE(sc, AR40XX_REG_ATU_DATA0, 0); in ar40xx_hw_atu_fetch_entry()
156 AR40XX_REG_WRITE(sc, AR40XX_REG_ATU_DATA1, 0); in ar40xx_hw_atu_fetch_entry()
157 AR40XX_REG_WRITE(sc, AR40XX_REG_ATU_DATA2, 0); in ar40xx_hw_atu_fetch_entry()
176 AR40XX_REG_WRITE(sc, AR40XX_REG_ATU_FUNC, val); in ar40xx_hw_atu_fetch_entry()
H A Dar40xx_hw_mirror.c83 AR40XX_REG_WRITE(sc, AR40XX_REG_FWD_CTRL0, reg); in ar40xx_hw_mirror_set_registers()
89 AR40XX_REG_WRITE(sc, AR40XX_REG_PORT_LOOKUP(port), reg); in ar40xx_hw_mirror_set_registers()
93 AR40XX_REG_WRITE(sc, AR40XX_REG_PORT_HOL_CTRL1(port), reg); in ar40xx_hw_mirror_set_registers()
109 AR40XX_REG_WRITE(sc, AR40XX_REG_FWD_CTRL0, reg); in ar40xx_hw_mirror_set_registers()
115 AR40XX_REG_WRITE(sc, in ar40xx_hw_mirror_set_registers()
125 AR40XX_REG_WRITE(sc, in ar40xx_hw_mirror_set_registers()
H A Dar40xx_hw.c120 AR40XX_REG_WRITE(sc, AR40XX_REG_FWD_CTRL0, reg); in ar40xx_hw_init_globals()
126 AR40XX_REG_WRITE(sc, AR40XX_REG_FWD_CTRL1, reg); in ar40xx_hw_init_globals()
132 AR40XX_REG_WRITE(sc, AR40XX_REG_MAX_FRAME_SIZE, reg); in ar40xx_hw_init_globals()
137 AR40XX_REG_WRITE(sc, AR40XX_REG_MODULE_EN, reg); in ar40xx_hw_init_globals()
140 AR40XX_REG_WRITE(sc, AR40XX_REG_EEE_CTRL, 0); in ar40xx_hw_init_globals()
145 AR40XX_REG_WRITE(sc, AR40XX_REG_PORT_FLOWCTRL_THRESH(0), reg); in ar40xx_hw_init_globals()
351 AR40XX_REG_WRITE(sc, AR40XX_REG_SW_MAC_ADDR0, ret0); in ar40xx_hw_write_switch_mac_address()
352 AR40XX_REG_WRITE(sc, AR40XX_REG_SW_MAC_ADDR1, ret1); in ar40xx_hw_write_switch_mac_address()
H A Dar40xx_hw_vtu.c92 AR40XX_REG_WRITE(sc, AR40XX_REG_VTU_FUNC0, val); in ar40xx_hw_vtu_op()
97 AR40XX_REG_WRITE(sc, AR40XX_REG_VTU_FUNC1, op); in ar40xx_hw_vtu_op()
H A Dar40xx_hw_psgmii.c353 AR40XX_REG_WRITE(sc, in ar40xx_hw_psgmii_self_test()
402 AR40XX_REG_WRITE(sc, AR40XX_REG_PORT_LOOKUP(phy + 1), reg); in ar40xx_hw_psgmii_self_test_clean()
H A Dar40xx_var.h37 #define AR40XX_REG_WRITE(sc, reg, val) do { \ macro
H A Dar40xx_hw_mib.c136 AR40XX_REG_WRITE(sc, AR40XX_REG_MIB_FUNC, reg); in ar40xx_hw_mib_op()
H A Dar40xx_main.c566 AR40XX_REG_WRITE(sc, addr, value); in ar40xx_writereg()