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Searched refs:AR40XX_REG_READ (Results 1 – 10 of 10) sorted by relevance

/freebsd/sys/dev/etherswitch/ar40xx/
H A Dar40xx_hw_mirror.c80 reg = AR40XX_REG_READ(sc, AR40XX_REG_FWD_CTRL0); in ar40xx_hw_mirror_set_registers()
87 reg = AR40XX_REG_READ(sc, AR40XX_REG_PORT_LOOKUP(port)); in ar40xx_hw_mirror_set_registers()
91 reg = AR40XX_REG_READ(sc, AR40XX_REG_PORT_HOL_CTRL1(port)); in ar40xx_hw_mirror_set_registers()
105 reg = AR40XX_REG_READ(sc, AR40XX_REG_FWD_CTRL0); in ar40xx_hw_mirror_set_registers()
112 reg = AR40XX_REG_READ(sc, in ar40xx_hw_mirror_set_registers()
122 reg = AR40XX_REG_READ(sc, in ar40xx_hw_mirror_set_registers()
H A Dar40xx_hw_atu.c174 val = AR40XX_REG_READ(sc, AR40XX_REG_ATU_FUNC); in ar40xx_hw_atu_fetch_entry()
186 ret0 = AR40XX_REG_READ(sc, AR40XX_REG_ATU_DATA0); in ar40xx_hw_atu_fetch_entry()
187 ret1 = AR40XX_REG_READ(sc, AR40XX_REG_ATU_DATA1); in ar40xx_hw_atu_fetch_entry()
188 ret2 = AR40XX_REG_READ(sc, AR40XX_REG_ATU_DATA2); in ar40xx_hw_atu_fetch_entry()
H A Dar40xx_hw.c129 reg = AR40XX_REG_READ(sc, AR40XX_REG_MAX_FRAME_SIZE); in ar40xx_hw_init_globals()
135 reg = AR40XX_REG_READ(sc, AR40XX_REG_MODULE_EN); in ar40xx_hw_init_globals()
285 t = AR40XX_REG_READ(sc, reg); in ar40xx_hw_wait_bit()
316 ret0 = AR40XX_REG_READ(sc, AR40XX_REG_SW_MAC_ADDR0); in ar40xx_hw_read_switch_mac_address()
317 ret1 = AR40XX_REG_READ(sc, AR40XX_REG_SW_MAC_ADDR1); in ar40xx_hw_read_switch_mac_address()
H A Dar40xx_hw_mib.c133 reg = AR40XX_REG_READ(sc, AR40XX_REG_MIB_FUNC); in ar40xx_hw_mib_op()
184 val = AR40XX_REG_READ(sc, base + ar40xx_mibs[i].offset); in ar40xx_hw_mib_fetch()
186 reg = AR40XX_REG_READ(sc, base + ar40xx_mibs[i].offset + 4); in ar40xx_hw_mib_fetch()
H A Dar40xx_main.c183 AR40XX_REG_READ(sc, AR40XX_REG_PORT_STATUS(val))); in ar40xx_sysctl_dump_port_state()
185 AR40XX_REG_READ(sc, AR40XX_REG_PORT_HEADER(val))); in ar40xx_sysctl_dump_port_state()
187 AR40XX_REG_READ(sc, AR40XX_REG_PORT_VLAN0(val))); in ar40xx_sysctl_dump_port_state()
189 AR40XX_REG_READ(sc, AR40XX_REG_PORT_VLAN1(val))); in ar40xx_sysctl_dump_port_state()
191 AR40XX_REG_READ(sc, AR40XX_REG_PORT_LOOKUP(val))); in ar40xx_sysctl_dump_port_state()
193 AR40XX_REG_READ(sc, AR40XX_REG_PORT_HOL_CTRL1(val))); in ar40xx_sysctl_dump_port_state()
195 val, AR40XX_REG_READ(sc, AR40XX_REG_PORT_FLOWCTRL_THRESH(val))); in ar40xx_sysctl_dump_port_state()
555 return AR40XX_REG_READ(sc, addr); in ar40xx_readreg()
H A Dar40xx_hw_port.c158 reg = AR40XX_REG_READ(sc, AR40XX_REG_PORT_STATUS(port)); in ar40xx_hw_port_link_up()
208 reg = AR40XX_REG_READ(sc, AR40XX_REG_PORT_VLAN0(port)); in ar40xx_hw_get_port_pvid()
H A Dar40xx_hw_psgmii.c350 reg = AR40XX_REG_READ(sc, in ar40xx_hw_psgmii_self_test()
400 reg = AR40XX_REG_READ(sc, AR40XX_REG_PORT_LOOKUP(phy + 1)); in ar40xx_hw_psgmii_self_test_clean()
H A Dar40xx_var.h41 #define AR40XX_REG_READ(sc, reg) bus_read_4(sc->sc_ess_mem_res, (reg)) macro
H A Dar40xx_hw_vtu.c179 reg = AR40XX_REG_READ(sc, AR40XX_REG_VTU_FUNC0); in ar40xx_hw_vtu_get_vlan()
H A Dar40xx_phy.c95 reg = AR40XX_REG_READ(sc, AR40XX_REG_PORT_STATUS(phy + 1)); in ar40xx_phy_tick()