| /freebsd/contrib/llvm-project/lldb/source/Plugins/Instruction/RISCV/ |
| H A D | RISCVInstructions.h | 126 I_TYPE_INST(ANDI);
277 SLTIU, XORI, ORI, ANDI, ADD, SUB, SLL, SLT, SLTU, XOR, SRL, SRA, OR, AND,
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| H A D | RISCVCInstructions.h | 256 return ANDI{rd, rd, uint32_t(imm)}; in DecodeC_ANDI()
257 return ANDI{rd, rd, uint32_t(int32_t(int8_t(imm | 0xc0)))}; in DecodeC_ANDI()
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| H A D | EmulateInstructionRISCV.cpp | 442 {"ANDI", 0x707F, 0x7013, DecodeIType<ANDI>},
778 bool operator()(ANDI inst) { in operator ()()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/ |
| H A D | LoongArchOptWInstrs.cpp | 205 case LoongArch::ANDI: { in hasAllNBitUsers()
336 case LoongArch::ANDI: in isSignExtendingOpW()
573 case LoongArch::ANDI: in isSignExtendedW()
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| H A D | LoongArchInstrInfo.cpp | 33 return MCInstBuilder(LoongArch::ANDI) in getNop()
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| H A D | LoongArchInstrInfo.td | 770 def ANDI : ALU_2RI12<0x03400000, uimm12>;
1277 def : PatGprImm<and, ANDI, uimm12>;
2227 def : InstAlias<"nop", (ANDI R0, R0, 0)>;
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVOptWInstrs.cpp | 223 case RISCV::ANDI: { in hasAllNBitUsers()
370 case RISCV::ANDI: in isSignExtendingOpW()
498 case RISCV::ANDI: in isSignExtendedW()
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| H A D | RISCVInstrInfoZb.td | 84 // Checks if this mask has a single 0 bit and cannot be used with ANDI.
158 // Check if (and r, i) can be optimized to (BCLRI (ANDI r, i0), i1),
567 (BCLRI (XLenVT (ANDI GPR:$r, (BCLRIANDIMaskLow BCLRIANDIMask:$i))),
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| H A D | RISCVInstrInfoZc.td | 296 def : CompressPat<(ANDI GPRC:$rs1, GPRC:$rs1, 255),
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| H A D | RISCVInstrInfo.td | 662 def ANDI : ALU_ri<0b111, "andi">;
1024 (ANDI GPR:$rd, GPR:$rs1, simm12:$imm12)>;
1069 def : InstAlias<"zext.b $rd, $rs", (ANDI GPR:$rd, GPR:$rs, 0xFF), 0>;
1263 def : PatGprSimm12<and, ANDI>;
1893 (ANDI GPR:$rs1, u32simm12:$imm)>;
2009 (ANDI GPR:$rs1, (i64 (as_i64imm $imm)))>;
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| H A D | RISCVExpandPseudoInsts.cpp | 221 case RISCV::PseudoCCANDI: NewOpc = RISCV::ANDI; break; in expandCCOp()
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| H A D | RISCVRegisterInfo.cpp | 847 case RISCV::ANDI: { in getRegAllocationHints()
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| H A D | RISCVAsmPrinter.cpp | 710 MCInstBuilder(RISCV::ANDI).addReg(RISCV::X28).addReg(Reg).addImm(0xF), in EmitHwasanMemaccessSymbols()
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| H A D | RISCVFrameLowering.cpp | 727 BuildMI(MBB, MBBI, DL, TII->get(RISCV::ANDI), SPReg) in emitPrologue()
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| H A D | RISCVInstrInfo.cpp | 1309 case RISCV::ANDI: return RISCV::PseudoCCANDI; break; in getPredicatedOpcode()
3785 return MI.getOpcode() == RISCV::ANDI && MI.getOperand(1).isReg() && in isRVVWholeLoadStore()
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| H A D | RISCVInstrInfoC.td | 932 def : CompressPat<(ANDI GPRC:$rs1, GPRC:$rs1, simm6:$imm),
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| H A D | RISCVISelDAGToDAG.cpp | 665 case ISD::AND: BinOpc = RISCV::ANDI; break; in tryShrinkShlLogicImm()
3180 case RISCV::ANDI: in hasAllNBitUsers()
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| /freebsd/contrib/llvm-project/lld/ELF/Arch/ |
| H A D | LoongArch.cpp | 55 ANDI = 0x03400000, enumerator
373 write32le(buf + 12, insn(ANDI, R_ZERO, R_ZERO, 0)); in writePlt()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | P9InstrResources.td | 133 (instregex "ANDI(S)?(8)?(_rec)?$"),
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AVR/ |
| H A D | AVRInstrInfo.td | 586 // ANDI Rd+1:Rd, K+1:K
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