| /freebsd/contrib/llvm-project/lldb/source/Plugins/Instruction/RISCV/ |
| H A D | RISCVInstructions.h | 126 I_TYPE_INST(ANDI);
277 SLTIU, XORI, ORI, ANDI, ADD, SUB, SLL, SLT, SLTU, XOR, SRL, SRA, OR, AND,
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| H A D | RISCVCInstructions.h | 256 return ANDI{rd, rd, uint32_t(imm)}; in DecodeC_ANDI()
257 return ANDI{rd, rd, uint32_t(int32_t(int8_t(imm | 0xc0)))}; in DecodeC_ANDI()
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| H A D | EmulateInstructionRISCV.cpp | 442 {"ANDI", 0x707F, 0x7013, DecodeIType<ANDI>},
779 bool operator()(ANDI inst) { in operator ()()
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| /freebsd/contrib/llvm-project/lld/ELF/Arch/ |
| H A D | LoongArch.cpp | 63 ANDI = 0x03400000, enumerator
396 write32le(buf + 12, insn(ANDI, R_ZERO, R_ZERO, 0)); in writePlt()
1063 write32le(loc, insn(ANDI, R_ZERO, R_ZERO, 0)); // nop in tlsIeToLe()
1107 write32le(loc, insn(ANDI, R_ZERO, R_ZERO, 0)); // nop in tlsdescToIe()
1139 write32le(loc, insn(ANDI, R_ZERO, R_ZERO, 0)); // nop in tlsdescToLe()
1143 write32le(loc, insn(ANDI, R_ZERO, R_ZERO, 0)); // nop in tlsdescToLe()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVOptWInstrs.cpp | 239 case RISCV::ANDI: { in hasAllNBitUsers()
390 case RISCV::ANDI: in isSignExtendingOpW()
518 case RISCV::ANDI: in isSignExtendedW()
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| H A D | RISCVInstrPredicates.td | 41 CheckOpcode<[ANDI]>,
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| H A D | RISCVInstrInfoZb.td | 73 // Checks if this mask has a single 0 bit and cannot be used with ANDI.
147 // Check if (and r, i) can be optimized to (BCLRI (ANDI r, i0), i1),
573 (BCLRI (XLenVT (ANDI GPR:$r, (BCLRIANDIMaskLow BCLRIANDIMask:$i))),
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| H A D | RISCVInstrInfoZc.td | 307 def : CompressPat<(ANDI GPRC:$rs1, GPRC:$rs1, 255),
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| H A D | RISCVExpandPseudoInsts.cpp | 230 case RISCV::PseudoCCANDI: NewOpc = RISCV::ANDI; break; in expandCCOp()
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| H A D | RISCVInstrInfo.td | 783 def ANDI : ALU_ri<0b111, "andi">;
1169 (ANDI GPR:$rd, GPR:$rs1, simm12:$imm12)>;
1211 def : InstAlias<"zext.b $rd, $rs", (ANDI GPR:$rd, GPR:$rs, 0xFF)>;
1444 def : PatGprSimm12<and, ANDI>;
2160 def : PatGprImm<binop_allwusers<and>, ANDI, u32simm12>;
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| H A D | RISCVRegisterInfo.cpp | 949 case RISCV::ANDI: { in getRegAllocationHints()
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| H A D | RISCVAsmPrinter.cpp | 825 MCInstBuilder(RISCV::ANDI).addReg(RISCV::X28).addReg(Reg).addImm(0xF), in EmitHwasanMemaccessSymbols()
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| H A D | RISCVInstrInfoXqci.td | 1692 (ANDI GPRNoX0:$rs1, GPRNoX0:$rs2, simm12:$imm)>;
1701 (ANDI GPRNoX0:$rd, GPRNoX0:$rd, simm12:$imm)>;
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| H A D | RISCVInstrInfoC.td | 932 def : CompressPat<(ANDI GPRC:$rs1, GPRC:$rs1, simm6:$imm),
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| H A D | RISCVISelDAGToDAG.cpp | 579 case ISD::AND: BinOpc = RISCV::ANDI; break; in tryShrinkShlLogicImm()
3703 case RISCV::ANDI: in hasAllNBitUsers()
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| H A D | RISCVFrameLowering.cpp | 1120 BuildMI(MBB, MBBI, DL, TII->get(RISCV::ANDI), SPReg) in emitPrologue()
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| H A D | RISCVInstrInfo.cpp | 1661 case RISCV::ANDI: return RISCV::PseudoCCANDI; break; in getPredicatedOpcode()
4192 case RISCV::ANDI: in simplifyInstruction()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/ |
| H A D | LoongArchOptWInstrs.cpp | 235 case LoongArch::ANDI: { in hasAllNBitUsers()
366 case LoongArch::ANDI: in isSignExtendingOpW()
604 case LoongArch::ANDI: in isSignExtendedW()
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| H A D | LoongArchFloat64InstrInfo.td | 157 (SLTU R0, (ANDI (MOVFR2GR_S_64 (FCLASS_D FPR64:$fj)),
162 (SLTU R0, (ANDI (MOVFR2GR_D (FCLASS_D FPR64:$fj)),
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| H A D | LoongArchFloat32InstrInfo.td | 184 (SLTU R0, (ANDI (MOVFR2GR_S (FCLASS_S FPR32:$fj)),
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| H A D | LoongArchInstrInfo.cpp | 34 return MCInstBuilder(LoongArch::ANDI) in getNop()
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| H A D | LoongArchInstrInfo.td | 816 def ANDI : ALU_2RI12<0x03400000, uimm12>;
1346 def : PatGprImm<and, ANDI, uimm12>;
2411 def : InstAlias<"nop", (ANDI R0, R0, 0)>;
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/GISel/ |
| H A D | RISCVInstructionSelector.cpp | 244 case RISCV::ANDI: in hasAllNBitUsers()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | P9InstrResources.td | 133 (instregex "ANDI(S)?(8)?(_rec)?$"),
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AVR/ |
| H A D | AVRInstrInfo.td | 572 // ANDI Rd+1:Rd, K+1:K
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