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Searched refs:AGPR (Results 1 – 10 of 10) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DGCNRegPressure.h32 enum RegKind { SGPR, VGPR, AGPR, TOTAL_KINDS }; enumerator
38 bool empty() const { return !Value[SGPR] && !Value[VGPR] && !Value[AGPR]; } in empty()
48 return Value[AGPR] ? getUnifiedVGPRNum(Value[VGPR], Value[AGPR]) in getVGPRNum()
51 return std::max(Value[VGPR], Value[AGPR]); in getVGPRNum()
65 unsigned getAGPRNum() const { return Value[AGPR]; } in getAGPRNum()
68 return std::max(Value[TOTAL_KINDS + VGPR], Value[TOTAL_KINDS + AGPR]); in getVGPRTuplesWeight()
H A DSIRegisterInfo.td322 defm AGPR#Index :
661 (add (sequence "AGPR%u_LO16", 0, 255))> {
670 (add (sequence "AGPR%u", 0, 255))> {
678 // AGPR 64-bit registers
681 // AGPR 96-bit registers
684 // AGPR 128-bit registers
687 // AGPR 160-bit registers
690 // AGPR 192-bit registers
693 // AGPR 224-bit registers
696 // AGPR 256-bit registers
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H A DAMDGPURegisterBanks.td20 def AGPRRegBank : RegisterBank <"AGPR",
H A DAMDGPUCallingConv.td90 (sequence "AGPR%u", 32, 255)
185 (sequence "AGPR%u", 0, 255)
H A DAMDGPUGenRegisterBankInfo.def94 {0, 32, AGPRRegBank}, // AGPR begin
H A DSIInstructions.td143 // 32-bit materialize immediate which supports AGPR or VGPR. Typically
145 // allocated to an AGPR in which case it will lower to
153 // Imprecise, technically if AGPR it's VOP3 and VOP1 for AGPR. But
1038 // VGPR or AGPR spill instructions. In case of AGPR spilling a temp register
1039 // needs to be used and an extra instruction to move between VGPR and AGPR.
H A DVOP3PInstructions.td811 // Does this MFMA use "AGPR" or "VGPR" for srcC/vdst
918 MFMATable<0, "AGPR", NAME # "_e64">;
932 MFMATable<1, "AGPR", NAME # "_e64", NAME # "_mac_e64">;
954 MFMATable<0, "AGPR", NAME # "_e64">;
966 MFMATable<1, "AGPR", NAME # "_e64">;
H A DGCNRegPressure.cpp41 return STI->isSGPRClass(RC) ? SGPR : (STI->isAGPRClass(RC) ? AGPR : VGPR); in getRegKind()
H A DSIInstrInfo.td2525 // Return an AGPR+VGPR operand class for the given VGPR register class.
3285 let ValueCols = [["AGPR"]];
H A DVOPInstructions.td510 bits<10> vdst; // VGPR or AGPR, but not SGPR. vdst{8} is not encoded in the instruction.