1 /* SPDX-License-Identifier: BSD-3-Clause */ 2 /* Copyright(c) 2007-2022 Intel Corporation */ 3 #ifndef ADF_DEV_ERR_H_ 4 #define ADF_DEV_ERR_H_ 5 6 #include <sys/types.h> 7 #include <dev/pci/pcivar.h> 8 #include "adf_accel_devices.h" 9 10 #define ADF_ERRSOU0 (0x3A000 + 0x00) 11 #define ADF_ERRSOU1 (0x3A000 + 0x04) 12 #define ADF_ERRSOU2 (0x3A000 + 0x08) 13 #define ADF_ERRSOU3 (0x3A000 + 0x0C) 14 #define ADF_ERRSOU4 (0x3A000 + 0xD0) 15 #define ADF_ERRSOU5 (0x3A000 + 0xD8) 16 #define ADF_ERRMSK0 (0x3A000 + 0x10) 17 #define ADF_ERRMSK1 (0x3A000 + 0x14) 18 #define ADF_ERRMSK2 (0x3A000 + 0x18) 19 #define ADF_ERRMSK3 (0x3A000 + 0x1C) 20 #define ADF_ERRMSK4 (0x3A000 + 0xD4) 21 #define ADF_ERRMSK5 (0x3A000 + 0xDC) 22 #define ADF_EMSK3_CPM0_MASK BIT(2) 23 #define ADF_EMSK3_CPM1_MASK BIT(3) 24 #define ADF_EMSK5_CPM2_MASK BIT(16) 25 #define ADF_EMSK5_CPM3_MASK BIT(17) 26 #define ADF_EMSK5_CPM4_MASK BIT(18) 27 #define ADF_RICPPINTSTS (0x3A000 + 0x114) 28 #define ADF_RIERRPUSHID (0x3A000 + 0x118) 29 #define ADF_RIERRPULLID (0x3A000 + 0x11C) 30 #define ADF_CPP_CFC_ERR_STATUS (0x30000 + 0xC04) 31 #define ADF_CPP_CFC_ERR_PPID (0x30000 + 0xC08) 32 #define ADF_TICPPINTSTS (0x3A400 + 0x13C) 33 #define ADF_TIERRPUSHID (0x3A400 + 0x140) 34 #define ADF_TIERRPULLID (0x3A400 + 0x144) 35 #define ADF_SECRAMUERR (0x3AC00 + 0x04) 36 #define ADF_SECRAMUERRAD (0x3AC00 + 0x0C) 37 #define ADF_CPPMEMTGTERR (0x3AC00 + 0x10) 38 #define ADF_ERRPPID (0x3AC00 + 0x14) 39 #define ADF_INTSTATSSM(i) ((i)*0x4000 + 0x04) 40 #define ADF_INTSTATSSM_SHANGERR BIT(13) 41 #define ADF_PPERR(i) ((i)*0x4000 + 0x08) 42 #define ADF_PPERRID(i) ((i)*0x4000 + 0x0C) 43 #define ADF_CERRSSMSH(i) ((i)*0x4000 + 0x10) 44 #define ADF_UERRSSMSH(i) ((i)*0x4000 + 0x18) 45 #define ADF_UERRSSMSHAD(i) ((i)*0x4000 + 0x1C) 46 #define ADF_SLICEHANGSTATUS(i) ((i)*0x4000 + 0x4C) 47 #define ADF_SLICE_HANG_AUTH0_MASK BIT(0) 48 #define ADF_SLICE_HANG_AUTH1_MASK BIT(1) 49 #define ADF_SLICE_HANG_AUTH2_MASK BIT(2) 50 #define ADF_SLICE_HANG_CPHR0_MASK BIT(4) 51 #define ADF_SLICE_HANG_CPHR1_MASK BIT(5) 52 #define ADF_SLICE_HANG_CPHR2_MASK BIT(6) 53 #define ADF_SLICE_HANG_CMP0_MASK BIT(8) 54 #define ADF_SLICE_HANG_CMP1_MASK BIT(9) 55 #define ADF_SLICE_HANG_XLT0_MASK BIT(12) 56 #define ADF_SLICE_HANG_XLT1_MASK BIT(13) 57 #define ADF_SLICE_HANG_MMP0_MASK BIT(16) 58 #define ADF_SLICE_HANG_MMP1_MASK BIT(17) 59 #define ADF_SLICE_HANG_MMP2_MASK BIT(18) 60 #define ADF_SLICE_HANG_MMP3_MASK BIT(19) 61 #define ADF_SLICE_HANG_MMP4_MASK BIT(20) 62 #define ADF_SSMWDT(i) ((i)*0x4000 + 0x54) 63 #define ADF_SSMWDTPKE(i) ((i)*0x4000 + 0x58) 64 #define ADF_SHINTMASKSSM(i) ((i)*0x4000 + 0x1018) 65 #define ADF_ENABLE_SLICE_HANG 0x000000 66 #define ADF_MAX_MMP (5) 67 #define ADF_MMP_BASE(i) ((i)*0x1000 % 0x3800) 68 #define ADF_CERRSSMMMP(i, n) ((i)*0x4000 + ADF_MMP_BASE(n) + 0x380) 69 #define ADF_UERRSSMMMP(i, n) ((i)*0x4000 + ADF_MMP_BASE(n) + 0x388) 70 #define ADF_UERRSSMMMPAD(i, n) ((i)*0x4000 + ADF_MMP_BASE(n) + 0x38C) 71 72 bool adf_handle_slice_hang(struct adf_accel_dev *accel_dev, 73 u8 accel_num, 74 struct resource *csr, 75 u32 slice_hang_offset); 76 bool adf_check_slice_hang(struct adf_accel_dev *accel_dev); 77 void adf_print_err_registers(struct adf_accel_dev *accel_dev); 78 79 #endif 80