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Searched refs:ADD_VL (Results 1 – 3 of 3) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.h236 ADD_VL, enumerator
H A DRISCVISelLowering.cpp4869 // Note the ADD_VL and VLMULU_VL should get selected as vwmaccu.vx in getWideningInterleave()
4870 Interleaved = DAG.getNode(RISCVISD::ADD_VL, DL, WideContainerVT, in getWideningInterleave()
6101 if (Opcode >= RISCVISD::ADD_VL && Opcode <= RISCVISD::VFMAX_VL) in hasMergeOp()
10596 DAG.getNode(RISCVISD::ADD_VL, DL, IdxVT, Idx, VLMax, Idx, OddMask, VL); in lowerVECTOR_INTERLEAVE()
14390 case RISCVISD::ADD_VL: in getSExtOpcode()
14413 case RISCVISD::ADD_VL: in getZExtOpcode()
14464 case RISCVISD::ADD_VL: in getWOpcode()
14620 case RISCVISD::ADD_VL: in isSupportedRoot()
14712 case RISCVISD::ADD_VL: in isCommutative()
14924 case RISCVISD::ADD_VL in getSupportedFoldings()
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H A DRISCVInstrInfoVVLPatterns.td98 def riscv_add_vl : SDNode<"RISCVISD::ADD_VL", SDT_RISCVIntBinOp_VL, [SDNPCommutative]>;