1 /****************************************************************************** 2 * 3 * Name: actbl1.h - Additional ACPI table definitions 4 * 5 *****************************************************************************/ 6 7 /****************************************************************************** 8 * 9 * 1. Copyright Notice 10 * 11 * Some or all of this work - Copyright (c) 1999 - 2026, Intel Corp. 12 * All rights reserved. 13 * 14 * 2. License 15 * 16 * 2.1. This is your license from Intel Corp. under its intellectual property 17 * rights. You may have additional license terms from the party that provided 18 * you this software, covering your right to use that party's intellectual 19 * property rights. 20 * 21 * 2.2. Intel grants, free of charge, to any person ("Licensee") obtaining a 22 * copy of the source code appearing in this file ("Covered Code") an 23 * irrevocable, perpetual, worldwide license under Intel's copyrights in the 24 * base code distributed originally by Intel ("Original Intel Code") to copy, 25 * make derivatives, distribute, use and display any portion of the Covered 26 * Code in any form, with the right to sublicense such rights; and 27 * 28 * 2.3. Intel grants Licensee a non-exclusive and non-transferable patent 29 * license (with the right to sublicense), under only those claims of Intel 30 * patents that are infringed by the Original Intel Code, to make, use, sell, 31 * offer to sell, and import the Covered Code and derivative works thereof 32 * solely to the minimum extent necessary to exercise the above copyright 33 * license, and in no event shall the patent license extend to any additions 34 * to or modifications of the Original Intel Code. No other license or right 35 * is granted directly or by implication, estoppel or otherwise; 36 * 37 * The above copyright and patent license is granted only if the following 38 * conditions are met: 39 * 40 * 3. Conditions 41 * 42 * 3.1. Redistribution of Source with Rights to Further Distribute Source. 43 * Redistribution of source code of any substantial portion of the Covered 44 * Code or modification with rights to further distribute source must include 45 * the above Copyright Notice, the above License, this list of Conditions, 46 * and the following Disclaimer and Export Compliance provision. In addition, 47 * Licensee must cause all Covered Code to which Licensee contributes to 48 * contain a file documenting the changes Licensee made to create that Covered 49 * Code and the date of any change. Licensee must include in that file the 50 * documentation of any changes made by any predecessor Licensee. Licensee 51 * must include a prominent statement that the modification is derived, 52 * directly or indirectly, from Original Intel Code. 53 * 54 * 3.2. Redistribution of Source with no Rights to Further Distribute Source. 55 * Redistribution of source code of any substantial portion of the Covered 56 * Code or modification without rights to further distribute source must 57 * include the following Disclaimer and Export Compliance provision in the 58 * documentation and/or other materials provided with distribution. In 59 * addition, Licensee may not authorize further sublicense of source of any 60 * portion of the Covered Code, and must include terms to the effect that the 61 * license from Licensee to its licensee is limited to the intellectual 62 * property embodied in the software Licensee provides to its licensee, and 63 * not to intellectual property embodied in modifications its licensee may 64 * make. 65 * 66 * 3.3. Redistribution of Executable. Redistribution in executable form of any 67 * substantial portion of the Covered Code or modification must reproduce the 68 * above Copyright Notice, and the following Disclaimer and Export Compliance 69 * provision in the documentation and/or other materials provided with the 70 * distribution. 71 * 72 * 3.4. Intel retains all right, title, and interest in and to the Original 73 * Intel Code. 74 * 75 * 3.5. Neither the name Intel nor any other trademark owned or controlled by 76 * Intel shall be used in advertising or otherwise to promote the sale, use or 77 * other dealings in products derived from or relating to the Covered Code 78 * without prior written authorization from Intel. 79 * 80 * 4. Disclaimer and Export Compliance 81 * 82 * 4.1. INTEL MAKES NO WARRANTY OF ANY KIND REGARDING ANY SOFTWARE PROVIDED 83 * HERE. ANY SOFTWARE ORIGINATING FROM INTEL OR DERIVED FROM INTEL SOFTWARE 84 * IS PROVIDED "AS IS," AND INTEL WILL NOT PROVIDE ANY SUPPORT, ASSISTANCE, 85 * INSTALLATION, TRAINING OR OTHER SERVICES. INTEL WILL NOT PROVIDE ANY 86 * UPDATES, ENHANCEMENTS OR EXTENSIONS. INTEL SPECIFICALLY DISCLAIMS ANY 87 * IMPLIED WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT AND FITNESS FOR A 88 * PARTICULAR PURPOSE. 89 * 90 * 4.2. IN NO EVENT SHALL INTEL HAVE ANY LIABILITY TO LICENSEE, ITS LICENSEES 91 * OR ANY OTHER THIRD PARTY, FOR ANY LOST PROFITS, LOST DATA, LOSS OF USE OR 92 * COSTS OF PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES, OR FOR ANY INDIRECT, 93 * SPECIAL OR CONSEQUENTIAL DAMAGES ARISING OUT OF THIS AGREEMENT, UNDER ANY 94 * CAUSE OF ACTION OR THEORY OF LIABILITY, AND IRRESPECTIVE OF WHETHER INTEL 95 * HAS ADVANCE NOTICE OF THE POSSIBILITY OF SUCH DAMAGES. THESE LIMITATIONS 96 * SHALL APPLY NOTWITHSTANDING THE FAILURE OF THE ESSENTIAL PURPOSE OF ANY 97 * LIMITED REMEDY. 98 * 99 * 4.3. Licensee shall not export, either directly or indirectly, any of this 100 * software or system incorporating such software without first obtaining any 101 * required license or other approval from the U. S. Department of Commerce or 102 * any other agency or department of the United States Government. In the 103 * event Licensee exports any such software from the United States or 104 * re-exports any such software from a foreign destination, Licensee shall 105 * ensure that the distribution and export/re-export of the software is in 106 * compliance with all laws, regulations, orders, or other restrictions of the 107 * U.S. Export Administration Regulations. Licensee agrees that neither it nor 108 * any of its subsidiaries will export/re-export any technical data, process, 109 * software, or service, directly or indirectly, to any country for which the 110 * United States government or any agency thereof requires an export license, 111 * other governmental approval, or letter of assurance, without first obtaining 112 * such license, approval or letter. 113 * 114 ***************************************************************************** 115 * 116 * Alternatively, you may choose to be licensed under the terms of the 117 * following license: 118 * 119 * Redistribution and use in source and binary forms, with or without 120 * modification, are permitted provided that the following conditions 121 * are met: 122 * 1. Redistributions of source code must retain the above copyright 123 * notice, this list of conditions, and the following disclaimer, 124 * without modification. 125 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 126 * substantially similar to the "NO WARRANTY" disclaimer below 127 * ("Disclaimer") and any redistribution must be conditioned upon 128 * including a substantially similar Disclaimer requirement for further 129 * binary redistribution. 130 * 3. Neither the names of the above-listed copyright holders nor the names 131 * of any contributors may be used to endorse or promote products derived 132 * from this software without specific prior written permission. 133 * 134 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 135 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 136 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 137 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 138 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 139 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 140 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 141 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 142 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 143 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 144 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 145 * 146 * Alternatively, you may choose to be licensed under the terms of the 147 * GNU General Public License ("GPL") version 2 as published by the Free 148 * Software Foundation. 149 * 150 *****************************************************************************/ 151 152 #ifndef __ACTBL1_H__ 153 #define __ACTBL1_H__ 154 155 156 /******************************************************************************* 157 * 158 * Additional ACPI Tables 159 * 160 * These tables are not consumed directly by the ACPICA subsystem, but are 161 * included here to support device drivers and the AML disassembler. 162 * 163 ******************************************************************************/ 164 165 166 /* 167 * Values for description table header signatures for tables defined in this 168 * file. Useful because they make it more difficult to inadvertently type in 169 * the wrong signature. 170 */ 171 #define ACPI_SIG_AEST "AEST" /* Arm Error Source Table */ 172 #define ACPI_SIG_ASF "ASF!" /* Alert Standard Format table */ 173 #define ACPI_SIG_ASPT "ASPT" /* AMD Secure Processor Table */ 174 #define ACPI_SIG_BERT "BERT" /* Boot Error Record Table */ 175 #define ACPI_SIG_BGRT "BGRT" /* Boot Graphics Resource Table */ 176 #define ACPI_SIG_BOOT "BOOT" /* Simple Boot Flag Table */ 177 #define ACPI_SIG_CEDT "CEDT" /* CXL Early Discovery Table */ 178 #define ACPI_SIG_CPEP "CPEP" /* Corrected Platform Error Polling table */ 179 #define ACPI_SIG_CSRT "CSRT" /* Core System Resource Table */ 180 #define ACPI_SIG_DBG2 "DBG2" /* Debug Port table type 2 */ 181 #define ACPI_SIG_DBGP "DBGP" /* Debug Port table */ 182 #define ACPI_SIG_DMAR "DMAR" /* DMA Remapping table */ 183 #define ACPI_SIG_DRTM "DRTM" /* Dynamic Root of Trust for Measurement table */ 184 #define ACPI_SIG_DTPR "DTPR" /* DMA TXT Protection Ranges table */ 185 #define ACPI_SIG_ECDT "ECDT" /* Embedded Controller Boot Resources Table */ 186 #define ACPI_SIG_EINJ "EINJ" /* Error Injection table */ 187 #define ACPI_SIG_ERST "ERST" /* Error Record Serialization Table */ 188 #define ACPI_SIG_FPDT "FPDT" /* Firmware Performance Data Table */ 189 #define ACPI_SIG_GTDT "GTDT" /* Generic Timer Description Table */ 190 #define ACPI_SIG_HEST "HEST" /* Hardware Error Source Table */ 191 #define ACPI_SIG_HMAT "HMAT" /* Heterogeneous Memory Attributes Table */ 192 #define ACPI_SIG_HPET "HPET" /* High Precision Event Timer table */ 193 #define ACPI_SIG_IBFT "IBFT" /* iSCSI Boot Firmware Table */ 194 #define ACPI_SIG_MSCT "MSCT" /* Maximum System Characteristics Table*/ 195 196 #define ACPI_SIG_S3PT "S3PT" /* S3 Performance (sub)Table */ 197 #define ACPI_SIG_PCCS "PCC" /* PCC Shared Memory Region */ 198 199 200 /* Reserved table signatures */ 201 202 #define ACPI_SIG_MATR "MATR" /* Memory Address Translation Table */ 203 #define ACPI_SIG_MSDM "MSDM" /* Microsoft Data Management Table */ 204 205 /* 206 * These tables have been seen in the field, but no definition has been found 207 */ 208 #ifdef ACPI_UNDEFINED_TABLES 209 #define ACPI_SIG_ATKG "ATKG" 210 #define ACPI_SIG_GSCI "GSCI" /* GMCH SCI table */ 211 #define ACPI_SIG_IEIT "IEIT" 212 #endif 213 214 /* 215 * All tables must be byte-packed to match the ACPI specification, since 216 * the tables are provided by the system BIOS. 217 */ 218 #pragma pack(1) 219 220 /* 221 * Note: C bitfields are not used for this reason: 222 * 223 * "Bitfields are great and easy to read, but unfortunately the C language 224 * does not specify the layout of bitfields in memory, which means they are 225 * essentially useless for dealing with packed data in on-disk formats or 226 * binary wire protocols." (Or ACPI tables and buffers.) "If you ask me, 227 * this decision was a design error in C. Ritchie could have picked an order 228 * and stuck with it." Norman Ramsey. 229 * See http://stackoverflow.com/a/1053662/41661 230 */ 231 232 233 /******************************************************************************* 234 * 235 * Common subtable headers 236 * 237 ******************************************************************************/ 238 239 /* Generic subtable header (used in MADT, SRAT, etc.) */ 240 241 typedef struct acpi_subtable_header 242 { 243 UINT8 Type; 244 UINT8 Length; 245 246 } ACPI_SUBTABLE_HEADER; 247 248 249 /* Subtable header for WHEA tables (EINJ, ERST, WDAT) */ 250 251 typedef struct acpi_whea_header 252 { 253 UINT8 Action; 254 UINT8 Instruction; 255 UINT8 Flags; 256 UINT8 Reserved; 257 ACPI_GENERIC_ADDRESS RegisterRegion; 258 UINT64 Value; /* Value used with Read/Write register */ 259 UINT64 Mask; /* Bitmask required for this register instruction */ 260 261 } ACPI_WHEA_HEADER; 262 263 264 /* Larger subtable header (when Length can exceed 255) */ 265 266 typedef struct acpi_subtbl_hdr_16 267 { 268 UINT16 Type; 269 UINT16 Length; 270 271 } ACPI_SUBTBL_HDR_16; 272 273 274 /******************************************************************************* 275 * 276 * ASF - Alert Standard Format table (Signature "ASF!") 277 * Revision 0x10 278 * 279 * Conforms to the Alert Standard Format Specification V2.0, 23 April 2003 280 * 281 ******************************************************************************/ 282 283 typedef struct acpi_table_asf 284 { 285 ACPI_TABLE_HEADER Header; /* Common ACPI table header */ 286 287 } ACPI_TABLE_ASF; 288 289 290 /* ASF subtable header */ 291 292 typedef struct acpi_asf_header 293 { 294 UINT8 Type; 295 UINT8 Reserved; 296 UINT16 Length; 297 298 } ACPI_ASF_HEADER; 299 300 301 /* Values for Type field above */ 302 303 enum AcpiAsfType 304 { 305 ACPI_ASF_TYPE_INFO = 0, 306 ACPI_ASF_TYPE_ALERT = 1, 307 ACPI_ASF_TYPE_CONTROL = 2, 308 ACPI_ASF_TYPE_BOOT = 3, 309 ACPI_ASF_TYPE_ADDRESS = 4, 310 ACPI_ASF_TYPE_RESERVED = 5 311 }; 312 313 /* 314 * ASF subtables 315 */ 316 317 /* 0: ASF Information */ 318 319 typedef struct acpi_asf_info 320 { 321 ACPI_ASF_HEADER Header; 322 UINT8 MinResetValue; 323 UINT8 MinPollInterval; 324 UINT16 SystemId; 325 UINT32 MfgId; 326 UINT8 Flags; 327 UINT8 Reserved2[3]; 328 329 } ACPI_ASF_INFO; 330 331 /* Masks for Flags field above */ 332 333 #define ACPI_ASF_SMBUS_PROTOCOLS (1) 334 335 336 /* 1: ASF Alerts */ 337 338 typedef struct acpi_asf_alert 339 { 340 ACPI_ASF_HEADER Header; 341 UINT8 AssertMask; 342 UINT8 DeassertMask; 343 UINT8 Alerts; 344 UINT8 DataLength; 345 346 } ACPI_ASF_ALERT; 347 348 typedef struct acpi_asf_alert_data 349 { 350 UINT8 Address; 351 UINT8 Command; 352 UINT8 Mask; 353 UINT8 Value; 354 UINT8 SensorType; 355 UINT8 Type; 356 UINT8 Offset; 357 UINT8 SourceType; 358 UINT8 Severity; 359 UINT8 SensorNumber; 360 UINT8 Entity; 361 UINT8 Instance; 362 363 } ACPI_ASF_ALERT_DATA; 364 365 366 /* 2: ASF Remote Control */ 367 368 typedef struct acpi_asf_remote 369 { 370 ACPI_ASF_HEADER Header; 371 UINT8 Controls; 372 UINT8 DataLength; 373 UINT16 Reserved2; 374 375 } ACPI_ASF_REMOTE; 376 377 typedef struct acpi_asf_control_data 378 { 379 UINT8 Function; 380 UINT8 Address; 381 UINT8 Command; 382 UINT8 Value; 383 384 } ACPI_ASF_CONTROL_DATA; 385 386 387 /* 3: ASF RMCP Boot Options */ 388 389 typedef struct acpi_asf_rmcp 390 { 391 ACPI_ASF_HEADER Header; 392 UINT8 Capabilities[7]; 393 UINT8 CompletionCode; 394 UINT32 EnterpriseId; 395 UINT8 Command; 396 UINT16 Parameter; 397 UINT16 BootOptions; 398 UINT16 OemParameters; 399 400 } ACPI_ASF_RMCP; 401 402 403 /* 4: ASF Address */ 404 405 typedef struct acpi_asf_address 406 { 407 ACPI_ASF_HEADER Header; 408 UINT8 EpromAddress; 409 UINT8 Devices; 410 411 } ACPI_ASF_ADDRESS; 412 413 /******************************************************************************* 414 * 415 * ASPT - AMD Secure Processor Table (Signature "ASPT") 416 * Revision 0x1 417 * 418 * Conforms to AMD Socket SP5/SP6 Platform ASPT Rev1 Specification, 419 * 12 September 2022 420 * 421 ******************************************************************************/ 422 423 typedef struct acpi_table_aspt 424 { 425 ACPI_TABLE_HEADER Header; /* Common ACPI table header */ 426 UINT32 NumEntries; 427 428 } ACPI_TABLE_ASPT; 429 430 431 /* ASPT subtable header */ 432 433 typedef struct acpi_aspt_header 434 { 435 UINT16 Type; 436 UINT16 Length; 437 438 } ACPI_ASPT_HEADER; 439 440 441 /* Values for Type field above */ 442 443 enum AcpiAsptType 444 { 445 ACPI_ASPT_TYPE_GLOBAL_REGS = 0, 446 ACPI_ASPT_TYPE_SEV_MBOX_REGS = 1, 447 ACPI_ASPT_TYPE_ACPI_MBOX_REGS = 2, 448 ACPI_ASPT_TYPE_UNKNOWN = 3, 449 }; 450 451 /* 452 * ASPT subtables 453 */ 454 455 /* 0: ASPT Global Registers */ 456 457 typedef struct acpi_aspt_global_regs 458 { 459 ACPI_ASPT_HEADER Header; 460 UINT32 Reserved; 461 UINT64 FeatureRegAddr; 462 UINT64 IrqEnRegAddr; 463 UINT64 IrqStRegAddr; 464 465 } ACPI_ASPT_GLOBAL_REGS; 466 467 468 /* 1: ASPT SEV Mailbox Registers */ 469 470 typedef struct acpi_aspt_sev_mbox_regs 471 { 472 ACPI_ASPT_HEADER Header; 473 UINT8 MboxIrqId; 474 UINT8 Reserved[3]; 475 UINT64 CmdRespRegAddr; 476 UINT64 CmdBufLoRegAddr; 477 UINT64 CmdBufHiRegAddr; 478 479 } ACPI_ASPT_SEV_MBOX_REGS; 480 481 482 /* 2: ASPT ACPI Mailbox Registers */ 483 484 typedef struct acpi_aspt_acpi_mbox_regs 485 { 486 ACPI_ASPT_HEADER Header; 487 UINT32 Reserved1; 488 UINT64 CmdRespRegAddr; 489 UINT64 Reserved2[2]; 490 491 } ACPI_ASPT_ACPI_MBOX_REGS; 492 493 494 /******************************************************************************* 495 * 496 * BERT - Boot Error Record Table (ACPI 4.0) 497 * Version 1 498 * 499 ******************************************************************************/ 500 501 typedef struct acpi_table_bert 502 { 503 ACPI_TABLE_HEADER Header; /* Common ACPI table header */ 504 UINT32 RegionLength; /* Length of the boot error region */ 505 UINT64 Address; /* Physical address of the error region */ 506 507 } ACPI_TABLE_BERT; 508 509 510 /* Boot Error Region (not a subtable, pointed to by Address field above) */ 511 512 typedef struct acpi_bert_region 513 { 514 UINT32 BlockStatus; /* Type of error information */ 515 UINT32 RawDataOffset; /* Offset to raw error data */ 516 UINT32 RawDataLength; /* Length of raw error data */ 517 UINT32 DataLength; /* Length of generic error data */ 518 UINT32 ErrorSeverity; /* Severity code */ 519 520 } ACPI_BERT_REGION; 521 522 /* Values for BlockStatus flags above */ 523 524 #define ACPI_BERT_UNCORRECTABLE (1) 525 #define ACPI_BERT_CORRECTABLE (1<<1) 526 #define ACPI_BERT_MULTIPLE_UNCORRECTABLE (1<<2) 527 #define ACPI_BERT_MULTIPLE_CORRECTABLE (1<<3) 528 #define ACPI_BERT_ERROR_ENTRY_COUNT (0xFF<<4) /* 8 bits, error count */ 529 530 /* Values for ErrorSeverity above */ 531 532 enum AcpiBertErrorSeverity 533 { 534 ACPI_BERT_ERROR_CORRECTABLE = 0, 535 ACPI_BERT_ERROR_FATAL = 1, 536 ACPI_BERT_ERROR_CORRECTED = 2, 537 ACPI_BERT_ERROR_NONE = 3, 538 ACPI_BERT_ERROR_RESERVED = 4 /* 4 and greater are reserved */ 539 }; 540 541 /* 542 * Note: The generic error data that follows the ErrorSeverity field above 543 * uses the ACPI_HEST_GENERIC_DATA defined under the HEST table below 544 */ 545 546 547 /******************************************************************************* 548 * 549 * BGRT - Boot Graphics Resource Table (ACPI 5.0) 550 * Version 1 551 * 552 ******************************************************************************/ 553 554 typedef struct acpi_table_bgrt 555 { 556 ACPI_TABLE_HEADER Header; /* Common ACPI table header */ 557 UINT16 Version; 558 UINT8 Status; 559 UINT8 ImageType; 560 UINT64 ImageAddress; 561 UINT32 ImageOffsetX; 562 UINT32 ImageOffsetY; 563 564 } ACPI_TABLE_BGRT; 565 566 /* Flags for Status field above */ 567 568 #define ACPI_BGRT_DISPLAYED (1) 569 #define ACPI_BGRT_ORIENTATION_OFFSET (3 << 1) 570 571 572 /******************************************************************************* 573 * 574 * BOOT - Simple Boot Flag Table 575 * Version 1 576 * 577 * Conforms to the "Simple Boot Flag Specification", Version 2.1 578 * 579 ******************************************************************************/ 580 581 typedef struct acpi_table_boot 582 { 583 ACPI_TABLE_HEADER Header; /* Common ACPI table header */ 584 UINT8 CmosIndex; /* Index in CMOS RAM for the boot register */ 585 UINT8 Reserved[3]; 586 587 } ACPI_TABLE_BOOT; 588 589 590 /******************************************************************************* 591 * 592 * CDAT - Coherent Device Attribute Table 593 * Version 1 594 * 595 * Conforms to the "Coherent Device Attribute Table (CDAT) Specification 596 " (Revision 1.01, October 2020.) 597 * 598 ******************************************************************************/ 599 600 typedef struct acpi_table_cdat 601 { 602 UINT32 Length; /* Length of table in bytes, including this header */ 603 UINT8 Revision; /* ACPI Specification minor version number */ 604 UINT8 Checksum; /* To make sum of entire table == 0 */ 605 UINT8 Reserved[6]; 606 UINT32 Sequence; /* Used to detect runtime CDAT table changes */ 607 608 } ACPI_TABLE_CDAT; 609 610 611 /* CDAT common subtable header */ 612 613 typedef struct acpi_cdat_header 614 { 615 UINT8 Type; 616 UINT8 Reserved; 617 UINT16 Length; 618 619 } ACPI_CDAT_HEADER; 620 621 /* Values for Type field above */ 622 623 enum AcpiCdatType 624 { 625 ACPI_CDAT_TYPE_DSMAS = 0, 626 ACPI_CDAT_TYPE_DSLBIS = 1, 627 ACPI_CDAT_TYPE_DSMSCIS = 2, 628 ACPI_CDAT_TYPE_DSIS = 3, 629 ACPI_CDAT_TYPE_DSEMTS = 4, 630 ACPI_CDAT_TYPE_SSLBIS = 5, 631 ACPI_CDAT_TYPE_RESERVED = 6 /* 6 through 0xFF are reserved */ 632 }; 633 634 635 /* Subtable 0: Device Scoped Memory Affinity Structure (DSMAS) */ 636 637 typedef struct acpi_cdat_dsmas 638 { 639 UINT8 DsmadHandle; 640 UINT8 Flags; 641 UINT16 Reserved; 642 UINT64 DpaBaseAddress; 643 UINT64 DpaLength; 644 645 } ACPI_CDAT_DSMAS; 646 647 /* Flags for subtable above */ 648 649 #define ACPI_CDAT_DSMAS_NON_VOLATILE (1 << 2) 650 #define ACPI_CDAT_DSMAS_SHAREABLE (1 << 3) 651 #define ACPI_CDAT_DSMAS_READ_ONLY (1 << 6) 652 653 654 /* Subtable 1: Device scoped Latency and Bandwidth Information Structure (DSLBIS) */ 655 656 typedef struct acpi_cdat_dslbis 657 { 658 UINT8 Handle; 659 UINT8 Flags; /* If Handle matches a DSMAS handle, the definition of this field matches 660 * Flags field in HMAT System Locality Latency */ 661 UINT8 DataType; 662 UINT8 Reserved; 663 UINT64 EntryBaseUnit; 664 UINT16 Entry[3]; 665 UINT16 Reserved2; 666 667 } ACPI_CDAT_DSLBIS; 668 669 670 /* Subtable 2: Device Scoped Memory Side Cache Information Structure (DSMSCIS) */ 671 672 typedef struct acpi_cdat_dsmscis 673 { 674 UINT8 DsmasHandle; 675 UINT8 Reserved[3]; 676 UINT64 SideCacheSize; 677 UINT32 CacheAttributes; 678 679 } ACPI_CDAT_DSMSCIS; 680 681 682 /* Subtable 3: Device Scoped Initiator Structure (DSIS) */ 683 684 typedef struct acpi_cdat_dsis 685 { 686 UINT8 Flags; 687 UINT8 Handle; 688 UINT16 Reserved; 689 690 } ACPI_CDAT_DSIS; 691 692 /* Flags for above subtable */ 693 694 #define ACPI_CDAT_DSIS_MEM_ATTACHED (1 << 0) 695 696 697 /* Subtable 4: Device Scoped EFI Memory Type Structure (DSEMTS) */ 698 699 typedef struct acpi_cdat_dsemts 700 { 701 UINT8 DsmasHandle; 702 UINT8 MemoryType; 703 UINT16 Reserved; 704 UINT64 DpaOffset; 705 UINT64 RangeLength; 706 707 } ACPI_CDAT_DSEMTS; 708 709 710 /* Subtable 5: Switch Scoped Latency and Bandwidth Information Structure (SSLBIS) */ 711 712 typedef struct acpi_cdat_sslbis 713 { 714 UINT8 DataType; 715 UINT8 Reserved[3]; 716 UINT64 EntryBaseUnit; 717 718 } ACPI_CDAT_SSLBIS; 719 720 721 /* Sub-subtable for above, SslbeEntries field */ 722 723 typedef struct acpi_cdat_sslbe 724 { 725 UINT16 PortxId; 726 UINT16 PortyId; 727 UINT16 LatencyOrBandwidth; 728 UINT16 Reserved; 729 730 } ACPI_CDAT_SSLBE; 731 732 #define ACPI_CDAT_SSLBIS_US_PORT 0x0100 733 #define ACPI_CDAT_SSLBIS_ANY_PORT 0xffff 734 735 /******************************************************************************* 736 * 737 * CEDT - CXL Early Discovery Table 738 * Version 1 739 * 740 * Conforms to the "CXL Early Discovery Table" (CXL 2.0, October 2020) 741 * 742 ******************************************************************************/ 743 744 typedef struct acpi_table_cedt 745 { 746 ACPI_TABLE_HEADER Header; /* Common ACPI table header */ 747 748 } ACPI_TABLE_CEDT; 749 750 /* CEDT subtable header (Performance Record Structure) */ 751 752 typedef struct acpi_cedt_header 753 { 754 UINT8 Type; 755 UINT8 Reserved; 756 UINT16 Length; 757 758 } ACPI_CEDT_HEADER; 759 760 /* Values for Type field above */ 761 762 enum AcpiCedtType 763 { 764 ACPI_CEDT_TYPE_CHBS = 0, 765 ACPI_CEDT_TYPE_CFMWS = 1, 766 ACPI_CEDT_TYPE_CXIMS = 2, 767 ACPI_CEDT_TYPE_RDPAS = 3, 768 ACPI_CEDT_TYPE_RESERVED = 4, 769 }; 770 771 /* Values for version field above */ 772 773 #define ACPI_CEDT_CHBS_VERSION_CXL11 (0) 774 #define ACPI_CEDT_CHBS_VERSION_CXL20 (1) 775 776 /* Values for length field above */ 777 778 #define ACPI_CEDT_CHBS_LENGTH_CXL11 (0x2000) 779 #define ACPI_CEDT_CHBS_LENGTH_CXL20 (0x10000) 780 781 /* 782 * CEDT subtables 783 */ 784 785 /* 0: CXL Host Bridge Structure */ 786 787 typedef struct acpi_cedt_chbs 788 { 789 ACPI_CEDT_HEADER Header; 790 UINT32 Uid; 791 UINT32 CxlVersion; 792 UINT32 Reserved; 793 UINT64 Base; 794 UINT64 Length; 795 796 } ACPI_CEDT_CHBS; 797 798 799 /* 1: CXL Fixed Memory Window Structure */ 800 801 typedef struct acpi_cedt_cfmws 802 { 803 ACPI_CEDT_HEADER Header; 804 UINT32 Reserved1; 805 UINT64 BaseHpa; 806 UINT64 WindowSize; 807 UINT8 InterleaveWays; 808 UINT8 InterleaveArithmetic; 809 UINT16 Reserved2; 810 UINT32 Granularity; 811 UINT16 Restrictions; 812 UINT16 QtgId; 813 UINT32 InterleaveTargets[]; 814 815 } ACPI_CEDT_CFMWS; 816 817 typedef struct acpi_cedt_cfmws_target_element 818 { 819 UINT32 InterleaveTarget; 820 821 } ACPI_CEDT_CFMWS_TARGET_ELEMENT; 822 823 /* Values for Interleave Arithmetic field above */ 824 825 #define ACPI_CEDT_CFMWS_ARITHMETIC_MODULO (0) 826 #define ACPI_CEDT_CFMWS_ARITHMETIC_XOR (1) 827 828 /* Values for Restrictions field above */ 829 830 #define ACPI_CEDT_CFMWS_RESTRICT_DEVMEM (1) 831 #define ACPI_CEDT_CFMWS_RESTRICT_HOSTONLYMEM (1<<1) 832 #define ACPI_CEDT_CFMWS_RESTRICT_VOLATILE (1<<2) 833 #define ACPI_CEDT_CFMWS_RESTRICT_PMEM (1<<3) 834 #define ACPI_CEDT_CFMWS_RESTRICT_FIXED (1<<4) 835 #define ACPI_CEDT_CFMWS_RESTRICT_BI (1<<5) 836 837 /* 2: CXL XOR Interleave Math Structure */ 838 839 typedef struct acpi_cedt_cxims { 840 ACPI_CEDT_HEADER Header; 841 UINT16 Reserved1; 842 UINT8 Hbig; 843 UINT8 NrXormaps; 844 UINT64 XormapList[]; 845 } ACPI_CEDT_CXIMS; 846 847 typedef struct acpi_cedt_cxims_target_element 848 { 849 UINT64 Xormap; 850 851 } ACPI_CEDT_CXIMS_TARGET_ELEMENT; 852 853 854 /* 3: CXL RCEC Downstream Port Association Structure */ 855 856 struct acpi_cedt_rdpas { 857 ACPI_CEDT_HEADER Header; 858 UINT16 Segment; 859 UINT16 Bdf; 860 UINT8 Protocol; 861 UINT64 Address; 862 }; 863 864 /* Masks for bdf field above */ 865 #define ACPI_CEDT_RDPAS_BUS_MASK 0xff00 866 #define ACPI_CEDT_RDPAS_DEVICE_MASK 0x00f8 867 #define ACPI_CEDT_RDPAS_FUNCTION_MASK 0x0007 868 869 #define ACPI_CEDT_RDPAS_PROTOCOL_IO (0) 870 #define ACPI_CEDT_RDPAS_PROTOCOL_CACHEMEM (1) 871 872 /******************************************************************************* 873 * 874 * CPEP - Corrected Platform Error Polling table (ACPI 4.0) 875 * Version 1 876 * 877 ******************************************************************************/ 878 879 typedef struct acpi_table_cpep 880 { 881 ACPI_TABLE_HEADER Header; /* Common ACPI table header */ 882 UINT64 Reserved; 883 884 } ACPI_TABLE_CPEP; 885 886 887 /* Subtable */ 888 889 typedef struct acpi_cpep_polling 890 { 891 ACPI_SUBTABLE_HEADER Header; 892 UINT8 Id; /* Processor ID */ 893 UINT8 Eid; /* Processor EID */ 894 UINT32 Interval; /* Polling interval (msec) */ 895 896 } ACPI_CPEP_POLLING; 897 898 899 /******************************************************************************* 900 * 901 * CSRT - Core System Resource Table 902 * Version 0 903 * 904 * Conforms to the "Core System Resource Table (CSRT)", November 14, 2011 905 * 906 ******************************************************************************/ 907 908 typedef struct acpi_table_csrt 909 { 910 ACPI_TABLE_HEADER Header; /* Common ACPI table header */ 911 912 } ACPI_TABLE_CSRT; 913 914 915 /* Resource Group subtable */ 916 917 typedef struct acpi_csrt_group 918 { 919 UINT32 Length; 920 UINT32 VendorId; 921 UINT32 SubvendorId; 922 UINT16 DeviceId; 923 UINT16 SubdeviceId; 924 UINT16 Revision; 925 UINT16 Reserved; 926 UINT32 SharedInfoLength; 927 928 /* Shared data immediately follows (Length = SharedInfoLength) */ 929 930 } ACPI_CSRT_GROUP; 931 932 /* Shared Info subtable */ 933 934 typedef struct acpi_csrt_shared_info 935 { 936 UINT16 MajorVersion; 937 UINT16 MinorVersion; 938 UINT32 MmioBaseLow; 939 UINT32 MmioBaseHigh; 940 UINT32 GsiInterrupt; 941 UINT8 InterruptPolarity; 942 UINT8 InterruptMode; 943 UINT8 NumChannels; 944 UINT8 DmaAddressWidth; 945 UINT16 BaseRequestLine; 946 UINT16 NumHandshakeSignals; 947 UINT32 MaxBlockSize; 948 949 /* Resource descriptors immediately follow (Length = Group Length - SharedInfoLength) */ 950 951 } ACPI_CSRT_SHARED_INFO; 952 953 /* Resource Descriptor subtable */ 954 955 typedef struct acpi_csrt_descriptor 956 { 957 UINT32 Length; 958 UINT16 Type; 959 UINT16 Subtype; 960 UINT32 Uid; 961 962 /* Resource-specific information immediately follows */ 963 964 } ACPI_CSRT_DESCRIPTOR; 965 966 967 /* Resource Types */ 968 969 #define ACPI_CSRT_TYPE_INTERRUPT 0x0001 970 #define ACPI_CSRT_TYPE_TIMER 0x0002 971 #define ACPI_CSRT_TYPE_DMA 0x0003 972 973 /* Resource Subtypes */ 974 975 #define ACPI_CSRT_XRUPT_LINE 0x0000 976 #define ACPI_CSRT_XRUPT_CONTROLLER 0x0001 977 #define ACPI_CSRT_TIMER 0x0000 978 #define ACPI_CSRT_DMA_CHANNEL 0x0000 979 #define ACPI_CSRT_DMA_CONTROLLER 0x0001 980 981 982 /******************************************************************************* 983 * 984 * DBG2 - Debug Port Table 2 985 * Version 0 (Both main table and subtables) 986 * 987 * Conforms to "Microsoft Debug Port Table 2 (DBG2)", September 21, 2020 988 * 989 ******************************************************************************/ 990 991 typedef struct acpi_table_dbg2 992 { 993 ACPI_TABLE_HEADER Header; /* Common ACPI table header */ 994 UINT32 InfoOffset; 995 UINT32 InfoCount; 996 997 } ACPI_TABLE_DBG2; 998 999 1000 typedef struct acpi_dbg2_header 1001 { 1002 UINT32 InfoOffset; 1003 UINT32 InfoCount; 1004 1005 } ACPI_DBG2_HEADER; 1006 1007 1008 /* Debug Device Information Subtable */ 1009 1010 typedef struct acpi_dbg2_device 1011 { 1012 UINT8 Revision; 1013 UINT16 Length; 1014 UINT8 RegisterCount; /* Number of BaseAddress registers */ 1015 UINT16 NamepathLength; 1016 UINT16 NamepathOffset; 1017 UINT16 OemDataLength; 1018 UINT16 OemDataOffset; 1019 UINT16 PortType; 1020 UINT16 PortSubtype; 1021 UINT16 Reserved; 1022 UINT16 BaseAddressOffset; 1023 UINT16 AddressSizeOffset; 1024 /* 1025 * Data that follows: 1026 * BaseAddress (required) - Each in 12-byte Generic Address Structure format. 1027 * AddressSize (required) - Array of UINT32 sizes corresponding to each BaseAddress register. 1028 * Namepath (required) - Null terminated string. Single dot if not supported. 1029 * OemData (optional) - Length is OemDataLength. 1030 */ 1031 } ACPI_DBG2_DEVICE; 1032 1033 /* Types for PortType field above */ 1034 1035 #define ACPI_DBG2_SERIAL_PORT 0x8000 1036 #define ACPI_DBG2_1394_PORT 0x8001 1037 #define ACPI_DBG2_USB_PORT 0x8002 1038 #define ACPI_DBG2_NET_PORT 0x8003 1039 1040 /* Subtypes for PortSubtype field above */ 1041 1042 #define ACPI_DBG2_16550_COMPATIBLE 0x0000 1043 #define ACPI_DBG2_16550_SUBSET 0x0001 1044 #define ACPI_DBG2_MAX311XE_SPI 0x0002 1045 #define ACPI_DBG2_ARM_PL011 0x0003 1046 #define ACPI_DBG2_MSM8X60 0x0004 1047 #define ACPI_DBG2_16550_NVIDIA 0x0005 1048 #define ACPI_DBG2_TI_OMAP 0x0006 1049 #define ACPI_DBG2_APM88XXXX 0x0008 1050 #define ACPI_DBG2_MSM8974 0x0009 1051 #define ACPI_DBG2_SAM5250 0x000A 1052 #define ACPI_DBG2_INTEL_USIF 0x000B 1053 #define ACPI_DBG2_IMX6 0x000C 1054 #define ACPI_DBG2_ARM_SBSA_32BIT 0x000D 1055 #define ACPI_DBG2_ARM_SBSA_GENERIC 0x000E 1056 #define ACPI_DBG2_ARM_DCC 0x000F 1057 #define ACPI_DBG2_BCM2835 0x0010 1058 #define ACPI_DBG2_SDM845_1_8432MHZ 0x0011 1059 #define ACPI_DBG2_16550_WITH_GAS 0x0012 1060 #define ACPI_DBG2_SDM845_7_372MHZ 0x0013 1061 #define ACPI_DBG2_INTEL_LPSS 0x0014 1062 #define ACPI_DBG2_RISCV_SBI_CON 0x0015 1063 1064 #define ACPI_DBG2_1394_STANDARD 0x0000 1065 1066 #define ACPI_DBG2_USB_XHCI 0x0000 1067 #define ACPI_DBG2_USB_EHCI 0x0001 1068 1069 1070 /******************************************************************************* 1071 * 1072 * DBGP - Debug Port table 1073 * Version 1 1074 * 1075 * Conforms to the "Debug Port Specification", Version 1.00, 2/9/2000 1076 * 1077 ******************************************************************************/ 1078 1079 typedef struct acpi_table_dbgp 1080 { 1081 ACPI_TABLE_HEADER Header; /* Common ACPI table header */ 1082 UINT8 Type; /* 0=full 16550, 1=subset of 16550 */ 1083 UINT8 Reserved[3]; 1084 ACPI_GENERIC_ADDRESS DebugPort; 1085 1086 } ACPI_TABLE_DBGP; 1087 1088 1089 /******************************************************************************* 1090 * 1091 * DMAR - DMA Remapping table 1092 * Version 1 1093 * 1094 * Conforms to "Intel Virtualization Technology for Directed I/O", 1095 * Version 2.3, October 2014 1096 * 1097 ******************************************************************************/ 1098 1099 typedef struct acpi_table_dmar 1100 { 1101 ACPI_TABLE_HEADER Header; /* Common ACPI table header */ 1102 UINT8 Width; /* Host Address Width */ 1103 UINT8 Flags; 1104 UINT8 Reserved[10]; 1105 1106 } ACPI_TABLE_DMAR; 1107 1108 /* Masks for Flags field above */ 1109 1110 #define ACPI_DMAR_INTR_REMAP (1) 1111 #define ACPI_DMAR_X2APIC_OPT_OUT (1<<1) 1112 #define ACPI_DMAR_X2APIC_MODE (1<<2) 1113 1114 1115 /* DMAR subtable header */ 1116 1117 typedef struct acpi_dmar_header 1118 { 1119 UINT16 Type; 1120 UINT16 Length; 1121 1122 } ACPI_DMAR_HEADER; 1123 1124 /* Values for subtable type in ACPI_DMAR_HEADER */ 1125 1126 enum AcpiDmarType 1127 { 1128 ACPI_DMAR_TYPE_HARDWARE_UNIT = 0, 1129 ACPI_DMAR_TYPE_RESERVED_MEMORY = 1, 1130 ACPI_DMAR_TYPE_ROOT_ATS = 2, 1131 ACPI_DMAR_TYPE_HARDWARE_AFFINITY = 3, 1132 ACPI_DMAR_TYPE_NAMESPACE = 4, 1133 ACPI_DMAR_TYPE_SATC = 5, 1134 ACPI_DMAR_TYPE_SIDP = 6, 1135 ACPI_DMAR_TYPE_RESERVED = 7 /* 7 and greater are reserved */ 1136 }; 1137 1138 1139 /* DMAR Device Scope structure */ 1140 1141 typedef struct acpi_dmar_device_scope 1142 { 1143 UINT8 EntryType; 1144 UINT8 Length; 1145 UINT8 Flags; 1146 UINT8 Reserved; 1147 UINT8 EnumerationId; 1148 UINT8 Bus; 1149 1150 } ACPI_DMAR_DEVICE_SCOPE; 1151 1152 /* Values for EntryType in ACPI_DMAR_DEVICE_SCOPE - device types */ 1153 1154 enum AcpiDmarScopeType 1155 { 1156 ACPI_DMAR_SCOPE_TYPE_NOT_USED = 0, 1157 ACPI_DMAR_SCOPE_TYPE_ENDPOINT = 1, 1158 ACPI_DMAR_SCOPE_TYPE_BRIDGE = 2, 1159 ACPI_DMAR_SCOPE_TYPE_IOAPIC = 3, 1160 ACPI_DMAR_SCOPE_TYPE_HPET = 4, 1161 ACPI_DMAR_SCOPE_TYPE_NAMESPACE = 5, 1162 ACPI_DMAR_SCOPE_TYPE_RESERVED = 6 /* 6 and greater are reserved */ 1163 }; 1164 1165 typedef struct acpi_dmar_pci_path 1166 { 1167 UINT8 Device; 1168 UINT8 Function; 1169 1170 } ACPI_DMAR_PCI_PATH; 1171 1172 1173 /* 1174 * DMAR Subtables, correspond to Type in ACPI_DMAR_HEADER 1175 */ 1176 1177 /* 0: Hardware Unit Definition */ 1178 1179 typedef struct acpi_dmar_hardware_unit 1180 { 1181 ACPI_DMAR_HEADER Header; 1182 UINT8 Flags; 1183 UINT8 Size; 1184 UINT16 Segment; 1185 UINT64 Address; /* Register Base Address */ 1186 1187 } ACPI_DMAR_HARDWARE_UNIT; 1188 1189 /* Masks for Flags field above */ 1190 1191 #define ACPI_DMAR_INCLUDE_ALL (1) 1192 1193 1194 /* 1: Reserved Memory Definition */ 1195 1196 typedef struct acpi_dmar_reserved_memory 1197 { 1198 ACPI_DMAR_HEADER Header; 1199 UINT16 Reserved; 1200 UINT16 Segment; 1201 UINT64 BaseAddress; /* 4K aligned base address */ 1202 UINT64 EndAddress; /* 4K aligned limit address */ 1203 1204 } ACPI_DMAR_RESERVED_MEMORY; 1205 1206 /* Masks for Flags field above */ 1207 1208 #define ACPI_DMAR_ALLOW_ALL (1) 1209 1210 1211 /* 2: Root Port ATS Capability Reporting Structure */ 1212 1213 typedef struct acpi_dmar_atsr 1214 { 1215 ACPI_DMAR_HEADER Header; 1216 UINT8 Flags; 1217 UINT8 Reserved; 1218 UINT16 Segment; 1219 1220 } ACPI_DMAR_ATSR; 1221 1222 /* Masks for Flags field above */ 1223 1224 #define ACPI_DMAR_ALL_PORTS (1) 1225 1226 1227 /* 3: Remapping Hardware Static Affinity Structure */ 1228 1229 typedef struct acpi_dmar_rhsa 1230 { 1231 ACPI_DMAR_HEADER Header; 1232 UINT32 Reserved; 1233 UINT64 BaseAddress; 1234 UINT32 ProximityDomain; 1235 1236 } ACPI_DMAR_RHSA; 1237 1238 1239 /* 4: ACPI Namespace Device Declaration Structure */ 1240 1241 typedef struct acpi_dmar_andd 1242 { 1243 ACPI_DMAR_HEADER Header; 1244 UINT8 Reserved[3]; 1245 UINT8 DeviceNumber; 1246 union { 1247 char __pad; 1248 ACPI_FLEX_ARRAY(char, DeviceName); 1249 }; 1250 1251 } ACPI_DMAR_ANDD; 1252 1253 1254 /* 5: SoC Integrated Address Translation Cache (SATC) */ 1255 1256 typedef struct acpi_dmar_satc 1257 { 1258 ACPI_DMAR_HEADER Header; 1259 UINT8 Flags; 1260 UINT8 Reserved; 1261 UINT16 Segment; 1262 1263 } ACPI_DMAR_SATC; 1264 1265 1266 /* 6: SoC Integrated Device Property Reporting Structure */ 1267 1268 typedef struct acpi_dmar_sidp 1269 { 1270 ACPI_DMAR_HEADER Header; 1271 UINT16 Reserved; 1272 UINT16 Segment; 1273 1274 } ACPI_DMAR_SIDP; 1275 1276 1277 /******************************************************************************* 1278 * 1279 * DRTM - Dynamic Root of Trust for Measurement table 1280 * Conforms to "TCG D-RTM Architecture" June 17 2013, Version 1.0.0 1281 * Table version 1 1282 * 1283 ******************************************************************************/ 1284 1285 typedef struct acpi_table_drtm 1286 { 1287 ACPI_TABLE_HEADER Header; /* Common ACPI table header */ 1288 UINT64 EntryBaseAddress; 1289 UINT64 EntryLength; 1290 UINT32 EntryAddress32; 1291 UINT64 EntryAddress64; 1292 UINT64 ExitAddress; 1293 UINT64 LogAreaAddress; 1294 UINT32 LogAreaLength; 1295 UINT64 ArchDependentAddress; 1296 UINT32 Flags; 1297 1298 } ACPI_TABLE_DRTM; 1299 1300 /* Flag Definitions for above */ 1301 1302 #define ACPI_DRTM_ACCESS_ALLOWED (1) 1303 #define ACPI_DRTM_ENABLE_GAP_CODE (1<<1) 1304 #define ACPI_DRTM_INCOMPLETE_MEASUREMENTS (1<<2) 1305 #define ACPI_DRTM_AUTHORITY_ORDER (1<<3) 1306 1307 1308 /* 1) Validated Tables List (64-bit addresses) */ 1309 1310 typedef struct acpi_drtm_vtable_list 1311 { 1312 UINT32 ValidatedTableCount; 1313 UINT64 ValidatedTables[]; 1314 1315 } ACPI_DRTM_VTABLE_LIST; 1316 1317 /* 2) Resources List (of Resource Descriptors) */ 1318 1319 /* Resource Descriptor */ 1320 1321 typedef struct acpi_drtm_resource 1322 { 1323 UINT8 Size[7]; 1324 UINT8 Type; 1325 UINT64 Address; 1326 1327 } ACPI_DRTM_RESOURCE; 1328 1329 typedef struct acpi_drtm_resource_list 1330 { 1331 UINT32 ResourceCount; 1332 ACPI_DRTM_RESOURCE Resources[]; 1333 1334 } ACPI_DRTM_RESOURCE_LIST; 1335 1336 /* 3) Platform-specific Identifiers List */ 1337 1338 typedef struct acpi_drtm_dps_id 1339 { 1340 UINT32 DpsIdLength; 1341 UINT8 DpsId[16]; 1342 1343 } ACPI_DRTM_DPS_ID; 1344 1345 1346 /******************************************************************************* 1347 * 1348 * DTPR - DMA TXT Protection Ranges Table 1349 * Version 1 1350 * 1351 * Conforms to "Intel® Trusted Execution Technology (Intel® TXT) DMA Protection 1352 * Ranges", 1353 * Revision 0.73, August 2021 1354 * 1355 ******************************************************************************/ 1356 1357 typedef struct acpi_table_dtpr { 1358 ACPI_TABLE_HEADER header; 1359 UINT32 Flags; /* 36 */ 1360 UINT32 InsCnt; 1361 1362 } ACPI_TABLE_DTPR; 1363 1364 typedef struct acpi_tpr_array { 1365 UINT64 Base; 1366 1367 } ACPI_TPR_ARRAY; 1368 1369 typedef struct acpi_tpr_instance { 1370 UINT32 Flags; 1371 UINT32 TprCnt; 1372 1373 } ACPI_TPR_INSTANCE; 1374 1375 typedef struct acpi_tpr_aux_sr { 1376 UINT32 SrlCnt; 1377 1378 } ACPI_TPR_AUX_SR; 1379 1380 1381 /* 1382 * TPRn_BASE (ACPI_TPRN_BASE_REG) 1383 * 1384 * Specifies the start address of TPRn region. TPR region address and size must 1385 * be with 1MB resolution. These bits are compared with the result of the 1386 * TPRn_LIMIT[63:20], which is applied to the incoming address, to 1387 * determine if an access fall within the TPRn defined region. 1388 * 1389 * Minimal TPRn_Base resolution is 1MB. Applied to the incoming address, to 1390 * determine if an access fall within the TPRn defined region. Width is 1391 * determined by a bus width which can be obtained via CPUID 1392 * function 0x80000008. 1393 */ 1394 1395 typedef UINT64 ACPI_TPRN_BASE_REG; 1396 1397 1398 /* TPRn_BASE Register Bit Masks */ 1399 1400 /* Bit 3 - RW: access: 1 == RO, 0 == RW register (for TPR must be RW) */ 1401 #define ACPI_TPRN_BASE_RW_SHIFT 3 1402 1403 1404 #define ACPI_TPRN_BASE_RW_MASK ((UINT64) 1 << ACPI_TPRN_BASE_RW_SHIFT) 1405 1406 1407 /* 1408 * Bit 4 - Enable: 0 – TPRn address range enabled; 1409 * 1 – TPRn address range disabled. 1410 */ 1411 #define ACPI_TPRN_BASE_ENABLE_SHIFT 4 1412 1413 1414 #define ACPI_TPRN_BASE_ENABLE_MASK ((UINT64) 1 << ACPI_TPRN_BASE_ENABLE_SHIFT) 1415 1416 1417 /* Bits 63:20 - TprBaseRw */ 1418 #define ACPI_TPRN_BASE_ADDR_SHIFT 20 1419 1420 1421 #define ACPI_TPRN_BASE_ADDR_MASK ((UINT64) 0xFFFFFFFFFFF << \ 1422 ACPI_TPRN_BASE_ADDR_SHIFT) 1423 1424 1425 /* TPRn_BASE Register Bit Handlers*/ 1426 1427 /* 1428 * GET_TPRN_BASE_RW: 1429 * 1430 * Read RW bit from TPRn Base Register - bit 3. 1431 * 1432 * Input: 1433 * - reg (represents TPRn Base Register (ACPI_TPRN_BASE_REG)) 1434 * 1435 * Output: 1436 * 1437 * Returns RW bit value (UINT64). 1438 */ 1439 #define GET_TPRN_BASE_RW(reg) (((UINT64) reg & ACPI_TPRN_BASE_RW_MASK) >> \ 1440 ACPI_TPRN_BASE_RW_SHIFT) 1441 1442 1443 /* 1444 * GET_TPRN_BASE_ENABLE: 1445 * 1446 * Read Enable bit from TPRn Base Register - bit 4. 1447 * 1448 * Input: 1449 * - reg (represents TPRn Base Register (ACPI_TPRN_BASE_REG)) 1450 * 1451 * Output: 1452 * 1453 * Returns Enable bit value (UINT64). 1454 */ 1455 #define GET_TPRN_BASE_ENABLE(reg) (((UINT64) reg & ACPI_TPRN_BASE_ENABLE_MASK) \ 1456 >> ACPI_TPRN_BASE_ENABLE_SHIFT) 1457 1458 1459 /* 1460 * GET_TPRN_BASE_ADDR: 1461 * 1462 * Read TPRn Base Register address from bits 63:20. 1463 * 1464 * Input: 1465 * - reg (represents TPRn Base Register (ACPI_TPRN_BASE_REG)) 1466 * 1467 * Output: 1468 * 1469 * Returns TPRn Base Register address (UINT64). 1470 */ 1471 #define GET_TPRN_BASE_ADDR(reg) (((UINT64) reg & ACPI_TPRN_BASE_ADDR_MASK) \ 1472 >> ACPI_TPRN_BASE_ADDR_SHIFT) 1473 1474 1475 /* 1476 * SET_TPRN_BASE_RW: 1477 * 1478 * Set RW bit in TPRn Base Register - bit 3. 1479 * 1480 * Input: 1481 * - reg (represents TPRn Base Register (ACPI_TPRN_BASE_REG)) 1482 * - val (represents RW value to be set (UINT64)) 1483 */ 1484 #define SET_TPRN_BASE_RW(reg, val) ACPI_REGISTER_INSERT_VALUE(reg, \ 1485 ACPI_TPRN_BASE_RW_SHIFT, \ 1486 ACPI_TPRN_BASE_RW_MASK, val); 1487 1488 1489 /* 1490 * SET_TPRN_BASE_ENABLE: 1491 * 1492 * Set Enable bit in TPRn Base Register - bit 4. 1493 * 1494 * Input: 1495 * - reg (represents TPRn Base Register (ACPI_TPRN_BASE_REG)) 1496 * - val (represents Enable value to be set (UINT64)) 1497 */ 1498 #define SET_TPRN_BASE_ENABLE(reg, val) ACPI_REGISTER_INSERT_VALUE(reg, \ 1499 ACPI_TPRN_BASE_ENABLE_SHIFT, \ 1500 ACPI_TPRN_BASE_ENABLE_MASK, val); 1501 1502 1503 /* 1504 * SET_TPRN_BASE_ADDR: 1505 * 1506 * Set TPRn Base Register address - bits 63:20 1507 * 1508 * Input 1509 * - reg (represents TPRn Base Register (ACPI_TPRN_BASE_REG)) 1510 * - val (represents address value to be set (UINT64)) 1511 */ 1512 #define SET_TPRN_BASE_ADDR(reg, val) ACPI_REGISTER_INSERT_VALUE(reg, \ 1513 ACPI_TPRN_BASE_ADDR_SHIFT, \ 1514 ACPI_TPRN_BASE_ADDR_MASK, val); 1515 1516 1517 /* 1518 * TPRn_LIMIT 1519 * 1520 * This register defines an isolated region of memory that can be enabled 1521 * to prohibit certain system agents from accessing memory. When an agent 1522 * sends a request upstream, whether snooped or not, a TPR prevents that 1523 * transaction from changing the state of memory. 1524 * 1525 * Minimal TPRn_Limit resolution is 1MB. Width is determined by a bus width. 1526 */ 1527 1528 typedef UINT64 ACPI_TPRN_LIMIT_REG; 1529 1530 1531 /* TPRn_LIMIT Register Bit Masks */ 1532 1533 1534 /* Bit 3 - RW: access: 1 == RO, 0 == RW register (for TPR must be RW) */ 1535 #define ACPI_TPRN_LIMIT_RW_SHIFT 3 1536 1537 1538 #define ACPI_TPRN_LIMIT_RW_MASK ((UINT64) 1 << ACPI_TPRN_LIMIT_RW_SHIFT) 1539 1540 1541 /* Bits 63:20 - TprLimitRw */ 1542 #define ACPI_TPRN_LIMIT_ADDR_SHIFT 20 1543 1544 1545 #define ACPI_TPRN_LIMIT_ADDR_MASK ((UINT64) 0xFFFFFFFFFFF << \ 1546 ACPI_TPRN_LIMIT_ADDR_SHIFT) 1547 1548 1549 /* TPRn_LIMIT Register Bit Handlers*/ 1550 1551 /* 1552 * GET_TPRN_LIMIT_RW: 1553 * 1554 * Read RW bit from TPRn Limit Register - bit 3. 1555 * 1556 * Input: 1557 * - reg (represents TPRn Limit Register (ACPI_TPRN_LIMIT_REG)) 1558 * 1559 * Output: 1560 * 1561 * Returns RW bit value (UINT64). 1562 */ 1563 #define GET_TPRN_LIMIT_RW(reg) (((UINT64) reg & ACPI_TPRN_LIMIT_RW_MASK) \ 1564 >> ACPI_TPRN_LIMIT_RW_SHIFT) 1565 1566 1567 /* 1568 * GET_TPRN_LIMIT_ADDR: 1569 * 1570 * Read TPRn Limit Register address from bits 63:20. 1571 * 1572 * Input: 1573 * - reg (represents TPRn Limit Register (ACPI_TPRN_LIMIT_REG)) 1574 * 1575 * Output: 1576 * 1577 * Returns TPRn Limit Register address (UINT64). 1578 */ 1579 #define GET_TPRN_LIMIT_ADDR(reg) (((UINT64) reg & ACPI_TPRN_LIMIT_ADDR_MASK) \ 1580 >> ACPI_TPRN_LIMIT_ADDR_SHIFT) 1581 1582 1583 /* 1584 * SET_TPRN_LIMIT_RW: 1585 * 1586 * Set RW bit in TPRn Limit Register - bit 3. 1587 * 1588 * Input: 1589 * - reg (represents TPRn Limit Register (ACPI_TPRN_LIMIT_REG)) 1590 * - val (represents RW value to be set (UINT64)) 1591 */ 1592 #define SET_TPRN_LIMIT_RW(reg, val) ACPI_REGISTER_INSERT_VALUE(reg, \ 1593 ACPI_TPRN_LIMIT_RW_SHIFT, \ 1594 ACPI_TPRN_LIMIT_RW_MASK, val); 1595 1596 1597 /* 1598 * SET_TPRN_LIMIT_ADDR: 1599 * 1600 * Set TPRn Limit Register address - bits 63:20. 1601 * 1602 * Input: 1603 * - reg (represents TPRn Limit Register (ACPI_TPRN_LIMIT_REG)) 1604 * - val (represents address value to be set (UINT64)) 1605 */ 1606 #define SET_TPRN_LIMIT_ADDR(reg, val) ACPI_REGISTER_INSERT_VALUE(reg, \ 1607 ACPI_TPRN_LIMIT_ADDR_SHIFT, \ 1608 ACPI_TPRN_LIMIT_ADDR_MASK, val); 1609 1610 1611 /* 1612 * SERIALIZE_REQUEST 1613 * 1614 * This register is used to request serialization of non-coherent DMA 1615 * transactions. OS shall issue it before changing of TPR settings 1616 * (base / size). 1617 */ 1618 1619 typedef struct acpi_tpr_serialize_request { 1620 UINT64 SrRegister; 1621 /* 1622 * BIT 1 - Status of serialization request (RO) 1623 * 0 == register idle, 1 == serialization in progress 1624 * BIT 2 - Control field to initiate serialization (RW) 1625 * 0 == normal, 1 == initialize serialization 1626 * (self-clear to allow multiple serialization requests) 1627 */ 1628 } ACPI_TPR_SERIALIZE_REQUEST; 1629 1630 1631 /******************************************************************************* 1632 * 1633 * ECDT - Embedded Controller Boot Resources Table 1634 * Version 1 1635 * 1636 ******************************************************************************/ 1637 1638 typedef struct acpi_table_ecdt 1639 { 1640 ACPI_TABLE_HEADER Header; /* Common ACPI table header */ 1641 ACPI_GENERIC_ADDRESS Control; /* Address of EC command/status register */ 1642 ACPI_GENERIC_ADDRESS Data; /* Address of EC data register */ 1643 UINT32 Uid; /* Unique ID - must be same as the EC _UID method */ 1644 UINT8 Gpe; /* The GPE for the EC */ 1645 UINT8 Id[]; /* Full namepath of the EC in the ACPI namespace */ 1646 1647 } ACPI_TABLE_ECDT; 1648 1649 1650 /******************************************************************************* 1651 * 1652 * EINJ - Error Injection Table (ACPI 4.0) 1653 * Version 1 1654 * 1655 ******************************************************************************/ 1656 1657 typedef struct acpi_table_einj 1658 { 1659 ACPI_TABLE_HEADER Header; /* Common ACPI table header */ 1660 UINT32 HeaderLength; 1661 UINT8 Flags; 1662 UINT8 Reserved[3]; 1663 UINT32 Entries; 1664 1665 } ACPI_TABLE_EINJ; 1666 1667 1668 /* EINJ Injection Instruction Entries (actions) */ 1669 1670 typedef struct acpi_einj_entry 1671 { 1672 ACPI_WHEA_HEADER WheaHeader; /* Common header for WHEA tables */ 1673 1674 } ACPI_EINJ_ENTRY; 1675 1676 /* Masks for Flags field above */ 1677 1678 #define ACPI_EINJ_PRESERVE (1) 1679 1680 /* Values for Action field above */ 1681 1682 enum AcpiEinjActions 1683 { 1684 ACPI_EINJ_BEGIN_OPERATION = 0x0, 1685 ACPI_EINJ_GET_TRIGGER_TABLE = 0x1, 1686 ACPI_EINJ_SET_ERROR_TYPE = 0x2, 1687 ACPI_EINJ_GET_ERROR_TYPE = 0x3, 1688 ACPI_EINJ_END_OPERATION = 0x4, 1689 ACPI_EINJ_EXECUTE_OPERATION = 0x5, 1690 ACPI_EINJ_CHECK_BUSY_STATUS = 0x6, 1691 ACPI_EINJ_GET_COMMAND_STATUS = 0x7, 1692 ACPI_EINJ_SET_ERROR_TYPE_WITH_ADDRESS = 0x8, 1693 ACPI_EINJ_GET_EXECUTE_TIMINGS = 0x9, 1694 ACPI_EINJV2_GET_ERROR_TYPE = 0x11, 1695 ACPI_EINJ_ACTION_RESERVED = 0x12, /* 0x12 and greater are reserved */ 1696 ACPI_EINJ_TRIGGER_ERROR = 0xFF /* Except for this value */ 1697 }; 1698 1699 /* Values for Instruction field above */ 1700 1701 enum AcpiEinjInstructions 1702 { 1703 ACPI_EINJ_READ_REGISTER = 0, 1704 ACPI_EINJ_READ_REGISTER_VALUE = 1, 1705 ACPI_EINJ_WRITE_REGISTER = 2, 1706 ACPI_EINJ_WRITE_REGISTER_VALUE = 3, 1707 ACPI_EINJ_NOOP = 4, 1708 ACPI_EINJ_FLUSH_CACHELINE = 5, 1709 ACPI_EINJ_INSTRUCTION_RESERVED = 6 /* 6 and greater are reserved */ 1710 }; 1711 1712 typedef struct acpi_einj_error_type_with_addr 1713 { 1714 UINT32 ErrorType; 1715 UINT32 VendorStructOffset; 1716 UINT32 Flags; 1717 UINT32 ApicId; 1718 UINT64 Address; 1719 UINT64 Range; 1720 UINT32 PcieId; 1721 1722 } ACPI_EINJ_ERROR_TYPE_WITH_ADDR; 1723 1724 typedef struct acpi_einj_vendor 1725 { 1726 UINT32 Length; 1727 UINT32 PcieId; 1728 UINT16 VendorId; 1729 UINT16 DeviceId; 1730 UINT8 RevisionId; 1731 UINT8 Reserved[3]; 1732 1733 } ACPI_EINJ_VENDOR; 1734 1735 1736 /* EINJ Trigger Error Action Table */ 1737 1738 typedef struct acpi_einj_trigger 1739 { 1740 UINT32 HeaderSize; 1741 UINT32 Revision; 1742 UINT32 TableSize; 1743 UINT32 EntryCount; 1744 1745 } ACPI_EINJ_TRIGGER; 1746 1747 /* Command status return values */ 1748 1749 enum AcpiEinjCommandStatus 1750 { 1751 ACPI_EINJ_SUCCESS = 0, 1752 ACPI_EINJ_FAILURE = 1, 1753 ACPI_EINJ_INVALID_ACCESS = 2, 1754 ACPI_EINJ_STATUS_RESERVED = 3 /* 3 and greater are reserved */ 1755 }; 1756 1757 1758 /* Error types returned from ACPI_EINJ_GET_ERROR_TYPE (bitfield) */ 1759 1760 #define ACPI_EINJ_PROCESSOR_CORRECTABLE (1) 1761 #define ACPI_EINJ_PROCESSOR_UNCORRECTABLE (1<<1) 1762 #define ACPI_EINJ_PROCESSOR_FATAL (1<<2) 1763 #define ACPI_EINJ_MEMORY_CORRECTABLE (1<<3) 1764 #define ACPI_EINJ_MEMORY_UNCORRECTABLE (1<<4) 1765 #define ACPI_EINJ_MEMORY_FATAL (1<<5) 1766 #define ACPI_EINJ_PCIX_CORRECTABLE (1<<6) 1767 #define ACPI_EINJ_PCIX_UNCORRECTABLE (1<<7) 1768 #define ACPI_EINJ_PCIX_FATAL (1<<8) 1769 #define ACPI_EINJ_PLATFORM_CORRECTABLE (1<<9) 1770 #define ACPI_EINJ_PLATFORM_UNCORRECTABLE (1<<10) 1771 #define ACPI_EINJ_PLATFORM_FATAL (1<<11) 1772 #define ACPI_EINJ_CXL_CACHE_CORRECTABLE (1<<12) 1773 #define ACPI_EINJ_CXL_CACHE_UNCORRECTABLE (1<<13) 1774 #define ACPI_EINJ_CXL_CACHE_FATAL (1<<14) 1775 #define ACPI_EINJ_CXL_MEM_CORRECTABLE (1<<15) 1776 #define ACPI_EINJ_CXL_MEM_UNCORRECTABLE (1<<16) 1777 #define ACPI_EINJ_CXL_MEM_FATAL (1<<17) 1778 #define ACPI_EINJ_VENDOR_DEFINED (1<<31) 1779 1780 1781 /******************************************************************************* 1782 * 1783 * ERST - Error Record Serialization Table (ACPI 4.0) 1784 * Version 1 1785 * 1786 ******************************************************************************/ 1787 1788 typedef struct acpi_table_erst 1789 { 1790 ACPI_TABLE_HEADER Header; /* Common ACPI table header */ 1791 UINT32 HeaderLength; 1792 UINT32 Reserved; 1793 UINT32 Entries; 1794 1795 } ACPI_TABLE_ERST; 1796 1797 1798 /* ERST Serialization Entries (actions) */ 1799 1800 typedef struct acpi_erst_entry 1801 { 1802 ACPI_WHEA_HEADER WheaHeader; /* Common header for WHEA tables */ 1803 1804 } ACPI_ERST_ENTRY; 1805 1806 /* Masks for Flags field above */ 1807 1808 #define ACPI_ERST_PRESERVE (1) 1809 1810 /* Values for Action field above */ 1811 1812 enum AcpiErstActions 1813 { 1814 ACPI_ERST_BEGIN_WRITE = 0, 1815 ACPI_ERST_BEGIN_READ = 1, 1816 ACPI_ERST_BEGIN_CLEAR = 2, 1817 ACPI_ERST_END = 3, 1818 ACPI_ERST_SET_RECORD_OFFSET = 4, 1819 ACPI_ERST_EXECUTE_OPERATION = 5, 1820 ACPI_ERST_CHECK_BUSY_STATUS = 6, 1821 ACPI_ERST_GET_COMMAND_STATUS = 7, 1822 ACPI_ERST_GET_RECORD_ID = 8, 1823 ACPI_ERST_SET_RECORD_ID = 9, 1824 ACPI_ERST_GET_RECORD_COUNT = 10, 1825 ACPI_ERST_BEGIN_DUMMY_WRIITE = 11, 1826 ACPI_ERST_NOT_USED = 12, 1827 ACPI_ERST_GET_ERROR_RANGE = 13, 1828 ACPI_ERST_GET_ERROR_LENGTH = 14, 1829 ACPI_ERST_GET_ERROR_ATTRIBUTES = 15, 1830 ACPI_ERST_EXECUTE_TIMINGS = 16, 1831 ACPI_ERST_ACTION_RESERVED = 17 /* 17 and greater are reserved */ 1832 }; 1833 1834 /* Values for Instruction field above */ 1835 1836 enum AcpiErstInstructions 1837 { 1838 ACPI_ERST_READ_REGISTER = 0, 1839 ACPI_ERST_READ_REGISTER_VALUE = 1, 1840 ACPI_ERST_WRITE_REGISTER = 2, 1841 ACPI_ERST_WRITE_REGISTER_VALUE = 3, 1842 ACPI_ERST_NOOP = 4, 1843 ACPI_ERST_LOAD_VAR1 = 5, 1844 ACPI_ERST_LOAD_VAR2 = 6, 1845 ACPI_ERST_STORE_VAR1 = 7, 1846 ACPI_ERST_ADD = 8, 1847 ACPI_ERST_SUBTRACT = 9, 1848 ACPI_ERST_ADD_VALUE = 10, 1849 ACPI_ERST_SUBTRACT_VALUE = 11, 1850 ACPI_ERST_STALL = 12, 1851 ACPI_ERST_STALL_WHILE_TRUE = 13, 1852 ACPI_ERST_SKIP_NEXT_IF_TRUE = 14, 1853 ACPI_ERST_GOTO = 15, 1854 ACPI_ERST_SET_SRC_ADDRESS_BASE = 16, 1855 ACPI_ERST_SET_DST_ADDRESS_BASE = 17, 1856 ACPI_ERST_MOVE_DATA = 18, 1857 ACPI_ERST_INSTRUCTION_RESERVED = 19 /* 19 and greater are reserved */ 1858 }; 1859 1860 /* Command status return values */ 1861 1862 enum AcpiErstCommandStatus 1863 { 1864 ACPI_ERST_SUCCESS = 0, 1865 ACPI_ERST_NO_SPACE = 1, 1866 ACPI_ERST_NOT_AVAILABLE = 2, 1867 ACPI_ERST_FAILURE = 3, 1868 ACPI_ERST_RECORD_EMPTY = 4, 1869 ACPI_ERST_NOT_FOUND = 5, 1870 ACPI_ERST_STATUS_RESERVED = 6 /* 6 and greater are reserved */ 1871 }; 1872 1873 1874 /* Error Record Serialization Information */ 1875 1876 typedef struct acpi_erst_info 1877 { 1878 UINT16 Signature; /* Should be "ER" */ 1879 UINT8 Data[48]; 1880 1881 } ACPI_ERST_INFO; 1882 1883 1884 /******************************************************************************* 1885 * 1886 * FPDT - Firmware Performance Data Table (ACPI 5.0) 1887 * Version 1 1888 * 1889 ******************************************************************************/ 1890 1891 typedef struct acpi_table_fpdt 1892 { 1893 ACPI_TABLE_HEADER Header; /* Common ACPI table header */ 1894 1895 } ACPI_TABLE_FPDT; 1896 1897 1898 /* FPDT subtable header (Performance Record Structure) */ 1899 1900 typedef struct acpi_fpdt_header 1901 { 1902 UINT16 Type; 1903 UINT8 Length; 1904 UINT8 Revision; 1905 1906 } ACPI_FPDT_HEADER; 1907 1908 /* Values for Type field above */ 1909 1910 enum AcpiFpdtType 1911 { 1912 ACPI_FPDT_TYPE_BOOT = 0, 1913 ACPI_FPDT_TYPE_S3PERF = 1 1914 }; 1915 1916 1917 /* 1918 * FPDT subtables 1919 */ 1920 1921 /* 0: Firmware Basic Boot Performance Record */ 1922 1923 typedef struct acpi_fpdt_boot_pointer 1924 { 1925 ACPI_FPDT_HEADER Header; 1926 UINT8 Reserved[4]; 1927 UINT64 Address; 1928 1929 } ACPI_FPDT_BOOT_POINTER; 1930 1931 1932 /* 1: S3 Performance Table Pointer Record */ 1933 1934 typedef struct acpi_fpdt_s3pt_pointer 1935 { 1936 ACPI_FPDT_HEADER Header; 1937 UINT8 Reserved[4]; 1938 UINT64 Address; 1939 1940 } ACPI_FPDT_S3PT_POINTER; 1941 1942 1943 /* 1944 * S3PT - S3 Performance Table. This table is pointed to by the 1945 * S3 Pointer Record above. 1946 */ 1947 typedef struct acpi_table_s3pt 1948 { 1949 UINT8 Signature[4]; /* "S3PT" */ 1950 UINT32 Length; 1951 1952 } ACPI_TABLE_S3PT; 1953 1954 1955 /* 1956 * S3PT Subtables (Not part of the actual FPDT) 1957 */ 1958 1959 /* Values for Type field in S3PT header */ 1960 1961 enum AcpiS3ptType 1962 { 1963 ACPI_S3PT_TYPE_RESUME = 0, 1964 ACPI_S3PT_TYPE_SUSPEND = 1, 1965 ACPI_FPDT_BOOT_PERFORMANCE = 2 1966 }; 1967 1968 typedef struct acpi_s3pt_resume 1969 { 1970 ACPI_FPDT_HEADER Header; 1971 UINT32 ResumeCount; 1972 UINT64 FullResume; 1973 UINT64 AverageResume; 1974 1975 } ACPI_S3PT_RESUME; 1976 1977 typedef struct acpi_s3pt_suspend 1978 { 1979 ACPI_FPDT_HEADER Header; 1980 UINT64 SuspendStart; 1981 UINT64 SuspendEnd; 1982 1983 } ACPI_S3PT_SUSPEND; 1984 1985 1986 /* 1987 * FPDT Boot Performance Record (Not part of the actual FPDT) 1988 */ 1989 typedef struct acpi_fpdt_boot 1990 { 1991 ACPI_FPDT_HEADER Header; 1992 UINT8 Reserved[4]; 1993 UINT64 ResetEnd; 1994 UINT64 LoadStart; 1995 UINT64 StartupStart; 1996 UINT64 ExitServicesEntry; 1997 UINT64 ExitServicesExit; 1998 1999 } ACPI_FPDT_BOOT; 2000 2001 2002 /******************************************************************************* 2003 * 2004 * GTDT - Generic Timer Description Table (ACPI 5.1) 2005 * Version 2 2006 * 2007 ******************************************************************************/ 2008 2009 typedef struct acpi_table_gtdt 2010 { 2011 ACPI_TABLE_HEADER Header; /* Common ACPI table header */ 2012 UINT64 CounterBlockAddresss; 2013 UINT32 Reserved; 2014 UINT32 SecureEl1Interrupt; 2015 UINT32 SecureEl1Flags; 2016 UINT32 NonSecureEl1Interrupt; 2017 UINT32 NonSecureEl1Flags; 2018 UINT32 VirtualTimerInterrupt; 2019 UINT32 VirtualTimerFlags; 2020 UINT32 NonSecureEl2Interrupt; 2021 UINT32 NonSecureEl2Flags; 2022 UINT64 CounterReadBlockAddress; 2023 UINT32 PlatformTimerCount; 2024 UINT32 PlatformTimerOffset; 2025 2026 } ACPI_TABLE_GTDT; 2027 2028 /* Flag Definitions: Timer Block Physical Timers and Virtual timers */ 2029 2030 #define ACPI_GTDT_INTERRUPT_MODE (1) 2031 #define ACPI_GTDT_INTERRUPT_POLARITY (1<<1) 2032 #define ACPI_GTDT_ALWAYS_ON (1<<2) 2033 2034 typedef struct acpi_gtdt_el2 2035 { 2036 UINT32 VirtualEL2TimerGsiv; 2037 UINT32 VirtualEL2TimerFlags; 2038 } ACPI_GTDT_EL2; 2039 2040 2041 /* Common GTDT subtable header */ 2042 2043 typedef struct acpi_gtdt_header 2044 { 2045 UINT8 Type; 2046 UINT16 Length; 2047 2048 } ACPI_GTDT_HEADER; 2049 2050 /* Values for GTDT subtable type above */ 2051 2052 enum AcpiGtdtType 2053 { 2054 ACPI_GTDT_TYPE_TIMER_BLOCK = 0, 2055 ACPI_GTDT_TYPE_WATCHDOG = 1, 2056 ACPI_GTDT_TYPE_RESERVED = 2 /* 2 and greater are reserved */ 2057 }; 2058 2059 2060 /* GTDT Subtables, correspond to Type in acpi_gtdt_header */ 2061 2062 /* 0: Generic Timer Block */ 2063 2064 typedef struct acpi_gtdt_timer_block 2065 { 2066 ACPI_GTDT_HEADER Header; 2067 UINT8 Reserved; 2068 UINT64 BlockAddress; 2069 UINT32 TimerCount; 2070 UINT32 TimerOffset; 2071 2072 } ACPI_GTDT_TIMER_BLOCK; 2073 2074 /* Timer Sub-Structure, one per timer */ 2075 2076 typedef struct acpi_gtdt_timer_entry 2077 { 2078 UINT8 FrameNumber; 2079 UINT8 Reserved[3]; 2080 UINT64 BaseAddress; 2081 UINT64 El0BaseAddress; 2082 UINT32 TimerInterrupt; 2083 UINT32 TimerFlags; 2084 UINT32 VirtualTimerInterrupt; 2085 UINT32 VirtualTimerFlags; 2086 UINT32 CommonFlags; 2087 2088 } ACPI_GTDT_TIMER_ENTRY; 2089 2090 /* Flag Definitions: TimerFlags and VirtualTimerFlags above */ 2091 2092 #define ACPI_GTDT_GT_IRQ_MODE (1) 2093 #define ACPI_GTDT_GT_IRQ_POLARITY (1<<1) 2094 2095 /* Flag Definitions: CommonFlags above */ 2096 2097 #define ACPI_GTDT_GT_IS_SECURE_TIMER (1) 2098 #define ACPI_GTDT_GT_ALWAYS_ON (1<<1) 2099 2100 2101 /* 1: SBSA Generic Watchdog Structure */ 2102 2103 typedef struct acpi_gtdt_watchdog 2104 { 2105 ACPI_GTDT_HEADER Header; 2106 UINT8 Reserved; 2107 UINT64 RefreshFrameAddress; 2108 UINT64 ControlFrameAddress; 2109 UINT32 TimerInterrupt; 2110 UINT32 TimerFlags; 2111 2112 } ACPI_GTDT_WATCHDOG; 2113 2114 /* Flag Definitions: TimerFlags above */ 2115 2116 #define ACPI_GTDT_WATCHDOG_IRQ_MODE (1) 2117 #define ACPI_GTDT_WATCHDOG_IRQ_POLARITY (1<<1) 2118 #define ACPI_GTDT_WATCHDOG_SECURE (1<<2) 2119 2120 2121 /******************************************************************************* 2122 * 2123 * HEST - Hardware Error Source Table (ACPI 4.0) 2124 * Version 1 2125 * 2126 ******************************************************************************/ 2127 2128 typedef struct acpi_table_hest 2129 { 2130 ACPI_TABLE_HEADER Header; /* Common ACPI table header */ 2131 UINT32 ErrorSourceCount; 2132 2133 } ACPI_TABLE_HEST; 2134 2135 2136 /* HEST subtable header */ 2137 2138 typedef struct acpi_hest_header 2139 { 2140 UINT16 Type; 2141 UINT16 SourceId; 2142 2143 } ACPI_HEST_HEADER; 2144 2145 2146 /* Values for Type field above for subtables */ 2147 2148 enum AcpiHestTypes 2149 { 2150 ACPI_HEST_TYPE_IA32_CHECK = 0, 2151 ACPI_HEST_TYPE_IA32_CORRECTED_CHECK = 1, 2152 ACPI_HEST_TYPE_IA32_NMI = 2, 2153 ACPI_HEST_TYPE_NOT_USED3 = 3, 2154 ACPI_HEST_TYPE_NOT_USED4 = 4, 2155 ACPI_HEST_TYPE_NOT_USED5 = 5, 2156 ACPI_HEST_TYPE_AER_ROOT_PORT = 6, 2157 ACPI_HEST_TYPE_AER_ENDPOINT = 7, 2158 ACPI_HEST_TYPE_AER_BRIDGE = 8, 2159 ACPI_HEST_TYPE_GENERIC_ERROR = 9, 2160 ACPI_HEST_TYPE_GENERIC_ERROR_V2 = 10, 2161 ACPI_HEST_TYPE_IA32_DEFERRED_CHECK = 11, 2162 ACPI_HEST_TYPE_RESERVED = 12 /* 12 and greater are reserved */ 2163 }; 2164 2165 2166 /* 2167 * HEST substructures contained in subtables 2168 */ 2169 2170 /* 2171 * IA32 Error Bank(s) - Follows the ACPI_HEST_IA_MACHINE_CHECK and 2172 * ACPI_HEST_IA_CORRECTED structures. 2173 */ 2174 typedef struct acpi_hest_ia_error_bank 2175 { 2176 UINT8 BankNumber; 2177 UINT8 ClearStatusOnInit; 2178 UINT8 StatusFormat; 2179 UINT8 Reserved; 2180 UINT32 ControlRegister; 2181 UINT64 ControlData; 2182 UINT32 StatusRegister; 2183 UINT32 AddressRegister; 2184 UINT32 MiscRegister; 2185 2186 } ACPI_HEST_IA_ERROR_BANK; 2187 2188 2189 /* Common HEST sub-structure for PCI/AER structures below (6,7,8) */ 2190 2191 typedef struct acpi_hest_aer_common 2192 { 2193 UINT16 Reserved1; 2194 UINT8 Flags; 2195 UINT8 Enabled; 2196 UINT32 RecordsToPreallocate; 2197 UINT32 MaxSectionsPerRecord; 2198 UINT32 Bus; /* Bus and Segment numbers */ 2199 UINT16 Device; 2200 UINT16 Function; 2201 UINT16 DeviceControl; 2202 UINT16 Reserved2; 2203 UINT32 UncorrectableMask; 2204 UINT32 UncorrectableSeverity; 2205 UINT32 CorrectableMask; 2206 UINT32 AdvancedCapabilities; 2207 2208 } ACPI_HEST_AER_COMMON; 2209 2210 /* Masks for HEST Flags fields */ 2211 2212 #define ACPI_HEST_FIRMWARE_FIRST (1) 2213 #define ACPI_HEST_GLOBAL (1<<1) 2214 #define ACPI_HEST_GHES_ASSIST (1<<2) 2215 2216 /* 2217 * Macros to access the bus/segment numbers in Bus field above: 2218 * Bus number is encoded in bits 7:0 2219 * Segment number is encoded in bits 23:8 2220 */ 2221 #define ACPI_HEST_BUS(Bus) ((Bus) & 0xFF) 2222 #define ACPI_HEST_SEGMENT(Bus) (((Bus) >> 8) & 0xFFFF) 2223 2224 2225 /* Hardware Error Notification */ 2226 2227 typedef struct acpi_hest_notify 2228 { 2229 UINT8 Type; 2230 UINT8 Length; 2231 UINT16 ConfigWriteEnable; 2232 UINT32 PollInterval; 2233 UINT32 Vector; 2234 UINT32 PollingThresholdValue; 2235 UINT32 PollingThresholdWindow; 2236 UINT32 ErrorThresholdValue; 2237 UINT32 ErrorThresholdWindow; 2238 2239 } ACPI_HEST_NOTIFY; 2240 2241 /* Values for Notify Type field above */ 2242 2243 enum AcpiHestNotifyTypes 2244 { 2245 ACPI_HEST_NOTIFY_POLLED = 0, 2246 ACPI_HEST_NOTIFY_EXTERNAL = 1, 2247 ACPI_HEST_NOTIFY_LOCAL = 2, 2248 ACPI_HEST_NOTIFY_SCI = 3, 2249 ACPI_HEST_NOTIFY_NMI = 4, 2250 ACPI_HEST_NOTIFY_CMCI = 5, /* ACPI 5.0 */ 2251 ACPI_HEST_NOTIFY_MCE = 6, /* ACPI 5.0 */ 2252 ACPI_HEST_NOTIFY_GPIO = 7, /* ACPI 6.0 */ 2253 ACPI_HEST_NOTIFY_SEA = 8, /* ACPI 6.1 */ 2254 ACPI_HEST_NOTIFY_SEI = 9, /* ACPI 6.1 */ 2255 ACPI_HEST_NOTIFY_GSIV = 10, /* ACPI 6.1 */ 2256 ACPI_HEST_NOTIFY_SOFTWARE_DELEGATED = 11, /* ACPI 6.2 */ 2257 ACPI_HEST_NOTIFY_RESERVED = 12 /* 12 and greater are reserved */ 2258 }; 2259 2260 /* Values for ConfigWriteEnable bitfield above */ 2261 2262 #define ACPI_HEST_TYPE (1) 2263 #define ACPI_HEST_POLL_INTERVAL (1<<1) 2264 #define ACPI_HEST_POLL_THRESHOLD_VALUE (1<<2) 2265 #define ACPI_HEST_POLL_THRESHOLD_WINDOW (1<<3) 2266 #define ACPI_HEST_ERR_THRESHOLD_VALUE (1<<4) 2267 #define ACPI_HEST_ERR_THRESHOLD_WINDOW (1<<5) 2268 2269 2270 /* 2271 * HEST subtables 2272 */ 2273 2274 /* 0: IA32 Machine Check Exception */ 2275 2276 typedef struct acpi_hest_ia_machine_check 2277 { 2278 ACPI_HEST_HEADER Header; 2279 UINT16 Reserved1; 2280 UINT8 Flags; /* See flags ACPI_HEST_GLOBAL, etc. above */ 2281 UINT8 Enabled; 2282 UINT32 RecordsToPreallocate; 2283 UINT32 MaxSectionsPerRecord; 2284 UINT64 GlobalCapabilityData; 2285 UINT64 GlobalControlData; 2286 UINT8 NumHardwareBanks; 2287 UINT8 Reserved3[7]; 2288 2289 } ACPI_HEST_IA_MACHINE_CHECK; 2290 2291 2292 /* 1: IA32 Corrected Machine Check */ 2293 2294 typedef struct acpi_hest_ia_corrected 2295 { 2296 ACPI_HEST_HEADER Header; 2297 UINT16 Reserved1; 2298 UINT8 Flags; /* See flags ACPI_HEST_GLOBAL, etc. above */ 2299 UINT8 Enabled; 2300 UINT32 RecordsToPreallocate; 2301 UINT32 MaxSectionsPerRecord; 2302 ACPI_HEST_NOTIFY Notify; 2303 UINT8 NumHardwareBanks; 2304 UINT8 Reserved2[3]; 2305 2306 } ACPI_HEST_IA_CORRECTED; 2307 2308 2309 /* 2: IA32 Non-Maskable Interrupt */ 2310 2311 typedef struct acpi_hest_ia_nmi 2312 { 2313 ACPI_HEST_HEADER Header; 2314 UINT32 Reserved; 2315 UINT32 RecordsToPreallocate; 2316 UINT32 MaxSectionsPerRecord; 2317 UINT32 MaxRawDataLength; 2318 2319 } ACPI_HEST_IA_NMI; 2320 2321 2322 /* 3,4,5: Not used */ 2323 2324 /* 6: PCI Express Root Port AER */ 2325 2326 typedef struct acpi_hest_aer_root 2327 { 2328 ACPI_HEST_HEADER Header; 2329 ACPI_HEST_AER_COMMON Aer; 2330 UINT32 RootErrorCommand; 2331 2332 } ACPI_HEST_AER_ROOT; 2333 2334 2335 /* 7: PCI Express AER (AER Endpoint) */ 2336 2337 typedef struct acpi_hest_aer 2338 { 2339 ACPI_HEST_HEADER Header; 2340 ACPI_HEST_AER_COMMON Aer; 2341 2342 } ACPI_HEST_AER; 2343 2344 2345 /* 8: PCI Express/PCI-X Bridge AER */ 2346 2347 typedef struct acpi_hest_aer_bridge 2348 { 2349 ACPI_HEST_HEADER Header; 2350 ACPI_HEST_AER_COMMON Aer; 2351 UINT32 UncorrectableMask2; 2352 UINT32 UncorrectableSeverity2; 2353 UINT32 AdvancedCapabilities2; 2354 2355 } ACPI_HEST_AER_BRIDGE; 2356 2357 2358 /* 9: Generic Hardware Error Source */ 2359 2360 typedef struct acpi_hest_generic 2361 { 2362 ACPI_HEST_HEADER Header; 2363 UINT16 RelatedSourceId; 2364 UINT8 Reserved; 2365 UINT8 Enabled; 2366 UINT32 RecordsToPreallocate; 2367 UINT32 MaxSectionsPerRecord; 2368 UINT32 MaxRawDataLength; 2369 ACPI_GENERIC_ADDRESS ErrorStatusAddress; 2370 ACPI_HEST_NOTIFY Notify; 2371 UINT32 ErrorBlockLength; 2372 2373 } ACPI_HEST_GENERIC; 2374 2375 2376 /* 10: Generic Hardware Error Source, version 2 */ 2377 2378 typedef struct acpi_hest_generic_v2 2379 { 2380 ACPI_HEST_HEADER Header; 2381 UINT16 RelatedSourceId; 2382 UINT8 Reserved; 2383 UINT8 Enabled; 2384 UINT32 RecordsToPreallocate; 2385 UINT32 MaxSectionsPerRecord; 2386 UINT32 MaxRawDataLength; 2387 ACPI_GENERIC_ADDRESS ErrorStatusAddress; 2388 ACPI_HEST_NOTIFY Notify; 2389 UINT32 ErrorBlockLength; 2390 ACPI_GENERIC_ADDRESS ReadAckRegister; 2391 UINT64 ReadAckPreserve; 2392 UINT64 ReadAckWrite; 2393 2394 } ACPI_HEST_GENERIC_V2; 2395 2396 2397 /* Generic Error Status block */ 2398 2399 typedef struct acpi_hest_generic_status 2400 { 2401 UINT32 BlockStatus; 2402 UINT32 RawDataOffset; 2403 UINT32 RawDataLength; 2404 UINT32 DataLength; 2405 UINT32 ErrorSeverity; 2406 2407 } ACPI_HEST_GENERIC_STATUS; 2408 2409 /* Values for BlockStatus flags above */ 2410 2411 #define ACPI_HEST_UNCORRECTABLE (1) 2412 #define ACPI_HEST_CORRECTABLE (1<<1) 2413 #define ACPI_HEST_MULTIPLE_UNCORRECTABLE (1<<2) 2414 #define ACPI_HEST_MULTIPLE_CORRECTABLE (1<<3) 2415 #define ACPI_HEST_ERROR_ENTRY_COUNT (0xFF<<4) /* 8 bits, error count */ 2416 2417 2418 /* Generic Error Data entry */ 2419 2420 typedef struct acpi_hest_generic_data 2421 { 2422 UINT8 SectionType[16]; 2423 UINT32 ErrorSeverity; 2424 UINT16 Revision; 2425 UINT8 ValidationBits; 2426 UINT8 Flags; 2427 UINT32 ErrorDataLength; 2428 UINT8 FruId[16]; 2429 UINT8 FruText[20]; 2430 2431 } ACPI_HEST_GENERIC_DATA; 2432 2433 /* Extension for revision 0x0300 */ 2434 2435 typedef struct acpi_hest_generic_data_v300 2436 { 2437 UINT8 SectionType[16]; 2438 UINT32 ErrorSeverity; 2439 UINT16 Revision; 2440 UINT8 ValidationBits; 2441 UINT8 Flags; 2442 UINT32 ErrorDataLength; 2443 UINT8 FruId[16]; 2444 UINT8 FruText[20]; 2445 UINT64 TimeStamp; 2446 2447 } ACPI_HEST_GENERIC_DATA_V300; 2448 2449 /* Values for ErrorSeverity above */ 2450 2451 #define ACPI_HEST_GEN_ERROR_RECOVERABLE 0 2452 #define ACPI_HEST_GEN_ERROR_FATAL 1 2453 #define ACPI_HEST_GEN_ERROR_CORRECTED 2 2454 #define ACPI_HEST_GEN_ERROR_NONE 3 2455 2456 /* Flags for ValidationBits above */ 2457 2458 #define ACPI_HEST_GEN_VALID_FRU_ID (1) 2459 #define ACPI_HEST_GEN_VALID_FRU_STRING (1<<1) 2460 #define ACPI_HEST_GEN_VALID_TIMESTAMP (1<<2) 2461 2462 2463 /* 11: IA32 Deferred Machine Check Exception (ACPI 6.2) */ 2464 2465 typedef struct acpi_hest_ia_deferred_check 2466 { 2467 ACPI_HEST_HEADER Header; 2468 UINT16 Reserved1; 2469 UINT8 Flags; /* See flags ACPI_HEST_GLOBAL, etc. above */ 2470 UINT8 Enabled; 2471 UINT32 RecordsToPreallocate; 2472 UINT32 MaxSectionsPerRecord; 2473 ACPI_HEST_NOTIFY Notify; 2474 UINT8 NumHardwareBanks; 2475 UINT8 Reserved2[3]; 2476 2477 } ACPI_HEST_IA_DEFERRED_CHECK; 2478 2479 2480 /******************************************************************************* 2481 * 2482 * HMAT - Heterogeneous Memory Attributes Table (ACPI 6.3) 2483 * 2484 ******************************************************************************/ 2485 2486 typedef struct acpi_table_hmat 2487 { 2488 ACPI_TABLE_HEADER Header; /* Common ACPI table header */ 2489 UINT32 Reserved; 2490 2491 } ACPI_TABLE_HMAT; 2492 2493 2494 /* Values for HMAT structure types */ 2495 2496 enum AcpiHmatType 2497 { 2498 ACPI_HMAT_TYPE_ADDRESS_RANGE = 0, /* Memory subsystem address range */ 2499 ACPI_HMAT_TYPE_LOCALITY = 1, /* System locality latency and bandwidth information */ 2500 ACPI_HMAT_TYPE_CACHE = 2, /* Memory side cache information */ 2501 ACPI_HMAT_TYPE_RESERVED = 3 /* 3 and greater are reserved */ 2502 }; 2503 2504 typedef struct acpi_hmat_structure 2505 { 2506 UINT16 Type; 2507 UINT16 Reserved; 2508 UINT32 Length; 2509 2510 } ACPI_HMAT_STRUCTURE; 2511 2512 2513 /* 2514 * HMAT Structures, correspond to Type in ACPI_HMAT_STRUCTURE 2515 */ 2516 2517 /* 0: Memory proximity domain attributes */ 2518 2519 typedef struct acpi_hmat_proximity_domain 2520 { 2521 ACPI_HMAT_STRUCTURE Header; 2522 UINT16 Flags; 2523 UINT16 Reserved1; 2524 UINT32 InitiatorPD; /* Attached Initiator proximity domain */ 2525 UINT32 MemoryPD; /* Memory proximity domain */ 2526 UINT32 Reserved2; 2527 UINT64 Reserved3; 2528 UINT64 Reserved4; 2529 2530 } ACPI_HMAT_PROXIMITY_DOMAIN; 2531 2532 /* Masks for Flags field above */ 2533 2534 #define ACPI_HMAT_INITIATOR_PD_VALID (1) /* 1: InitiatorPD field is valid */ 2535 2536 2537 /* 1: System locality latency and bandwidth information */ 2538 2539 typedef struct acpi_hmat_locality 2540 { 2541 ACPI_HMAT_STRUCTURE Header; 2542 UINT8 Flags; 2543 UINT8 DataType; 2544 UINT8 MinTransferSize; 2545 UINT8 Reserved1; 2546 UINT32 NumberOfInitiatorPDs; 2547 UINT32 NumberOfTargetPDs; 2548 UINT32 Reserved2; 2549 UINT64 EntryBaseUnit; 2550 2551 } ACPI_HMAT_LOCALITY; 2552 2553 /* Masks for Flags field above */ 2554 2555 #define ACPI_HMAT_MEMORY_HIERARCHY (0x0F) /* Bits 0-3 */ 2556 2557 /* Values for Memory Hierarchy flags */ 2558 2559 #define ACPI_HMAT_MEMORY 0 2560 #define ACPI_HMAT_1ST_LEVEL_CACHE 1 2561 #define ACPI_HMAT_2ND_LEVEL_CACHE 2 2562 #define ACPI_HMAT_3RD_LEVEL_CACHE 3 2563 #define ACPI_HMAT_MINIMUM_XFER_SIZE 0x10 /* Bit 4: ACPI 6.4 */ 2564 #define ACPI_HMAT_NON_SEQUENTIAL_XFERS 0x20 /* Bit 5: ACPI 6.4 */ 2565 2566 2567 /* Values for DataType field above */ 2568 2569 #define ACPI_HMAT_ACCESS_LATENCY 0 2570 #define ACPI_HMAT_READ_LATENCY 1 2571 #define ACPI_HMAT_WRITE_LATENCY 2 2572 #define ACPI_HMAT_ACCESS_BANDWIDTH 3 2573 #define ACPI_HMAT_READ_BANDWIDTH 4 2574 #define ACPI_HMAT_WRITE_BANDWIDTH 5 2575 2576 2577 /* 2: Memory side cache information */ 2578 2579 typedef struct acpi_hmat_cache 2580 { 2581 ACPI_HMAT_STRUCTURE Header; 2582 UINT32 MemoryPD; 2583 UINT32 Reserved1; 2584 UINT64 CacheSize; 2585 UINT32 CacheAttributes; 2586 UINT16 AddressMode; 2587 UINT16 NumberOfSMBIOSHandles; 2588 2589 } ACPI_HMAT_CACHE; 2590 2591 /* Masks for CacheAttributes field above */ 2592 2593 #define ACPI_HMAT_TOTAL_CACHE_LEVEL (0x0000000F) 2594 #define ACPI_HMAT_CACHE_LEVEL (0x000000F0) 2595 #define ACPI_HMAT_CACHE_ASSOCIATIVITY (0x00000F00) 2596 #define ACPI_HMAT_WRITE_POLICY (0x0000F000) 2597 #define ACPI_HMAT_CACHE_LINE_SIZE (0xFFFF0000) 2598 2599 #define ACPI_HMAT_CACHE_MODE_UNKNOWN (0) 2600 #define ACPI_HMAT_CACHE_MODE_EXTENDED_LINEAR (1) 2601 2602 /* Values for cache associativity flag */ 2603 2604 #define ACPI_HMAT_CA_NONE (0) 2605 #define ACPI_HMAT_CA_DIRECT_MAPPED (1) 2606 #define ACPI_HMAT_CA_COMPLEX_CACHE_INDEXING (2) 2607 2608 /* Values for write policy flag */ 2609 2610 #define ACPI_HMAT_CP_NONE (0) 2611 #define ACPI_HMAT_CP_WB (1) 2612 #define ACPI_HMAT_CP_WT (2) 2613 2614 2615 /******************************************************************************* 2616 * 2617 * HPET - High Precision Event Timer table 2618 * Version 1 2619 * 2620 * Conforms to "IA-PC HPET (High Precision Event Timers) Specification", 2621 * Version 1.0a, October 2004 2622 * 2623 ******************************************************************************/ 2624 2625 typedef struct acpi_table_hpet 2626 { 2627 ACPI_TABLE_HEADER Header; /* Common ACPI table header */ 2628 UINT32 Id; /* Hardware ID of event timer block */ 2629 ACPI_GENERIC_ADDRESS Address; /* Address of event timer block */ 2630 UINT8 Sequence; /* HPET sequence number */ 2631 UINT16 MinimumTick; /* Main counter min tick, periodic mode */ 2632 UINT8 Flags; 2633 2634 } ACPI_TABLE_HPET; 2635 2636 /* Masks for Flags field above */ 2637 2638 #define ACPI_HPET_PAGE_PROTECT_MASK (3) 2639 2640 /* Values for Page Protect flags */ 2641 2642 enum AcpiHpetPageProtect 2643 { 2644 ACPI_HPET_NO_PAGE_PROTECT = 0, 2645 ACPI_HPET_PAGE_PROTECT4 = 1, 2646 ACPI_HPET_PAGE_PROTECT64 = 2 2647 }; 2648 2649 2650 /******************************************************************************* 2651 * 2652 * IBFT - Boot Firmware Table 2653 * Version 1 2654 * 2655 * Conforms to "iSCSI Boot Firmware Table (iBFT) as Defined in ACPI 3.0b 2656 * Specification", Version 1.01, March 1, 2007 2657 * 2658 * Note: It appears that this table is not intended to appear in the RSDT/XSDT. 2659 * Therefore, it is not currently supported by the disassembler. 2660 * 2661 ******************************************************************************/ 2662 2663 typedef struct acpi_table_ibft 2664 { 2665 ACPI_TABLE_HEADER Header; /* Common ACPI table header */ 2666 UINT8 Reserved[12]; 2667 2668 } ACPI_TABLE_IBFT; 2669 2670 2671 /* IBFT common subtable header */ 2672 2673 typedef struct acpi_ibft_header 2674 { 2675 UINT8 Type; 2676 UINT8 Version; 2677 UINT16 Length; 2678 UINT8 Index; 2679 UINT8 Flags; 2680 2681 } ACPI_IBFT_HEADER; 2682 2683 /* Values for Type field above */ 2684 2685 enum AcpiIbftType 2686 { 2687 ACPI_IBFT_TYPE_NOT_USED = 0, 2688 ACPI_IBFT_TYPE_CONTROL = 1, 2689 ACPI_IBFT_TYPE_INITIATOR = 2, 2690 ACPI_IBFT_TYPE_NIC = 3, 2691 ACPI_IBFT_TYPE_TARGET = 4, 2692 ACPI_IBFT_TYPE_EXTENSIONS = 5, 2693 ACPI_IBFT_TYPE_RESERVED = 6 /* 6 and greater are reserved */ 2694 }; 2695 2696 2697 /* IBFT subtables */ 2698 2699 typedef struct acpi_ibft_control 2700 { 2701 ACPI_IBFT_HEADER Header; 2702 UINT16 Extensions; 2703 UINT16 InitiatorOffset; 2704 UINT16 Nic0Offset; 2705 UINT16 Target0Offset; 2706 UINT16 Nic1Offset; 2707 UINT16 Target1Offset; 2708 2709 } ACPI_IBFT_CONTROL; 2710 2711 typedef struct acpi_ibft_initiator 2712 { 2713 ACPI_IBFT_HEADER Header; 2714 UINT8 SnsServer[16]; 2715 UINT8 SlpServer[16]; 2716 UINT8 PrimaryServer[16]; 2717 UINT8 SecondaryServer[16]; 2718 UINT16 NameLength; 2719 UINT16 NameOffset; 2720 2721 } ACPI_IBFT_INITIATOR; 2722 2723 typedef struct acpi_ibft_nic 2724 { 2725 ACPI_IBFT_HEADER Header; 2726 UINT8 IpAddress[16]; 2727 UINT8 SubnetMaskPrefix; 2728 UINT8 Origin; 2729 UINT8 Gateway[16]; 2730 UINT8 PrimaryDns[16]; 2731 UINT8 SecondaryDns[16]; 2732 UINT8 Dhcp[16]; 2733 UINT16 Vlan; 2734 UINT8 MacAddress[6]; 2735 UINT16 PciAddress; 2736 UINT16 NameLength; 2737 UINT16 NameOffset; 2738 2739 } ACPI_IBFT_NIC; 2740 2741 typedef struct acpi_ibft_target 2742 { 2743 ACPI_IBFT_HEADER Header; 2744 UINT8 TargetIpAddress[16]; 2745 UINT16 TargetIpSocket; 2746 UINT8 TargetBootLun[8]; 2747 UINT8 ChapType; 2748 UINT8 NicAssociation; 2749 UINT16 TargetNameLength; 2750 UINT16 TargetNameOffset; 2751 UINT16 ChapNameLength; 2752 UINT16 ChapNameOffset; 2753 UINT16 ChapSecretLength; 2754 UINT16 ChapSecretOffset; 2755 UINT16 ReverseChapNameLength; 2756 UINT16 ReverseChapNameOffset; 2757 UINT16 ReverseChapSecretLength; 2758 UINT16 ReverseChapSecretOffset; 2759 2760 } ACPI_IBFT_TARGET; 2761 2762 /* Reset to default packing */ 2763 2764 #pragma pack() 2765 2766 #endif /* __ACTBL1_H__ */ 2767