1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 1996-2008, 4Front Technologies 5 * Copyright (C) 1992-2000 Don Kim (don.kim@esstech.com) 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHERIN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 * 29 */ 30 31 /*--------------------------------------------------------------------------- 32 * Copyright (C) 1997-1999, ESS Technology, Inc. 33 * This source code, its compiled object code, and its associated data sets 34 * are copyright (C) 1997-1999 ESS Technology, Inc. 35 *--------------------------------------------------------------------------- 36 * This header contains data structures and registers taken from the 37 * 4Front OSS Allegro BSD licensed driver (in the Attic/ directory). 38 * Files used for this header include: 39 * hardware.h 40 * kernel.h and hckernel.h 41 * srcmgr.h 42 *--------------------------------------------------------------------------- 43 */ 44 45 #ifndef _DEV_SOUND_PCI_ALLEGRO_REG_H 46 #define _DEV_SOUND_PCI_ALLEGRO_REG_H 47 48 /* Allegro PCI configuration registers */ 49 #define PCI_LEGACY_AUDIO_CTRL 0x40 50 #define SOUND_BLASTER_ENABLE 0x00000001 51 #define FM_SYNTHESIS_ENABLE 0x00000002 52 #define GAME_PORT_ENABLE 0x00000004 53 #define MPU401_IO_ENABLE 0x00000008 54 #define MPU401_IRQ_ENABLE 0x00000010 55 #define ALIAS_10BIT_IO 0x00000020 56 #define SB_DMA_MASK 0x000000C0 57 #define SB_DMA_0 0x00000040 58 #define SB_DMA_1 0x00000040 59 #define SB_DMA_R 0x00000080 60 #define SB_DMA_3 0x000000C0 61 #define SB_IRQ_MASK 0x00000700 62 #define SB_IRQ_5 0x00000000 63 #define SB_IRQ_7 0x00000100 64 #define SB_IRQ_9 0x00000200 65 #define SB_IRQ_10 0x00000300 66 #define MIDI_IRQ_MASK 0x00003800 67 #define SERIAL_IRQ_ENABLE 0x00004000 68 #define DISABLE_LEGACY 0x00008000 69 70 #define PCI_ALLEGRO_CONFIG 0x50 71 #define SB_ADDR_240 0x00000004 72 #define MPU_ADDR_MASK 0x00000018 73 #define MPU_ADDR_330 0x00000000 74 #define MPU_ADDR_300 0x00000008 75 #define MPU_ADDR_320 0x00000010 76 #define MPU_ADDR_340 0x00000018 77 #define USE_PCI_TIMING 0x00000040 78 #define POSTED_WRITE_ENABLE 0x00000080 79 #define DMA_POLICY_MASK 0x00000700 80 #define DMA_DDMA 0x00000000 81 #define DMA_TDMA 0x00000100 82 #define DMA_PCPCI 0x00000200 83 #define DMA_WBDMA16 0x00000400 84 #define DMA_WBDMA4 0x00000500 85 #define DMA_WBDMA2 0x00000600 86 #define DMA_WBDMA1 0x00000700 87 #define DMA_SAFE_GUARD 0x00000800 88 #define HI_PERF_GP_ENABLE 0x00001000 89 #define PIC_SNOOP_MODE_0 0x00002000 90 #define PIC_SNOOP_MODE_1 0x00004000 91 #define SOUNDBLASTER_IRQ_MASK 0x00008000 92 #define RING_IN_ENABLE 0x00010000 93 #define SPDIF_TEST_MODE 0x00020000 94 #define CLK_MULT_MODE_SELECT_2 0x00040000 95 #define EEPROM_WRITE_ENABLE 0x00080000 96 #define CODEC_DIR_IN 0x00100000 97 #define HV_BUTTON_FROM_GD 0x00200000 98 #define REDUCED_DEBOUNCE 0x00400000 99 #define HV_CTRL_ENABLE 0x00800000 100 #define SPDIF_ENABLE 0x01000000 101 #define CLK_DIV_SELECT 0x06000000 102 #define CLK_DIV_BY_48 0x00000000 103 #define CLK_DIV_BY_49 0x02000000 104 #define CLK_DIV_BY_50 0x04000000 105 #define CLK_DIV_RESERVED 0x06000000 106 #define PM_CTRL_ENABLE 0x08000000 107 #define CLK_MULT_MODE_SELECT 0x30000000 108 #define CLK_MULT_MODE_SHIFT 28 109 #define CLK_MULT_MODE_0 0x00000000 110 #define CLK_MULT_MODE_1 0x10000000 111 #define CLK_MULT_MODE_2 0x20000000 112 #define CLK_MULT_MODE_3 0x30000000 113 #define INT_CLK_SELECT 0x40000000 114 #define INT_CLK_MULT_RESET 0x80000000 115 116 /* M3 */ 117 #define INT_CLK_SRC_NOT_PCI 0x00100000 118 #define INT_CLK_MULT_ENABLE 0x80000000 119 120 #define PCI_ACPI_CONTROL 0x54 121 #define PCI_ACPI_D0 0x00000000 122 #define PCI_ACPI_D1 0xB4F70000 123 #define PCI_ACPI_D2 0xB4F7B4F7 124 125 #define PCI_USER_CONFIG 0x58 126 #define EXT_PCI_MASTER_ENABLE 0x00000001 127 #define SPDIF_OUT_SELECT 0x00000002 128 #define TEST_PIN_DIR_CTRL 0x00000004 129 #define AC97_CODEC_TEST 0x00000020 130 #define TRI_STATE_BUFFER 0x00000080 131 #define IN_CLK_12MHZ_SELECT 0x00000100 132 #define MULTI_FUNC_DISABLE 0x00000200 133 #define EXT_MASTER_PAIR_SEL 0x00000400 134 #define PCI_MASTER_SUPPORT 0x00000800 135 #define STOP_CLOCK_ENABLE 0x00001000 136 #define EAPD_DRIVE_ENABLE 0x00002000 137 #define REQ_TRI_STATE_ENABLE 0x00004000 138 #define REQ_LOW_ENABLE 0x00008000 139 #define MIDI_1_ENABLE 0x00010000 140 #define MIDI_2_ENABLE 0x00020000 141 #define SB_AUDIO_SYNC 0x00040000 142 #define HV_CTRL_TEST 0x00100000 143 #define SOUNDBLASTER_TEST 0x00400000 144 145 #define PCI_USER_CONFIG_C 0x5C 146 147 #define PCI_DDMA_CTRL 0x60 148 #define DDMA_ENABLE 0x00000001 149 150 /* Allegro registers */ 151 #define HOST_INT_CTRL 0x18 152 #define SB_INT_ENABLE 0x0001 153 #define MPU401_INT_ENABLE 0x0002 154 #define ASSP_INT_ENABLE 0x0010 155 #define RING_INT_ENABLE 0x0020 156 #define HV_INT_ENABLE 0x0040 157 #define CLKRUN_GEN_ENABLE 0x0100 158 #define HV_CTRL_TO_PME 0x0400 159 #define SOFTWARE_RESET_ENABLE 0x8000 160 161 #define HOST_INT_STATUS 0x1A 162 #define SB_INT_PENDING 0x01 163 #define MPU401_INT_PENDING 0x02 164 #define ASSP_INT_PENDING 0x10 165 #define RING_INT_PENDING 0x20 166 #define HV_INT_PENDING 0x40 167 168 #define HARDWARE_VOL_CTRL 0x1B 169 #define SHADOW_MIX_REG_VOICE 0x1C 170 #define HW_VOL_COUNTER_VOICE 0x1D 171 #define SHADOW_MIX_REG_MASTER 0x1E 172 #define HW_VOL_COUNTER_MASTER 0x1F 173 174 #define CODEC_COMMAND 0x30 175 #define CODEC_READ_B 0x80 176 177 #define CODEC_STATUS 0x30 178 #define CODEC_BUSY_B 0x01 179 180 #define CODEC_DATA 0x32 181 182 /* AC97 registers */ 183 #ifndef M3_MODEL 184 #define AC97_RESET 0x00 185 #endif 186 187 #define AC97_VOL_MUTE_B 0x8000 188 #define AC97_VOL_M 0x1F 189 #define AC97_LEFT_VOL_S 8 190 191 #define AC97_MASTER_VOL 0x02 192 #define AC97_LINE_LEVEL_VOL 0x04 193 #define AC97_MASTER_MONO_VOL 0x06 194 #define AC97_PC_BEEP_VOL 0x0A 195 #define AC97_PC_BEEP_VOL_M 0x0F 196 #define AC97_SROUND_MASTER_VOL 0x38 197 #define AC97_PC_BEEP_VOL_S 1 198 199 #ifndef M3_MODEL 200 #define AC97_PHONE_VOL 0x0C 201 #define AC97_MIC_VOL 0x0E 202 #endif 203 #define AC97_MIC_20DB_ENABLE 0x40 204 205 #ifndef M3_MODEL 206 #define AC97_LINEIN_VOL 0x10 207 #define AC97_CD_VOL 0x12 208 #define AC97_VIDEO_VOL 0x14 209 #define AC97_AUX_VOL 0x16 210 #endif 211 #define AC97_PCM_OUT_VOL 0x18 212 #ifndef M3_MODEL 213 #define AC97_RECORD_SELECT 0x1A 214 #endif 215 #define AC97_RECORD_MIC 0x00 216 #define AC97_RECORD_CD 0x01 217 #define AC97_RECORD_VIDEO 0x02 218 #define AC97_RECORD_AUX 0x03 219 #define AC97_RECORD_MONO_MUX 0x02 220 #define AC97_RECORD_DIGITAL 0x03 221 #define AC97_RECORD_LINE 0x04 222 #define AC97_RECORD_STEREO 0x05 223 #define AC97_RECORD_MONO 0x06 224 #define AC97_RECORD_PHONE 0x07 225 226 #ifndef M3_MODEL 227 #define AC97_RECORD_GAIN 0x1C 228 #endif 229 #define AC97_RECORD_VOL_M 0x0F 230 231 #ifndef M3_MODEL 232 #define AC97_GENERAL_PURPOSE 0x20 233 #endif 234 #define AC97_POWER_DOWN_CTRL 0x26 235 #define AC97_ADC_READY 0x0001 236 #define AC97_DAC_READY 0x0002 237 #define AC97_ANALOG_READY 0x0004 238 #define AC97_VREF_ON 0x0008 239 #define AC97_PR0 0x0100 240 #define AC97_PR1 0x0200 241 #define AC97_PR2 0x0400 242 #define AC97_PR3 0x0800 243 #define AC97_PR4 0x1000 244 245 #define AC97_RESERVED1 0x28 246 247 #define AC97_VENDOR_TEST 0x5A 248 249 #define AC97_CLOCK_DELAY 0x5C 250 #define AC97_LINEOUT_MUX_SEL 0x0001 251 #define AC97_MONO_MUX_SEL 0x0002 252 #define AC97_CLOCK_DELAY_SEL 0x1F 253 #define AC97_DAC_CDS_SHIFT 6 254 #define AC97_ADC_CDS_SHIFT 11 255 256 #define AC97_MULTI_CHANNEL_SEL 0x74 257 258 #ifndef M3_MODEL 259 #define AC97_VENDOR_ID1 0x7C 260 #define AC97_VENDOR_ID2 0x7E 261 #endif 262 263 #define RING_BUS_CTRL_A 0x36 264 #define RAC_PME_ENABLE 0x0100 265 #define RAC_SDFS_ENABLE 0x0200 266 #define LAC_PME_ENABLE 0x0400 267 #define LAC_SDFS_ENABLE 0x0800 268 #define SERIAL_AC_LINK_ENABLE 0x1000 269 #define IO_SRAM_ENABLE 0x2000 270 #define IIS_INPUT_ENABLE 0x8000 271 272 #define RING_BUS_CTRL_B 0x38 273 #define SECOND_CODEC_ID_MASK 0x0003 274 #define SPDIF_FUNC_ENABLE 0x0010 275 #define SECOND_AC_ENABLE 0x0020 276 #define SB_MODULE_INTF_ENABLE 0x0040 277 #define SSPE_ENABLE 0x0040 278 #define M3I_DOCK_ENABLE 0x0080 279 280 #define SDO_OUT_DEST_CTRL 0x3A 281 #define COMMAND_ADDR_OUT 0x0003 282 #define PCM_LR_OUT_LOCAL 0x0000 283 #define PCM_LR_OUT_REMOTE 0x0004 284 #define PCM_LR_OUT_MUTE 0x0008 285 #define PCM_LR_OUT_BOTH 0x000C 286 #define LINE1_DAC_OUT_LOCAL 0x0000 287 #define LINE1_DAC_OUT_REMOTE 0x0010 288 #define LINE1_DAC_OUT_MUTE 0x0020 289 #define LINE1_DAC_OUT_BOTH 0x0030 290 #define PCM_CLS_OUT_LOCAL 0x0000 291 #define PCM_CLS_OUT_REMOTE 0x0040 292 #define PCM_CLS_OUT_MUTE 0x0080 293 #define PCM_CLS_OUT_BOTH 0x00C0 294 #define PCM_RLF_OUT_LOCAL 0x0000 295 #define PCM_RLF_OUT_REMOTE 0x0100 296 #define PCM_RLF_OUT_MUTE 0x0200 297 #define PCM_RLF_OUT_BOTH 0x0300 298 #define LINE2_DAC_OUT_LOCAL 0x0000 299 #define LINE2_DAC_OUT_REMOTE 0x0400 300 #define LINE2_DAC_OUT_MUTE 0x0800 301 #define LINE2_DAC_OUT_BOTH 0x0C00 302 #define HANDSET_OUT_LOCAL 0x0000 303 #define HANDSET_OUT_REMOTE 0x1000 304 #define HANDSET_OUT_MUTE 0x2000 305 #define HANDSET_OUT_BOTH 0x3000 306 #define IO_CTRL_OUT_LOCAL 0x0000 307 #define IO_CTRL_OUT_REMOTE 0x4000 308 #define IO_CTRL_OUT_MUTE 0x8000 309 #define IO_CTRL_OUT_BOTH 0xC000 310 311 #define SDO_IN_DEST_CTRL 0x3C 312 #define STATUS_ADDR_IN 0x0003 313 #define PCM_LR_IN_LOCAL 0x0000 314 #define PCM_LR_IN_REMOTE 0x0004 315 #define PCM_LR_RESERVED 0x0008 316 #define PCM_LR_IN_BOTH 0x000C 317 #define LINE1_ADC_IN_LOCAL 0x0000 318 #define LINE1_ADC_IN_REMOTE 0x0010 319 #define LINE1_ADC_IN_MUTE 0x0020 320 #define MIC_ADC_IN_LOCAL 0x0000 321 #define MIC_ADC_IN_REMOTE 0x0040 322 #define MIC_ADC_IN_MUTE 0x0080 323 #define LINE2_DAC_IN_LOCAL 0x0000 324 #define LINE2_DAC_IN_REMOTE 0x0400 325 #define LINE2_DAC_IN_MUTE 0x0800 326 #define HANDSET_IN_LOCAL 0x0000 327 #define HANDSET_IN_REMOTE 0x1000 328 #define HANDSET_IN_MUTE 0x2000 329 #define IO_STATUS_IN_LOCAL 0x0000 330 #define IO_STATUS_IN_REMOTE 0x4000 331 332 #define SPDIF_IN_CTRL 0x3E 333 #define SPDIF_IN_ENABLE 0x0001 334 335 #define GPIO_DATA 0x60 336 #define GPIO_DATA_MASK 0x0FFF 337 #define GPIO_HV_STATUS 0x3000 338 #define GPIO_PME_STATUS 0x4000 339 340 #define GPIO_MASK 0x64 341 #define GPIO_DIRECTION 0x68 342 #define GPO_PRIMARY_AC97 0x0001 343 #define GPI_LINEOUT_SENSE 0x0004 344 #define GPO_SECONDARY_AC97 0x0008 345 #define GPI_VOL_DOWN 0x0010 346 #define GPI_VOL_UP 0x0020 347 #define GPI_IIS_CLK 0x0040 348 #define GPI_IIS_LRCLK 0x0080 349 #define GPI_IIS_DATA 0x0100 350 #define GPI_DOCKING_STATUS 0x0100 351 #define GPI_HEADPHONE_SENSE 0x0200 352 #define GPO_EXT_AMP_SHUTDOWN 0x1000 353 354 /* M3 */ 355 #define GPO_M3_EXT_AMP_SHUTDN 0x0002 356 357 #define ASSP_INDEX_PORT 0x80 358 #define ASSP_MEMORY_PORT 0x82 359 #define ASSP_DATA_PORT 0x84 360 361 #define MPU401_DATA_PORT 0x98 362 #define MPU401_STATUS_PORT 0x99 363 364 #define CLK_MULT_DATA_PORT 0x9C 365 366 #define ASSP_CONTROL_A 0xA2 367 #define ASSP_0_WS_ENABLE 0x01 368 #define ASSP_CTRL_A_RESERVED1 0x02 369 #define ASSP_CTRL_A_RESERVED2 0x04 370 #define ASSP_CLK_49MHZ_SELECT 0x08 371 #define FAST_PLU_ENABLE 0x10 372 #define ASSP_CTRL_A_RESERVED3 0x20 373 #define DSP_CLK_36MHZ_SELECT 0x40 374 375 #define ASSP_CONTROL_B 0xA4 376 #define RESET_ASSP 0x00 377 #define RUN_ASSP 0x01 378 #define ENABLE_ASSP_CLOCK 0x00 379 #define STOP_ASSP_CLOCK 0x10 380 #define RESET_TOGGLE 0x40 381 382 #define ASSP_CONTROL_C 0xA6 383 #define ASSP_HOST_INT_ENABLE 0x01 384 #define FM_ADDR_REMAP_DISABLE 0x02 385 #define HOST_WRITE_PORT_ENABLE 0x08 386 387 #define ASSP_HOST_INT_STATUS 0xAC 388 #define DSP2HOST_REQ_PIORECORD 0x01 389 #define DSP2HOST_REQ_I2SRATE 0x02 390 #define DSP2HOST_REQ_TIMER 0x04 391 392 /* 393 * DSP memory map 394 */ 395 396 #define REV_A_CODE_MEMORY_BEGIN 0x0000 397 #define REV_A_CODE_MEMORY_END 0x0FFF 398 #define REV_A_CODE_MEMORY_UNIT_LENGTH 0x0040 399 #define REV_A_CODE_MEMORY_LENGTH (REV_A_CODE_MEMORY_END - REV_A_CODE_MEMORY_BEGIN + 1) 400 401 #define REV_B_CODE_MEMORY_BEGIN 0x0000 402 #define REV_B_CODE_MEMORY_END 0x0BFF 403 #define REV_B_CODE_MEMORY_UNIT_LENGTH 0x0040 404 #define REV_B_CODE_MEMORY_LENGTH (REV_B_CODE_MEMORY_END - REV_B_CODE_MEMORY_BEGIN + 1) 405 406 #if (REV_A_CODE_MEMORY_LENGTH % REV_A_CODE_MEMORY_UNIT_LENGTH) 407 #error Assumption about code memory unit length failed. 408 #endif 409 #if (REV_B_CODE_MEMORY_LENGTH % REV_B_CODE_MEMORY_UNIT_LENGTH) 410 #error Assumption about code memory unit length failed. 411 #endif 412 413 #define REV_A_DATA_MEMORY_BEGIN 0x1000 414 #define REV_A_DATA_MEMORY_END 0x2FFF 415 #define REV_A_DATA_MEMORY_UNIT_LENGTH 0x0080 416 #define REV_A_DATA_MEMORY_LENGTH (REV_A_DATA_MEMORY_END - REV_A_DATA_MEMORY_BEGIN + 1) 417 418 #define REV_B_DATA_MEMORY_BEGIN 0x1000 419 /*#define REV_B_DATA_MEMORY_END 0x23FF */ 420 #define REV_B_DATA_MEMORY_END 0x2BFF 421 #define REV_B_DATA_MEMORY_UNIT_LENGTH 0x0080 422 #define REV_B_DATA_MEMORY_LENGTH (REV_B_DATA_MEMORY_END - REV_B_DATA_MEMORY_BEGIN + 1) 423 424 #if (REV_A_DATA_MEMORY_LENGTH % REV_A_DATA_MEMORY_UNIT_LENGTH) 425 #error Assumption about data memory unit length failed. 426 #endif 427 #if (REV_B_DATA_MEMORY_LENGTH % REV_B_DATA_MEMORY_UNIT_LENGTH) 428 #error Assumption about data memory unit length failed. 429 #endif 430 431 #define CODE_MEMORY_MAP_LENGTH (64 + 1) 432 #define DATA_MEMORY_MAP_LENGTH (64 + 1) 433 434 #if (CODE_MEMORY_MAP_LENGTH < ((REV_A_CODE_MEMORY_LENGTH / REV_A_CODE_MEMORY_UNIT_LENGTH) + 1)) 435 #error Code memory map length too short. 436 #endif 437 #if (DATA_MEMORY_MAP_LENGTH < ((REV_A_DATA_MEMORY_LENGTH / REV_A_DATA_MEMORY_UNIT_LENGTH) + 1)) 438 #error Data memory map length too short. 439 #endif 440 #if (CODE_MEMORY_MAP_LENGTH < ((REV_B_CODE_MEMORY_LENGTH / REV_B_CODE_MEMORY_UNIT_LENGTH) + 1)) 441 #error Code memory map length too short. 442 #endif 443 #if (DATA_MEMORY_MAP_LENGTH < ((REV_B_DATA_MEMORY_LENGTH / REV_B_DATA_MEMORY_UNIT_LENGTH) + 1)) 444 #error Data memory map length too short. 445 #endif 446 447 /* 448 * Kernel code memory definition 449 */ 450 451 #define KCODE_VECTORS_BEGIN 0x0000 452 #define KCODE_VECTORS_END 0x002F 453 #define KCODE_VECTORS_UNIT_LENGTH 0x0002 454 #define KCODE_VECTORS_LENGTH (KCODE_VECTORS_END - KCODE_VECTORS_BEGIN + 1) 455 456 /* 457 * Kernel data memory definition 458 */ 459 460 #define KDATA_BASE_ADDR 0x1000 461 #define KDATA_BASE_ADDR2 0x1080 462 463 #define KDATA_TASK0 (KDATA_BASE_ADDR + 0x0000) 464 #define KDATA_TASK1 (KDATA_BASE_ADDR + 0x0001) 465 #define KDATA_TASK2 (KDATA_BASE_ADDR + 0x0002) 466 #define KDATA_TASK3 (KDATA_BASE_ADDR + 0x0003) 467 #define KDATA_TASK4 (KDATA_BASE_ADDR + 0x0004) 468 #define KDATA_TASK5 (KDATA_BASE_ADDR + 0x0005) 469 #define KDATA_TASK6 (KDATA_BASE_ADDR + 0x0006) 470 #define KDATA_TASK7 (KDATA_BASE_ADDR + 0x0007) 471 #define KDATA_TASK_ENDMARK (KDATA_BASE_ADDR + 0x0008) 472 473 #define KDATA_CURRENT_TASK (KDATA_BASE_ADDR + 0x0009) 474 #define KDATA_TASK_SWITCH (KDATA_BASE_ADDR + 0x000A) 475 476 #define KDATA_INSTANCE0_POS3D (KDATA_BASE_ADDR + 0x000B) 477 #define KDATA_INSTANCE1_POS3D (KDATA_BASE_ADDR + 0x000C) 478 #define KDATA_INSTANCE2_POS3D (KDATA_BASE_ADDR + 0x000D) 479 #define KDATA_INSTANCE3_POS3D (KDATA_BASE_ADDR + 0x000E) 480 #define KDATA_INSTANCE4_POS3D (KDATA_BASE_ADDR + 0x000F) 481 #define KDATA_INSTANCE5_POS3D (KDATA_BASE_ADDR + 0x0010) 482 #define KDATA_INSTANCE6_POS3D (KDATA_BASE_ADDR + 0x0011) 483 #define KDATA_INSTANCE7_POS3D (KDATA_BASE_ADDR + 0x0012) 484 #define KDATA_INSTANCE8_POS3D (KDATA_BASE_ADDR + 0x0013) 485 #define KDATA_INSTANCE_POS3D_ENDMARK (KDATA_BASE_ADDR + 0x0014) 486 487 #define KDATA_INSTANCE0_SPKVIRT (KDATA_BASE_ADDR + 0x0015) 488 #define KDATA_INSTANCE_SPKVIRT_ENDMARK (KDATA_BASE_ADDR + 0x0016) 489 490 #define KDATA_INSTANCE0_SPDIF (KDATA_BASE_ADDR + 0x0017) 491 #define KDATA_INSTANCE_SPDIF_ENDMARK (KDATA_BASE_ADDR + 0x0018) 492 493 #define KDATA_INSTANCE0_MODEM (KDATA_BASE_ADDR + 0x0019) 494 #define KDATA_INSTANCE_MODEM_ENDMARK (KDATA_BASE_ADDR + 0x001A) 495 496 #define KDATA_INSTANCE0_SRC (KDATA_BASE_ADDR + 0x001B) 497 #define KDATA_INSTANCE1_SRC (KDATA_BASE_ADDR + 0x001C) 498 #define KDATA_INSTANCE_SRC_ENDMARK (KDATA_BASE_ADDR + 0x001D) 499 500 #define KDATA_INSTANCE0_MINISRC (KDATA_BASE_ADDR + 0x001E) 501 #define KDATA_INSTANCE1_MINISRC (KDATA_BASE_ADDR + 0x001F) 502 #define KDATA_INSTANCE2_MINISRC (KDATA_BASE_ADDR + 0x0020) 503 #define KDATA_INSTANCE3_MINISRC (KDATA_BASE_ADDR + 0x0021) 504 #define KDATA_INSTANCE_MINISRC_ENDMARK (KDATA_BASE_ADDR + 0x0022) 505 506 #define KDATA_INSTANCE0_CPYTHRU (KDATA_BASE_ADDR + 0x0023) 507 #define KDATA_INSTANCE1_CPYTHRU (KDATA_BASE_ADDR + 0x0024) 508 #define KDATA_INSTANCE_CPYTHRU_ENDMARK (KDATA_BASE_ADDR + 0x0025) 509 510 #define KDATA_CURRENT_DMA (KDATA_BASE_ADDR + 0x0026) 511 #define KDATA_DMA_SWITCH (KDATA_BASE_ADDR + 0x0027) 512 #define KDATA_DMA_ACTIVE (KDATA_BASE_ADDR + 0x0028) 513 514 #define KDATA_DMA_XFER0 (KDATA_BASE_ADDR + 0x0029) 515 #define KDATA_DMA_XFER1 (KDATA_BASE_ADDR + 0x002A) 516 #define KDATA_DMA_XFER2 (KDATA_BASE_ADDR + 0x002B) 517 #define KDATA_DMA_XFER3 (KDATA_BASE_ADDR + 0x002C) 518 #define KDATA_DMA_XFER4 (KDATA_BASE_ADDR + 0x002D) 519 #define KDATA_DMA_XFER5 (KDATA_BASE_ADDR + 0x002E) 520 #define KDATA_DMA_XFER6 (KDATA_BASE_ADDR + 0x002F) 521 #define KDATA_DMA_XFER7 (KDATA_BASE_ADDR + 0x0030) 522 #define KDATA_DMA_XFER8 (KDATA_BASE_ADDR + 0x0031) 523 #define KDATA_DMA_XFER_ENDMARK (KDATA_BASE_ADDR + 0x0032) 524 525 #define KDATA_I2S_SAMPLE_COUNT (KDATA_BASE_ADDR + 0x0033) 526 #define KDATA_I2S_INT_METER (KDATA_BASE_ADDR + 0x0034) 527 #define KDATA_I2S_ACTIVE (KDATA_BASE_ADDR + 0x0035) 528 529 #define KDATA_TIMER_COUNT_RELOAD (KDATA_BASE_ADDR + 0x0036) 530 #define KDATA_TIMER_COUNT_CURRENT (KDATA_BASE_ADDR + 0x0037) 531 532 #define KDATA_HALT_SYNCH_CLIENT (KDATA_BASE_ADDR + 0x0038) 533 #define KDATA_HALT_SYNCH_DMA (KDATA_BASE_ADDR + 0x0039) 534 #define KDATA_HALT_ACKNOWLEDGE (KDATA_BASE_ADDR + 0x003A) 535 536 #define KDATA_ADC1_XFER0 (KDATA_BASE_ADDR + 0x003B) 537 #define KDATA_ADC1_XFER_ENDMARK (KDATA_BASE_ADDR + 0x003C) 538 #define KDATA_ADC1_LEFT_VOLUME (KDATA_BASE_ADDR + 0x003D) 539 #define KDATA_ADC1_RIGHT_VOLUME (KDATA_BASE_ADDR + 0x003E) 540 #define KDATA_ADC1_LEFT_SUR_VOL (KDATA_BASE_ADDR + 0x003F) 541 #define KDATA_ADC1_RIGHT_SUR_VOL (KDATA_BASE_ADDR + 0x0040) 542 543 #define KDATA_ADC2_XFER0 (KDATA_BASE_ADDR + 0x0041) 544 #define KDATA_ADC2_XFER_ENDMARK (KDATA_BASE_ADDR + 0x0042) 545 #define KDATA_ADC2_LEFT_VOLUME (KDATA_BASE_ADDR + 0x0043) 546 #define KDATA_ADC2_RIGHT_VOLUME (KDATA_BASE_ADDR + 0x0044) 547 #define KDATA_ADC2_LEFT_SUR_VOL (KDATA_BASE_ADDR + 0x0045) 548 #define KDATA_ADC2_RIGHT_SUR_VOL (KDATA_BASE_ADDR + 0x0046) 549 550 #define KDATA_CD_XFER0 (KDATA_BASE_ADDR + 0x0047) 551 #define KDATA_CD_XFER_ENDMARK (KDATA_BASE_ADDR + 0x0048) 552 #define KDATA_CD_LEFT_VOLUME (KDATA_BASE_ADDR + 0x0049) 553 #define KDATA_CD_RIGHT_VOLUME (KDATA_BASE_ADDR + 0x004A) 554 #define KDATA_CD_LEFT_SUR_VOL (KDATA_BASE_ADDR + 0x004B) 555 #define KDATA_CD_RIGHT_SUR_VOL (KDATA_BASE_ADDR + 0x004C) 556 557 #define KDATA_MIC_XFER0 (KDATA_BASE_ADDR + 0x004D) 558 #define KDATA_MIC_XFER_ENDMARK (KDATA_BASE_ADDR + 0x004E) 559 #define KDATA_MIC_VOLUME (KDATA_BASE_ADDR + 0x004F) 560 #define KDATA_MIC_SUR_VOL (KDATA_BASE_ADDR + 0x0050) 561 562 #define KDATA_I2S_XFER0 (KDATA_BASE_ADDR + 0x0051) 563 #define KDATA_I2S_XFER_ENDMARK (KDATA_BASE_ADDR + 0x0052) 564 565 #define KDATA_CHI_XFER0 (KDATA_BASE_ADDR + 0x0053) 566 #define KDATA_CHI_XFER_ENDMARK (KDATA_BASE_ADDR + 0x0054) 567 568 #define KDATA_SPDIF_XFER (KDATA_BASE_ADDR + 0x0055) 569 #define KDATA_SPDIF_CURRENT_FRAME (KDATA_BASE_ADDR + 0x0056) 570 #define KDATA_SPDIF_FRAME0 (KDATA_BASE_ADDR + 0x0057) 571 #define KDATA_SPDIF_FRAME1 (KDATA_BASE_ADDR + 0x0058) 572 #define KDATA_SPDIF_FRAME2 (KDATA_BASE_ADDR + 0x0059) 573 574 #define KDATA_SPDIF_REQUEST (KDATA_BASE_ADDR + 0x005A) 575 #define KDATA_SPDIF_TEMP (KDATA_BASE_ADDR + 0x005B) 576 577 /*AY SPDIF IN */ 578 #define KDATA_SPDIFIN_XFER0 (KDATA_BASE_ADDR + 0x005C) 579 #define KDATA_SPDIFIN_XFER_ENDMARK (KDATA_BASE_ADDR + 0x005D) 580 #define KDATA_SPDIFIN_INT_METER (KDATA_BASE_ADDR + 0x005E) 581 582 #define KDATA_DSP_RESET_COUNT (KDATA_BASE_ADDR + 0x005F) 583 #define KDATA_DEBUG_OUTPUT (KDATA_BASE_ADDR + 0x0060) 584 585 #define KDATA_KERNEL_ISR_LIST (KDATA_BASE_ADDR + 0x0061) 586 587 #define KDATA_KERNEL_ISR_CBSR1 (KDATA_BASE_ADDR + 0x0062) 588 #define KDATA_KERNEL_ISR_CBER1 (KDATA_BASE_ADDR + 0x0063) 589 #define KDATA_KERNEL_ISR_CBCR (KDATA_BASE_ADDR + 0x0064) 590 #define KDATA_KERNEL_ISR_AR0 (KDATA_BASE_ADDR + 0x0065) 591 #define KDATA_KERNEL_ISR_AR1 (KDATA_BASE_ADDR + 0x0066) 592 #define KDATA_KERNEL_ISR_AR2 (KDATA_BASE_ADDR + 0x0067) 593 #define KDATA_KERNEL_ISR_AR3 (KDATA_BASE_ADDR + 0x0068) 594 #define KDATA_KERNEL_ISR_AR4 (KDATA_BASE_ADDR + 0x0069) 595 #define KDATA_KERNEL_ISR_AR5 (KDATA_BASE_ADDR + 0x006A) 596 #define KDATA_KERNEL_ISR_BRCR (KDATA_BASE_ADDR + 0x006B) 597 #define KDATA_KERNEL_ISR_PASR (KDATA_BASE_ADDR + 0x006C) 598 #define KDATA_KERNEL_ISR_PAER (KDATA_BASE_ADDR + 0x006D) 599 600 #define KDATA_CLIENT_SCRATCH0 (KDATA_BASE_ADDR + 0x006E) 601 #define KDATA_CLIENT_SCRATCH1 (KDATA_BASE_ADDR + 0x006F) 602 #define KDATA_KERNEL_SCRATCH (KDATA_BASE_ADDR + 0x0070) 603 #define KDATA_KERNEL_ISR_SCRATCH (KDATA_BASE_ADDR + 0x0071) 604 605 #define KDATA_OUEUE_LEFT (KDATA_BASE_ADDR + 0x0072) 606 #define KDATA_QUEUE_RIGHT (KDATA_BASE_ADDR + 0x0073) 607 608 #define KDATA_ADC1_REQUEST (KDATA_BASE_ADDR + 0x0074) 609 #define KDATA_ADC2_REQUEST (KDATA_BASE_ADDR + 0x0075) 610 #define KDATA_CD_REQUEST (KDATA_BASE_ADDR + 0x0076) 611 #define KDATA_MIC_REQUEST (KDATA_BASE_ADDR + 0x0077) 612 613 #define KDATA_ADC1_MIXER_REQUEST (KDATA_BASE_ADDR + 0x0078) 614 #define KDATA_ADC2_MIXER_REQUEST (KDATA_BASE_ADDR + 0x0079) 615 #define KDATA_CD_MIXER_REQUEST (KDATA_BASE_ADDR + 0x007A) 616 #define KDATA_MIC_MIXER_REQUEST (KDATA_BASE_ADDR + 0x007B) 617 #define KDATA_MIC_SYNC_COUNTER (KDATA_BASE_ADDR + 0x007C) 618 619 /* 620 * second segment 621 */ 622 623 /* smart mixer buffer */ 624 625 #define KDATA_MIXER_WORD0 (KDATA_BASE_ADDR2 + 0x0000) 626 #define KDATA_MIXER_WORD1 (KDATA_BASE_ADDR2 + 0x0001) 627 #define KDATA_MIXER_WORD2 (KDATA_BASE_ADDR2 + 0x0002) 628 #define KDATA_MIXER_WORD3 (KDATA_BASE_ADDR2 + 0x0003) 629 #define KDATA_MIXER_WORD4 (KDATA_BASE_ADDR2 + 0x0004) 630 #define KDATA_MIXER_WORD5 (KDATA_BASE_ADDR2 + 0x0005) 631 #define KDATA_MIXER_WORD6 (KDATA_BASE_ADDR2 + 0x0006) 632 #define KDATA_MIXER_WORD7 (KDATA_BASE_ADDR2 + 0x0007) 633 #define KDATA_MIXER_WORD8 (KDATA_BASE_ADDR2 + 0x0008) 634 #define KDATA_MIXER_WORD9 (KDATA_BASE_ADDR2 + 0x0009) 635 #define KDATA_MIXER_WORDA (KDATA_BASE_ADDR2 + 0x000A) 636 #define KDATA_MIXER_WORDB (KDATA_BASE_ADDR2 + 0x000B) 637 #define KDATA_MIXER_WORDC (KDATA_BASE_ADDR2 + 0x000C) 638 #define KDATA_MIXER_WORDD (KDATA_BASE_ADDR2 + 0x000D) 639 #define KDATA_MIXER_WORDE (KDATA_BASE_ADDR2 + 0x000E) 640 #define KDATA_MIXER_WORDF (KDATA_BASE_ADDR2 + 0x000F) 641 642 #define KDATA_MIXER_XFER0 (KDATA_BASE_ADDR2 + 0x0010) 643 #define KDATA_MIXER_XFER1 (KDATA_BASE_ADDR2 + 0x0011) 644 #define KDATA_MIXER_XFER2 (KDATA_BASE_ADDR2 + 0x0012) 645 #define KDATA_MIXER_XFER3 (KDATA_BASE_ADDR2 + 0x0013) 646 #define KDATA_MIXER_XFER4 (KDATA_BASE_ADDR2 + 0x0014) 647 #define KDATA_MIXER_XFER5 (KDATA_BASE_ADDR2 + 0x0015) 648 #define KDATA_MIXER_XFER6 (KDATA_BASE_ADDR2 + 0x0016) 649 #define KDATA_MIXER_XFER7 (KDATA_BASE_ADDR2 + 0x0017) 650 #define KDATA_MIXER_XFER8 (KDATA_BASE_ADDR2 + 0x0018) 651 #define KDATA_MIXER_XFER9 (KDATA_BASE_ADDR2 + 0x0019) 652 #define KDATA_MIXER_XFER_ENDMARK (KDATA_BASE_ADDR2 + 0x001A) 653 654 #define KDATA_MIXER_TASK_NUMBER (KDATA_BASE_ADDR2 + 0x001B) 655 #define KDATA_CURRENT_MIXER (KDATA_BASE_ADDR2 + 0x001C) 656 #define KDATA_MIXER_ACTIVE (KDATA_BASE_ADDR2 + 0x001D) 657 #define KDATA_MIXER_BANK_STATUS (KDATA_BASE_ADDR2 + 0x001E) 658 #define KDATA_DAC_LEFT_VOLUME (KDATA_BASE_ADDR2 + 0x001F) 659 #define KDATA_DAC_RIGHT_VOLUME (KDATA_BASE_ADDR2 + 0x0020) 660 661 /* 662 * Client data memory definition 663 */ 664 665 #define CDATA_INSTANCE_READY 0x00 666 667 #define CDATA_HOST_SRC_ADDRL 0x01 668 #define CDATA_HOST_SRC_ADDRH 0x02 669 #define CDATA_HOST_SRC_END_PLUS_1L 0x03 670 #define CDATA_HOST_SRC_END_PLUS_1H 0x04 671 #define CDATA_HOST_SRC_CURRENTL 0x05 672 #define CDATA_HOST_SRC_CURRENTH 0x06 673 674 #define CDATA_IN_BUF_CONNECT 0x07 675 #define CDATA_OUT_BUF_CONNECT 0x08 676 677 #define CDATA_IN_BUF_BEGIN 0x09 678 #define CDATA_IN_BUF_END_PLUS_1 0x0A 679 #define CDATA_IN_BUF_HEAD 0x0B 680 #define CDATA_IN_BUF_TAIL 0x0C 681 682 #define CDATA_OUT_BUF_BEGIN 0x0D 683 #define CDATA_OUT_BUF_END_PLUS_1 0x0E 684 #define CDATA_OUT_BUF_HEAD 0x0F 685 #define CDATA_OUT_BUF_TAIL 0x10 686 687 #define CDATA_DMA_CONTROL 0x11 688 #define CDATA_RESERVED 0x12 689 690 #define CDATA_FREQUENCY 0x13 691 #define CDATA_LEFT_VOLUME 0x14 692 #define CDATA_RIGHT_VOLUME 0x15 693 #define CDATA_LEFT_SUR_VOL 0x16 694 #define CDATA_RIGHT_SUR_VOL 0x17 695 696 /* These are from Allegro hckernel.h */ 697 #define CDATA_HEADER_LEN 0x18 698 #define SRC3_DIRECTION_OFFSET CDATA_HEADER_LEN 699 #define SRC3_MODE_OFFSET CDATA_HEADER_LEN + 1 700 #define SRC3_WORD_LENGTH_OFFSET CDATA_HEADER_LEN + 2 701 #define SRC3_PARAMETER_OFFSET CDATA_HEADER_LEN + 3 702 #define SRC3_COEFF_ADDR_OFFSET CDATA_HEADER_LEN + 8 703 #define SRC3_FILTAP_ADDR_OFFSET CDATA_HEADER_LEN + 10 704 #define SRC3_TEMP_INBUF_ADDR_OFFSET CDATA_HEADER_LEN + 16 705 #define SRC3_TEMP_OUTBUF_ADDR_OFFSET CDATA_HEADER_LEN + 17 706 #define FOR_FUTURE_USE 10 /* for storing temporary variable in future */ 707 708 /* 709 * DMA control definition 710 */ 711 712 #define DMACONTROL_BLOCK_MASK 0x000F 713 #define DMAC_BLOCK0_SELECTOR 0x0000 714 #define DMAC_BLOCK1_SELECTOR 0x0001 715 #define DMAC_BLOCK2_SELECTOR 0x0002 716 #define DMAC_BLOCK3_SELECTOR 0x0003 717 #define DMAC_BLOCK4_SELECTOR 0x0004 718 #define DMAC_BLOCK5_SELECTOR 0x0005 719 #define DMAC_BLOCK6_SELECTOR 0x0006 720 #define DMAC_BLOCK7_SELECTOR 0x0007 721 #define DMAC_BLOCK8_SELECTOR 0x0008 722 #define DMAC_BLOCK9_SELECTOR 0x0009 723 #define DMAC_BLOCKA_SELECTOR 0x000A 724 #define DMAC_BLOCKB_SELECTOR 0x000B 725 #define DMAC_BLOCKC_SELECTOR 0x000C 726 #define DMAC_BLOCKD_SELECTOR 0x000D 727 #define DMAC_BLOCKE_SELECTOR 0x000E 728 #define DMAC_BLOCKF_SELECTOR 0x000F 729 #define DMACONTROL_PAGE_MASK 0x00F0 730 #define DMAC_PAGE0_SELECTOR 0x0030 731 #define DMAC_PAGE1_SELECTOR 0x0020 732 #define DMAC_PAGE2_SELECTOR 0x0010 733 #define DMAC_PAGE3_SELECTOR 0x0000 734 #define DMACONTROL_AUTOREPEAT 0x1000 735 #define DMACONTROL_STOPPED 0x2000 736 #define DMACONTROL_DIRECTION 0x0100 737 738 /* 739 * Kernel/client memory allocation 740 */ 741 742 #define NUM_UNITS_KERNEL_CODE 16 743 #define NUM_UNITS_KERNEL_DATA 2 744 745 #define NUM_UNITS_KERNEL_CODE_WITH_HSP 16 746 #ifdef M3_MODEL 747 #define NUM_UNITS_KERNEL_DATA_WITH_HSP 5 748 #else 749 #define NUM_UNITS_KERNEL_DATA_WITH_HSP 4 750 #endif 751 752 #define NUM_UNITS( BYTES, UNITLEN ) ((((BYTES+1)>>1) + (UNITLEN-1)) / UNITLEN) 753 754 /* 755 * DSP hardware 756 */ 757 758 #define DSP_PORT_TIMER_COUNT 0x06 759 #define DSP_PORT_MEMORY_INDEX 0x80 760 #define DSP_PORT_MEMORY_TYPE 0x82 761 #define DSP_PORT_MEMORY_DATA 0x84 762 #define DSP_PORT_CONTROL_REG_A 0xA2 763 #define DSP_PORT_CONTROL_REG_B 0xA4 764 #define DSP_PORT_CONTROL_REG_C 0xA6 765 766 #define MEMTYPE_INTERNAL_CODE 0x0002 767 #define MEMTYPE_INTERNAL_DATA 0x0003 768 #define MEMTYPE_MASK 0x0003 769 770 #define REGB_ENABLE_RESET 0x01 771 #define REGB_STOP_CLOCK 0x10 772 773 #define REGC_DISABLE_FM_MAPPING 0x02 774 775 #define DP_SHIFT_COUNT 7 776 777 #define DMA_BLOCK_LENGTH 32 778 779 /* These are from Allegro srcmgr.h */ 780 #define MINISRC_BIQUAD_STAGE 2 781 #define MINISRC_IN_BUFFER_SIZE ( 0x50 * 2 ) 782 #define MINISRC_OUT_BUFFER_SIZE ( 0x50 * 2 * 2) 783 #define MINISRC_TMP_BUFFER_SIZE ( 112 + ( MINISRC_BIQUAD_STAGE * 3 + 4 ) * 2 * 2 ) 784 #define MINISRC_BIQUAD_STAGE 2 785 /* M. SRC LPF coefficient could be changed in the DSP code */ 786 #define MINISRC_COEF_LOC 0X175 787 788 #endif /* !_DEV_SOUND_PCI_ALLEGRO_REG_H */ 789