| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | ISDOpcodes.h | 692 ABDU, enumerator
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| H A D | TargetLowering.h | 2915 case ISD::ABDU: in isCommutativeBinOp()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAGDumper.cpp | 266 case ISD::ABDU: return "abdu"; in getOperationName()
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| H A D | LegalizeVectorOps.cpp | 371 case ISD::ABDU: in LegalizeOp()
928 case ISD::ABDU: in Expand()
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| H A D | DAGCombiner.cpp | 1873 case ISD::ABDU: return visitABD(N); in visit()
4124 if (hasOperation(ISD::ABDU, VT) && in visitSUB()
4127 return DAG.getNode(ISD::ABDU, DL, VT, A, B); in visitSUB()
5298 if (sd_match(N, m_c_BinOp(ISD::ABDU, m_Value(X), m_Zero()))) in visitABD()
5302 if (Opcode == ISD::ABDS && hasOperation(ISD::ABDU, VT) && in visitABD()
5304 return DAG.getNode(ISD::ABDU, DL, VT, N1, N0); in visitABD()
10967 unsigned ABDOpcode = (Opc0 == ISD::ZERO_EXTEND) ? ISD::ABDU : ISD::ABDS; in foldABSToABD()
12404 unsigned ABDOpc = IsSigned ? ISD::ABDS : ISD::ABDU; in visitVSELECT()
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| H A D | SelectionDAG.cpp | 3472 case ISD::ABDU: { in computeKnownBits()
6302 case ISD::ABDU: in FoldValue()
7013 case ISD::ABDU: in getNode()
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| H A D | LegalizeDAG.cpp | 3066 case ISD::ABDU: in ExpandNode()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | TargetLoweringBase.cpp | 754 setOperationAction({ISD::ABDS, ISD::ABDU}, VT, Expand); in initActions()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 1288 setOperationAction(ISD::ABDU, VT, Legal); in AArch64TargetLowering()
1460 setOperationAction(ISD::ABDU, VT, Custom); in AArch64TargetLowering()
7014 case ISD::ABDU: in LowerOperation()
17694 SDValue UABDHigh8 = DAG.getNode(IsZExt ? ISD::ABDU : ISD::ABDS, DL, MVT::v8i8, in performVecReduceAddCombineWithUADDLP()
17705 SDValue UABDLo8 = DAG.getNode(IsZExt ? ISD::ABDU : ISD::ABDS, DL, MVT::v8i8, in performVecReduceAddCombineWithUADDLP()
21296 return DAG.getNode(ISD::ABDU, SDLoc(N), N->getValueType(0), in performIntrinsicCombine()
21417 return DAG.getNode(ISD::ABDU, SDLoc(N), N->getValueType(0), in performIntrinsicCombine()
21595 (N->getOperand(0).getOpcode() == ISD::ABDU || in performExtendCombine()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/Target/ |
| H A D | TargetSelectionDAG.td | 408 def abdu : SDNode<"ISD::ABDU" , SDTIntBinOp, [SDNPCommutative]>;
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| /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.cpp | 1328 setOperationAction(ISD::ABDU, MVT::v16i8, Legal); in PPCTargetLowering()
1329 setOperationAction(ISD::ABDU, MVT::v8i16, Legal); in PPCTargetLowering()
1330 setOperationAction(ISD::ABDU, MVT::v4i32, Legal); in PPCTargetLowering()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 832 setOperationAction({ISD::ABDS, ISD::ABDU}, VT, Custom); in RISCVTargetLowering()
1242 setOperationAction({ISD::ABDS, ISD::ABDU}, VT, Custom); in RISCVTargetLowering()
7047 case ISD::ABDU: { in LowerOperation()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 220 for (auto Opcode : {ISD::ABS, ISD::ABDS, ISD::ABDU, ISD::SMIN, ISD::SMAX, in addTypeForNEON()
287 setOperationAction(ISD::ABDU, VT, Legal); in addMVEVectorTypes()
4205 return DAG.getNode(ISD::ABDU, SDLoc(Op), Op.getValueType(), in LowerINTRINSIC_WO_CHAIN()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 230 for (auto Op : {ISD::ABDS, ISD::ABDU}) { in X86TargetLowering()
1154 setOperationAction(ISD::ABDU, VT, Custom); in X86TargetLowering()
1497 setOperationAction(ISD::ABDU, VT, Custom); in X86TargetLowering()
1929 setOperationAction(ISD::ABDU, VT, Custom); in X86TargetLowering()
32492 case ISD::ABDU: return LowerABD(Op, Subtarget, DAG); in LowerOperation()
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