| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | ISDOpcodes.h | 713 ABDS, enumerator
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| H A D | TargetLowering.h | 3000 case ISD::ABDS: in isCommutativeBinOp()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAGDumper.cpp | 282 case ISD::ABDS: return "abds"; in getOperationName()
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| H A D | LegalizeVectorOps.cpp | 381 case ISD::ABDS: in LegalizeOp()
1051 case ISD::ABDS: in Expand()
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| H A D | DAGCombiner.cpp | 1930 case ISD::ABDS: in visit()
4422 if ((!LegalOperations || hasOperation(ISD::ABDS, VT)) && in visitSUB()
4425 return DAG.getNode(ISD::ABDS, DL, VT, A, B); in visitSUB()
4428 if (hasOperation(ISD::ABDS, VT) && in visitSUB()
4431 return DAG.getNegative(DAG.getNode(ISD::ABDS, DL, VT, A, B), DL, VT); in visitSUB()
5668 if (sd_match(N, m_c_BinOp(ISD::ABDS, m_Value(X), m_Zero())) && in visitABD()
5677 if (Opcode == ISD::ABDS && hasOperation(ISD::ABDU, VT) && in visitABD()
11413 if (hasOperation(ISD::ABDS, VT) && TLI.preferABDSToABSWithNSW(VT) && in foldABSToABD()
11416 SDValue ABD = DAG.getNode(ISD::ABDS, DL, VT, Op0, Op1); in foldABSToABD()
11436 unsigned ABDOpcode = (Opc0 == ISD::ZERO_EXTEND) ? ISD::ABDU : ISD::ABDS; in foldABSToABD()
[all …]
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| H A D | LegalizeVectorTypes.cpp | 163 case ISD::ABDS: in ScalarizeVectorResult()
1294 case ISD::ABDS: in SplitVectorResult()
4739 case ISD::ABDS: in WidenVectorResult()
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| H A D | LegalizeIntegerTypes.cpp | 213 case ISD::ABDS: in PromoteIntegerResult()
2972 case ISD::ABDS: in ExpandIntegerResult()
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| H A D | SelectionDAG.cpp | 3721 case ISD::ABDS: { in computeKnownBits()
6714 case ISD::ABDS: in FoldValue()
7557 case ISD::ABDS: in getNode()
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| H A D | LegalizeDAG.cpp | 3095 case ISD::ABDS: in ExpandNode()
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| H A D | TargetLowering.cpp | 9705 bool IsSigned = N->getOpcode() == ISD::ABDS; in expandABD()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | TargetLoweringBase.cpp | 845 setOperationAction({ISD::ABDS, ISD::ABDU}, VT, Expand); in initActions()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 1339 setOperationAction(ISD::ABDS, VT, Legal); in AArch64TargetLowering()
1551 setOperationAction(ISD::ABDS, VT, Custom); in AArch64TargetLowering()
2270 setOperationAction(ISD::ABDS, VT, Default); in addTypeForFixedLengthSVE()
7484 case ISD::ABDS: in LowerOperation()
18165 SDValue UABDHigh8 = DAG.getNode(IsZExt ? ISD::ABDU : ISD::ABDS, DL, MVT::v8i8, in performVecReduceAddCombineWithUADDLP()
18176 SDValue UABDLo8 = DAG.getNode(IsZExt ? ISD::ABDU : ISD::ABDS, DL, MVT::v8i8, in performVecReduceAddCombineWithUADDLP()
22142 return DAG.getNode(ISD::ABDS, SDLoc(N), N->getValueType(0), in performIntrinsicCombine()
22275 return DAG.getNode(ISD::ABDS, SDLoc(N), N->getValueType(0), in performIntrinsicCombine()
22584 N->getOperand(0).getOpcode() == ISD::ABDS)) { in performExtendCombine()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/Target/ |
| H A D | TargetSelectionDAG.td | 420 def abds : SDNode<"ISD::ABDS" , SDTIntBinOp, [SDNPCommutative]>;
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| /freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/ |
| H A D | LoongArchISelLowering.cpp | 310 setOperationAction(ISD::ABDS, VT, Legal); in LoongArchTargetLowering()
377 setOperationAction(ISD::ABDS, VT, Legal); in LoongArchTargetLowering()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 880 setOperationAction({ISD::ABDS, ISD::ABDU}, VT, Custom); in RISCVTargetLowering()
1361 setOperationAction({ISD::ABDS, ISD::ABDU}, VT, Custom); in RISCVTargetLowering()
8157 case ISD::ABDS: in LowerOperation()
8163 bool IsSigned = Op->getOpcode() == ISD::ABDS; in LowerOperation()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 225 for (auto Opcode : {ISD::ABS, ISD::ABDS, ISD::ABDU, ISD::SMIN, ISD::SMAX, in addTypeForNEON()
291 setOperationAction(ISD::ABDS, VT, Legal); in addMVEVectorTypes()
4271 return DAG.getNode(ISD::ABDS, SDLoc(Op), Op.getValueType(), in LowerINTRINSIC_WO_CHAIN()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 215 for (auto Op : {ISD::ABDS, ISD::ABDU}) { in X86TargetLowering()
1174 setOperationAction(ISD::ABDS, VT, Custom); in X86TargetLowering()
1520 setOperationAction(ISD::ABDS, VT, Custom); in X86TargetLowering()
1960 setOperationAction(ISD::ABDS, VT, Custom); in X86TargetLowering()
29479 bool IsSigned = Op.getOpcode() == ISD::ABDS; in LowerABD()
33718 case ISD::ABDS: in LowerOperation()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.cpp | 1349 setOperationAction(ISD::ABDS, MVT::v4i32, Legal); in PPCTargetLowering()
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