| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | ISDOpcodes.h | 691 ABDS, enumerator
|
| H A D | TargetLowering.h | 2914 case ISD::ABDS: in isCommutativeBinOp()
|
| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAGDumper.cpp | 265 case ISD::ABDS: return "abds"; in getOperationName()
|
| H A D | LegalizeVectorOps.cpp | 370 case ISD::ABDS: in LegalizeOp()
927 case ISD::ABDS: in Expand()
|
| H A D | DAGCombiner.cpp | 1872 case ISD::ABDS: in visit()
4118 if (hasOperation(ISD::ABDS, VT) && in visitSUB()
4121 return DAG.getNode(ISD::ABDS, DL, VT, A, B); in visitSUB()
5293 if (sd_match(N, m_c_BinOp(ISD::ABDS, m_Value(X), m_Zero())) && in visitABD()
5302 if (Opcode == ISD::ABDS && hasOperation(ISD::ABDU, VT) && in visitABD()
10951 if (AbsOp1->getFlags().hasNoSignedWrap() && hasOperation(ISD::ABDS, VT) && in foldABSToABD()
10953 SDValue ABD = DAG.getNode(ISD::ABDS, DL, VT, Op0, Op1); in foldABSToABD()
10967 unsigned ABDOpcode = (Opc0 == ISD::ZERO_EXTEND) ? ISD::ABDU : ISD::ABDS; in foldABSToABD()
12404 unsigned ABDOpc = IsSigned ? ISD::ABDS : ISD::ABDU; in visitVSELECT()
|
| H A D | SelectionDAG.cpp | 3478 case ISD::ABDS: { in computeKnownBits()
6300 case ISD::ABDS: in FoldValue()
7012 case ISD::ABDS: in getNode()
|
| H A D | LegalizeDAG.cpp | 3065 case ISD::ABDS: in ExpandNode()
|
| H A D | TargetLowering.cpp | 9262 bool IsSigned = N->getOpcode() == ISD::ABDS; in expandABD()
|
| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | TargetLoweringBase.cpp | 754 setOperationAction({ISD::ABDS, ISD::ABDU}, VT, Expand); in initActions()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 1287 setOperationAction(ISD::ABDS, VT, Legal); in AArch64TargetLowering()
1459 setOperationAction(ISD::ABDS, VT, Custom); in AArch64TargetLowering()
7012 case ISD::ABDS: in LowerOperation()
17694 SDValue UABDHigh8 = DAG.getNode(IsZExt ? ISD::ABDU : ISD::ABDS, DL, MVT::v8i8, in performVecReduceAddCombineWithUADDLP()
17705 SDValue UABDLo8 = DAG.getNode(IsZExt ? ISD::ABDU : ISD::ABDS, DL, MVT::v8i8, in performVecReduceAddCombineWithUADDLP()
21293 return DAG.getNode(ISD::ABDS, SDLoc(N), N->getValueType(0), in performIntrinsicCombine()
21414 return DAG.getNode(ISD::ABDS, SDLoc(N), N->getValueType(0), in performIntrinsicCombine()
21596 N->getOperand(0).getOpcode() == ISD::ABDS)) { in performExtendCombine()
|
| /freebsd/contrib/llvm-project/llvm/include/llvm/Target/ |
| H A D | TargetSelectionDAG.td | 407 def abds : SDNode<"ISD::ABDS" , SDTIntBinOp, [SDNPCommutative]>;
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 832 setOperationAction({ISD::ABDS, ISD::ABDU}, VT, Custom); in RISCVTargetLowering()
1242 setOperationAction({ISD::ABDS, ISD::ABDU}, VT, Custom); in RISCVTargetLowering()
7046 case ISD::ABDS: in LowerOperation()
7052 bool IsSigned = Op->getOpcode() == ISD::ABDS; in LowerOperation()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 220 for (auto Opcode : {ISD::ABS, ISD::ABDS, ISD::ABDU, ISD::SMIN, ISD::SMAX, in addTypeForNEON()
286 setOperationAction(ISD::ABDS, VT, Legal); in addMVEVectorTypes()
4201 return DAG.getNode(ISD::ABDS, SDLoc(Op), Op.getValueType(), in LowerINTRINSIC_WO_CHAIN()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 230 for (auto Op : {ISD::ABDS, ISD::ABDU}) { in X86TargetLowering()
1153 setOperationAction(ISD::ABDS, VT, Custom); in X86TargetLowering()
1496 setOperationAction(ISD::ABDS, VT, Custom); in X86TargetLowering()
1928 setOperationAction(ISD::ABDS, VT, Custom); in X86TargetLowering()
28433 bool IsSigned = Op.getOpcode() == ISD::ABDS; in LowerABD()
32491 case ISD::ABDS: in LowerOperation()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.cpp | 1331 setOperationAction(ISD::ABDS, MVT::v4i32, Legal); in PPCTargetLowering()
|