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/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCScheduleP10.td12 // Modeling pipeline forwarding logic.
83 // A BF pipeline may take from 7 to 36 cycles to complete.
84 // Some BF operations may keep the pipeline busy for up to 10 cycles.
114 // A BR pipeline may take 2 cycles to complete.
119 // A CY pipeline may take 7 cycles to complete.
124 // A DF pipeline may take from 13 to 174 cycles to complete.
125 // Some DF operations may keep the pipeline busy for up to 67 cycles.
210 // A DV pipeline may take from 20 to 83 cycles to complete.
211 // Some DV operations may keep the pipeline busy for up to 33 cycles.
262 // A DX pipeline ma
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H A DPPCSchedule440.td13 // The basic PPC 440 does not include a floating-point unit; the pipeline
34 // the complex integer (I-pipe) pipeline
36 // the floating-point execution (F-pipe) pipeline
37 def P440_IEXE1 : FuncUnit; // Execution stage 1 for the I pipeline
38 def P440_IEXE2 : FuncUnit; // Execution stage 2 for the I pipeline
39 def P440_IWB : FuncUnit; // Write-back unit for the I pipeline
40 def P440_JEXE1 : FuncUnit; // Execution stage 1 for the J pipeline
41 def P440_JEXE2 : FuncUnit; // Execution stage 2 for the J pipeline
42 def P440_JWB : FuncUnit; // Write-back unit for the J pipeline
43 def P440_AGEN : FuncUnit; // Address generation for the L pipeline
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H A DPPCScheduleP7.td113 // Instruction of BRU pipeline
136 // Instructions of CRU pipeline
240 // Instructions of FPU and VMX pipeline
H A DPPCScheduleP8.td144 // Instructions of CR pipeline
150 // Instructions of CY pipeline
155 // Instructions of FPU pipeline
195 // Instructions of FX, LU or LS pipeline
264 // Instructions of PM pipeline
295 // Instructions of VX pipeline
302 // Instructions of BR pipeline
309 // Instructions of DFP pipeline
H A DPPCScheduleA2.td16 def A2_XU : FuncUnit; // A2_XU pipeline
17 def A2_FU : FuncUnit; // FI pipeline
H A DPPCScheduleE5500.td34 def E5500_CFX_0 : FuncUnit; // CFX pipeline stage 0
36 def E5500_CFX_1 : FuncUnit; // CFX pipeline stage 1
38 def E5500_LSU_0 : FuncUnit; // LSU pipeline
39 def E5500_FPU_0 : FuncUnit; // FPU pipeline
H A DPPCScheduleE500mc.td34 def E500mc_CFX_0 : FuncUnit; // CFX pipeline
35 def E500mc_LSU_0 : FuncUnit; // LSU pipeline
36 def E500mc_FPU_0 : FuncUnit; // FPU pipeline
/freebsd/usr.bin/man/
H A Dman.sh343 local IFS pipeline testline
380 pipeline="mandoc -Tps $mandoc_args"
382 pipeline="mandoc $mandoc_args | $MANPAGER"
398 decho "Command: $cattool \"$manpage\" | eval \"$pipeline\""
401 $cattool "$manpage" | eval "$pipeline"
410 local IFS l nroff_dev pipeline preproc_arg tool
469 e) pipeline="$pipeline | $EQN" ;;
471 p) pipeline="$pipeline | $PIC" ;;
472 r) pipeline="$pipeline | $REFER" ;;
473 t) pipeline="$pipeline | $TBL" ;;
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/freebsd/sbin/hastd/
H A Dhast_proto.c67 static struct hast_pipe_stage pipeline[] = { variable
95 for (ii = 0; ii < sizeof(pipeline) / sizeof(pipeline[0]); in hast_proto_send()
97 (void)pipeline[ii].hps_send(res, nv, &dptr, &size, in hast_proto_send()
197 for (ii = sizeof(pipeline) / sizeof(pipeline[0]); ii > 0; in hast_proto_recv_data()
199 ret = pipeline[ii - 1].hps_recv(res, nv, &dptr, in hast_proto_recv_data()
/freebsd/tools/tools/netrate/juggle/
H A Djuggle.c233 juggle(int fd1, int fd2, int pipeline) in juggle() argument
243 for (j = 0; j < pipeline; j++) { in juggle()
248 for (j = 0; j < pipeline; j++) { in juggle()
256 for (j = 0; j < pipeline; j++) { in juggle()
315 thread_juggle(int fd1, int fd2, int pipeline) in thread_juggle() argument
321 threaded_pipeline = pipeline; in thread_juggle()
344 for (j = 0; j < pipeline; j++) { in thread_juggle()
349 for (j = 0; j < pipeline; j++) { in thread_juggle()
374 process_juggle(int fd1, int fd2, int pipeline) in process_juggle() argument
395 for (j = 0; j < pipeline; j++) { in process_juggle()
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/freebsd/sys/contrib/device-tree/Bindings/display/
H A Darm,komeda.txt18 Required properties for sub-node: pipeline@nq
19 Each device contains one or two pipeline sub-nodes (at least one), each
20 pipeline node should provide properties:
21 - reg: Zero-indexed identifier for the pipeline
27 - port: each pipeline connect to an encoder input port. The connection is
53 dp0_pipe0: pipeline@0 {
65 dp0_pipe1: pipeline@1 {
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMScheduleV6.td16 def V6_Pipe : FuncUnit; // pipeline
87 // Integer multiply pipeline
96 // Integer load pipeline
149 // Integer store pipeline
190 // Issue through integer pipeline, and execute in NEON unit. We assume
191 // RunFast mode so that NFP pipeline is used for single-precision when
H A DARMScheduleA8.td16 def A8_Pipe0 : FuncUnit; // pipeline 0
17 def A8_Pipe1 : FuncUnit; // pipeline 1
18 def A8_LSPipe : FuncUnit; // Load / store pipeline
22 // Dual issue pipeline represented by A8_Pipe0 | A8_Pipe1
94 // Integer multiply pipeline
105 // Integer load pipeline
184 // Integer store pipeline
248 // Issue through integer pipeline, and execute in NEON unit. We assume
249 // RunFast mode so that NFP pipeline is used for single-precision when
437 // Issue through integer pipeline, and execute in NEON unit.
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H A DARMScheduleM7.td116 // The FP pipeline has a latency of 3 cycles.
117 // ALU operations (32/64-bit). These go down the FP pipeline.
173 // What pipeline stage operands need to be ready for depending on
188 // Assume that these will go down the main ALU pipeline.
189 // In reality, many look likely to stall the whole pipeline.
469 // Double-precision chained MAC stalls the pipeline behind it for 3 cycles,
488 // Double-precision fused MAC stalls the pipeline behind it for 2 cycles, making
H A DARMScheduleM55.td15 // has an extra pipeline stage but that is unimportant for scheduling, just
26 // up with the rest of the pipeline we model, and take the latency as the time
35 // can look like this is a pipeline:
60 // instructions at the point in the pipeline where we do the scheduling. The
79 // T2SizeReduction pass earlier in the pipeline, for example, so that at least
104 // Modeling each pipeline as a ProcResource using the BufferSize = 0 since
112 // Some VMOV's can go down either pipeline. FIXME: This M55Write2IntFPE2 is
421 // Some VMOV's can go down either pipeline.
/freebsd/sys/contrib/device-tree/Bindings/media/xilinx/
H A Dxlnx,video.txt7 Xilinx video IP pipeline processes video streams through one or more Xilinx
10 node of the VIPP represents as a top level node of the pipeline and defines
H A Dvideo.txt6 creating a video pipeline.
12 The whole pipeline is represented by an AMBA bus child node in the device
/freebsd/bin/sh/
H A Dnodetypes59 NPIPE npipe # a pipeline
61 backgnd int # set to run pipeline in background
62 cmdlist nodelist # the commands in the pipeline
140 NNOT nnot # ! command (actually pipeline)
/freebsd/sys/contrib/device-tree/Bindings/display/bridge/
H A Dmegachips-stdpxxxx-ge-b850v3-fw.txt5 The video processing pipeline on the second output on the GE B850v3:
15 The hardware do not provide control over the video processing pipeline, as the
/freebsd/sys/contrib/device-tree/Bindings/arc/
H A Darchs-pct.txt3 The ARC HS can be configured with a pipeline performance monitor for counting
H A Dpct.txt3 The ARC700 can be configured with a pipeline performance monitor for counting
/freebsd/crypto/openssl/doc/man3/
H A DSSL_CTX_set_split_send_fragment.pod55 "read" pipelining and "write" pipelining. By default only one pipeline will be
59 explained further below. OpenSSL will only ever use more than one pipeline if
60 a cipher suite is negotiated that uses a pipeline capable cipher provided by an
73 SSL_write/SSL_write_ex called with 0-2000 bytes == 1 pipeline used
/freebsd/sys/crypto/openssl/arm/
H A Dsha512-armv4.S27 @ Rescheduling for dual-issue pipeline resulted in 6% improvement on
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVSchedSiFiveP400.td25 // One pipeline for FPU operations.
26 // One pipeline for Load operations.
27 // One pipeline for Store operations.
/freebsd/sys/contrib/device-tree/Bindings/hsi/
H A Dclient-devices.txt15 - hsi-flow: RX flow type ("synchronized" or "pipeline")

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