1 // SPDX-License-Identifier: BSD-2-Clause OR GPL-2.0-only
2 /*
3 * Implement fast Fletcher4 with AVX2 instructions. (x86_64)
4 *
5 * Use the 256-bit AVX2 SIMD instructions and registers to compute
6 * Fletcher4 in four incremental 64-bit parallel accumulator streams,
7 * and then combine the streams to form the final four checksum words.
8 *
9 * Copyright (C) 2015 Intel Corporation.
10 *
11 * Authors:
12 * James Guilford <james.guilford@intel.com>
13 * Jinshan Xiong <jinshan.xiong@intel.com>
14 *
15 * This software is available to you under a choice of one of two
16 * licenses. You may choose to be licensed under the terms of the GNU
17 * General Public License (GPL) Version 2, available from the file
18 * COPYING in the main directory of this source tree, or the
19 * OpenIB.org BSD license below:
20 *
21 * Redistribution and use in source and binary forms, with or
22 * without modification, are permitted provided that the following
23 * conditions are met:
24 *
25 * - Redistributions of source code must retain the above
26 * copyright notice, this list of conditions and the following
27 * disclaimer.
28 *
29 * - Redistributions in binary form must reproduce the above
30 * copyright notice, this list of conditions and the following
31 * disclaimer in the documentation and/or other materials
32 * provided with the distribution.
33 *
34 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
35 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
36 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
37 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
38 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
39 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
40 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
41 * SOFTWARE.
42 */
43
44 #if defined(HAVE_AVX) && defined(HAVE_AVX2)
45
46 #include <sys/spa_checksum.h>
47 #include <sys/string.h>
48 #include <sys/simd.h>
49 #include <zfs_fletcher.h>
50
51 static void
fletcher_4_avx2_init(fletcher_4_ctx_t * ctx)52 fletcher_4_avx2_init(fletcher_4_ctx_t *ctx)
53 {
54 memset(ctx->avx, 0, 4 * sizeof (zfs_fletcher_avx_t));
55 }
56
57 static void
fletcher_4_avx2_fini(fletcher_4_ctx_t * ctx,zio_cksum_t * zcp)58 fletcher_4_avx2_fini(fletcher_4_ctx_t *ctx, zio_cksum_t *zcp)
59 {
60 uint64_t A, B, C, D;
61
62 A = ctx->avx[0].v[0] + ctx->avx[0].v[1] +
63 ctx->avx[0].v[2] + ctx->avx[0].v[3];
64 B = 0 - ctx->avx[0].v[1] - 2 * ctx->avx[0].v[2] - 3 * ctx->avx[0].v[3] +
65 4 * ctx->avx[1].v[0] + 4 * ctx->avx[1].v[1] + 4 * ctx->avx[1].v[2] +
66 4 * ctx->avx[1].v[3];
67
68 C = ctx->avx[0].v[2] + 3 * ctx->avx[0].v[3] - 6 * ctx->avx[1].v[0] -
69 10 * ctx->avx[1].v[1] - 14 * ctx->avx[1].v[2] -
70 18 * ctx->avx[1].v[3] + 16 * ctx->avx[2].v[0] +
71 16 * ctx->avx[2].v[1] + 16 * ctx->avx[2].v[2] +
72 16 * ctx->avx[2].v[3];
73
74 D = 0 - ctx->avx[0].v[3] + 4 * ctx->avx[1].v[0] +
75 10 * ctx->avx[1].v[1] + 20 * ctx->avx[1].v[2] +
76 34 * ctx->avx[1].v[3] - 48 * ctx->avx[2].v[0] -
77 64 * ctx->avx[2].v[1] - 80 * ctx->avx[2].v[2] -
78 96 * ctx->avx[2].v[3] + 64 * ctx->avx[3].v[0] +
79 64 * ctx->avx[3].v[1] + 64 * ctx->avx[3].v[2] +
80 64 * ctx->avx[3].v[3];
81
82 ZIO_SET_CHECKSUM(zcp, A, B, C, D);
83 }
84
85 #define FLETCHER_4_AVX2_RESTORE_CTX(ctx) \
86 { \
87 asm volatile("vmovdqu %0, %%ymm0" :: "m" ((ctx)->avx[0])); \
88 asm volatile("vmovdqu %0, %%ymm1" :: "m" ((ctx)->avx[1])); \
89 asm volatile("vmovdqu %0, %%ymm2" :: "m" ((ctx)->avx[2])); \
90 asm volatile("vmovdqu %0, %%ymm3" :: "m" ((ctx)->avx[3])); \
91 }
92
93 #define FLETCHER_4_AVX2_SAVE_CTX(ctx) \
94 { \
95 asm volatile("vmovdqu %%ymm0, %0" : "=m" ((ctx)->avx[0])); \
96 asm volatile("vmovdqu %%ymm1, %0" : "=m" ((ctx)->avx[1])); \
97 asm volatile("vmovdqu %%ymm2, %0" : "=m" ((ctx)->avx[2])); \
98 asm volatile("vmovdqu %%ymm3, %0" : "=m" ((ctx)->avx[3])); \
99 }
100
101
102 static void
fletcher_4_avx2_native(fletcher_4_ctx_t * ctx,const void * buf,uint64_t size)103 fletcher_4_avx2_native(fletcher_4_ctx_t *ctx, const void *buf, uint64_t size)
104 {
105 const uint64_t *ip = buf;
106 const uint64_t *ipend = (uint64_t *)((uint8_t *)ip + size);
107
108 FLETCHER_4_AVX2_RESTORE_CTX(ctx);
109
110 do {
111 asm volatile("vpmovzxdq %0, %%ymm4"::"m" (*ip));
112 asm volatile("vpaddq %ymm4, %ymm0, %ymm0");
113 asm volatile("vpaddq %ymm0, %ymm1, %ymm1");
114 asm volatile("vpaddq %ymm1, %ymm2, %ymm2");
115 asm volatile("vpaddq %ymm2, %ymm3, %ymm3");
116 } while ((ip += 2) < ipend);
117
118 FLETCHER_4_AVX2_SAVE_CTX(ctx);
119 asm volatile("vzeroupper");
120 }
121
122 static void
fletcher_4_avx2_byteswap(fletcher_4_ctx_t * ctx,const void * buf,uint64_t size)123 fletcher_4_avx2_byteswap(fletcher_4_ctx_t *ctx, const void *buf, uint64_t size)
124 {
125 static const zfs_fletcher_avx_t mask = {
126 .v = { 0xFFFFFFFF00010203, 0xFFFFFFFF08090A0B,
127 0xFFFFFFFF00010203, 0xFFFFFFFF08090A0B }
128 };
129 const uint64_t *ip = buf;
130 const uint64_t *ipend = (uint64_t *)((uint8_t *)ip + size);
131
132 FLETCHER_4_AVX2_RESTORE_CTX(ctx);
133
134 asm volatile("vmovdqu %0, %%ymm5" :: "m" (mask));
135
136 do {
137 asm volatile("vpmovzxdq %0, %%ymm4"::"m" (*ip));
138 asm volatile("vpshufb %ymm5, %ymm4, %ymm4");
139
140 asm volatile("vpaddq %ymm4, %ymm0, %ymm0");
141 asm volatile("vpaddq %ymm0, %ymm1, %ymm1");
142 asm volatile("vpaddq %ymm1, %ymm2, %ymm2");
143 asm volatile("vpaddq %ymm2, %ymm3, %ymm3");
144 } while ((ip += 2) < ipend);
145
146 FLETCHER_4_AVX2_SAVE_CTX(ctx);
147 asm volatile("vzeroupper");
148 }
149
fletcher_4_avx2_valid(void)150 static boolean_t fletcher_4_avx2_valid(void)
151 {
152 return (kfpu_allowed() && zfs_avx_available() && zfs_avx2_available());
153 }
154
155 const fletcher_4_ops_t fletcher_4_avx2_ops = {
156 .init_native = fletcher_4_avx2_init,
157 .fini_native = fletcher_4_avx2_fini,
158 .compute_native = fletcher_4_avx2_native,
159 .init_byteswap = fletcher_4_avx2_init,
160 .fini_byteswap = fletcher_4_avx2_fini,
161 .compute_byteswap = fletcher_4_avx2_byteswap,
162 .valid = fletcher_4_avx2_valid,
163 .uses_fpu = B_TRUE,
164 .name = "avx2"
165 };
166
167 #endif /* defined(HAVE_AVX) && defined(HAVE_AVX2) */
168