1 /* 2 * This file and its contents are supplied under the terms of the 3 * Common Development and Distribution License ("CDDL"), version 1.0. 4 * You may only use this file in accordance with the terms of version 5 * 1.0 of the CDDL. 6 * 7 * A full copy of the text of the CDDL should have accompanied this 8 * source. A copy of the CDDL is also available via the Internet at 9 * http://www.illumos.org/license/CDDL. 10 */ 11 12 /* 13 * Copyright 2025 Oxide Computer Company 14 */ 15 16 /* 17 * This provides a few different examples of how we take into account the DRAM 18 * hole. There are three primary cases to consider: 19 * 20 * o Taking it into account when determine if DRAM is valid or not. 21 * o Taking it into account when we do address interleaving (DFv4) 22 * o Taking it into account when performing normalization. 23 */ 24 25 #include "zen_umc_test.h" 26 27 /* 28 * This is a standard application of the DRAM hole starting at 2 GiB in the 29 * space. This follows the DFv3 rules. 30 */ 31 static const zen_umc_t zen_umc_hole_dfv3 = { 32 .umc_tom = 2ULL * 1024ULL * 1024ULL * 1024ULL, 33 .umc_tom2 = 68ULL * 1024ULL * 1024ULL * 1024ULL, 34 .umc_df_rev = DF_REV_3, 35 .umc_decomp = { 36 .dfd_sock_mask = 0x01, 37 .dfd_die_mask = 0x00, 38 .dfd_node_mask = 0x20, 39 .dfd_comp_mask = 0x1f, 40 .dfd_sock_shift = 0, 41 .dfd_die_shift = 0, 42 .dfd_node_shift = 5, 43 .dfd_comp_shift = 0 44 }, 45 .umc_ndfs = 1, 46 .umc_dfs = { { 47 .zud_flags = ZEN_UMC_DF_F_HOLE_VALID, 48 .zud_dfno = 0, 49 .zud_dram_nrules = 1, 50 .zud_nchan = 4, 51 .zud_cs_nremap = 0, 52 .zud_hole_base = 0x80000000, 53 .zud_rules = { { 54 .ddr_flags = DF_DRAM_F_VALID | DF_DRAM_F_HOLE, 55 .ddr_base = 0, 56 .ddr_limit = 68ULL * 1024ULL * 1024ULL * 1024ULL, 57 .ddr_dest_fabid = 0, 58 .ddr_sock_ileave_bits = 0, 59 .ddr_die_ileave_bits = 0, 60 .ddr_addr_start = 9, 61 .ddr_chan_ileave = DF_CHAN_ILEAVE_4CH 62 } }, 63 .zud_chan = { { 64 .chan_flags = UMC_CHAN_F_ECC_EN, 65 .chan_fabid = 0, 66 .chan_instid = 0, 67 .chan_logid = 0, 68 .chan_nrules = 1, 69 .chan_type = UMC_DIMM_T_DDR4, 70 .chan_rules = { { 71 .ddr_flags = DF_DRAM_F_VALID | DF_DRAM_F_HOLE, 72 .ddr_base = 0, 73 .ddr_limit = 68ULL * 1024ULL * 1024ULL * 74 1024ULL, 75 .ddr_dest_fabid = 0, 76 .ddr_sock_ileave_bits = 0, 77 .ddr_die_ileave_bits = 0, 78 .ddr_addr_start = 9, 79 .ddr_chan_ileave = DF_CHAN_ILEAVE_4CH 80 } }, 81 .chan_dimms = { { 82 .ud_flags = UMC_DIMM_F_VALID, 83 .ud_width = UMC_DIMM_W_X4, 84 .ud_kind = UMC_DIMM_K_RDIMM, 85 .ud_dimmno = 0, 86 .ud_cs = { { 87 .ucs_flags = UMC_CS_F_DECODE_EN, 88 .ucs_base = { 89 .udb_base = 0, 90 .udb_valid = B_TRUE 91 }, 92 .ucs_base_mask = 0x3ffffffff, 93 .ucs_nbanks = 0x4, 94 .ucs_ncol = 0xa, 95 .ucs_nrow_lo = 0x11, 96 .ucs_nbank_groups = 0x2, 97 .ucs_row_hi_bit = 0x18, 98 .ucs_row_low_bit = 0x11, 99 .ucs_bank_bits = { 0xf, 0x10, 0xd, 100 0xe }, 101 .ucs_col_bits = { 0x3, 0x4, 0x5, 0x6, 102 0x7, 0x8, 0x9, 0xa, 0xb, 0xc } 103 } } 104 } }, 105 }, { 106 .chan_flags = UMC_CHAN_F_ECC_EN, 107 .chan_fabid = 1, 108 .chan_instid = 1, 109 .chan_logid = 1, 110 .chan_nrules = 1, 111 .chan_type = UMC_DIMM_T_DDR4, 112 .chan_rules = { { 113 .ddr_flags = DF_DRAM_F_VALID | DF_DRAM_F_HOLE, 114 .ddr_base = 0, 115 .ddr_limit = 68ULL * 1024ULL * 1024ULL * 116 1024ULL, 117 .ddr_dest_fabid = 0, 118 .ddr_sock_ileave_bits = 0, 119 .ddr_die_ileave_bits = 0, 120 .ddr_addr_start = 9, 121 .ddr_chan_ileave = DF_CHAN_ILEAVE_4CH 122 } }, 123 .chan_dimms = { { 124 .ud_flags = UMC_DIMM_F_VALID, 125 .ud_width = UMC_DIMM_W_X4, 126 .ud_kind = UMC_DIMM_K_RDIMM, 127 .ud_dimmno = 0, 128 .ud_cs = { { 129 .ucs_flags = UMC_CS_F_DECODE_EN, 130 .ucs_base = { 131 .udb_base = 0, 132 .udb_valid = B_TRUE 133 }, 134 .ucs_base_mask = 0x3ffffffff, 135 .ucs_nbanks = 0x4, 136 .ucs_ncol = 0xa, 137 .ucs_nrow_lo = 0x11, 138 .ucs_nbank_groups = 0x2, 139 .ucs_row_hi_bit = 0x18, 140 .ucs_row_low_bit = 0x11, 141 .ucs_bank_bits = { 0xf, 0x10, 0xd, 142 0xe }, 143 .ucs_col_bits = { 0x3, 0x4, 0x5, 0x6, 144 0x7, 0x8, 0x9, 0xa, 0xb, 0xc } 145 } } 146 } }, 147 }, { 148 .chan_flags = UMC_CHAN_F_ECC_EN, 149 .chan_fabid = 2, 150 .chan_instid = 2, 151 .chan_logid = 2, 152 .chan_nrules = 1, 153 .chan_type = UMC_DIMM_T_DDR4, 154 .chan_rules = { { 155 .ddr_flags = DF_DRAM_F_VALID | DF_DRAM_F_HOLE, 156 .ddr_base = 0, 157 .ddr_limit = 68ULL * 1024ULL * 1024ULL * 158 1024ULL, 159 .ddr_dest_fabid = 0, 160 .ddr_sock_ileave_bits = 0, 161 .ddr_die_ileave_bits = 0, 162 .ddr_addr_start = 9, 163 .ddr_chan_ileave = DF_CHAN_ILEAVE_4CH 164 } }, 165 .chan_dimms = { { 166 .ud_flags = UMC_DIMM_F_VALID, 167 .ud_width = UMC_DIMM_W_X4, 168 .ud_kind = UMC_DIMM_K_RDIMM, 169 .ud_dimmno = 0, 170 .ud_cs = { { 171 .ucs_flags = UMC_CS_F_DECODE_EN, 172 .ucs_base = { 173 .udb_base = 0, 174 .udb_valid = B_TRUE 175 }, 176 .ucs_base_mask = 0x3ffffffff, 177 .ucs_nbanks = 0x4, 178 .ucs_ncol = 0xa, 179 .ucs_nrow_lo = 0x11, 180 .ucs_nbank_groups = 0x2, 181 .ucs_row_hi_bit = 0x18, 182 .ucs_row_low_bit = 0x11, 183 .ucs_bank_bits = { 0xf, 0x10, 0xd, 184 0xe }, 185 .ucs_col_bits = { 0x3, 0x4, 0x5, 0x6, 186 0x7, 0x8, 0x9, 0xa, 0xb, 0xc } 187 } } 188 } }, 189 }, { 190 .chan_flags = UMC_CHAN_F_ECC_EN, 191 .chan_fabid = 3, 192 .chan_instid = 3, 193 .chan_logid = 3, 194 .chan_nrules = 1, 195 .chan_type = UMC_DIMM_T_DDR4, 196 .chan_rules = { { 197 .ddr_flags = DF_DRAM_F_VALID | DF_DRAM_F_HOLE, 198 .ddr_base = 0, 199 .ddr_limit = 68ULL * 1024ULL * 1024ULL * 200 1024ULL, 201 .ddr_dest_fabid = 0, 202 .ddr_sock_ileave_bits = 0, 203 .ddr_die_ileave_bits = 0, 204 .ddr_addr_start = 9, 205 .ddr_chan_ileave = DF_CHAN_ILEAVE_4CH 206 } }, 207 .chan_dimms = { { 208 .ud_flags = UMC_DIMM_F_VALID, 209 .ud_width = UMC_DIMM_W_X4, 210 .ud_kind = UMC_DIMM_K_RDIMM, 211 .ud_dimmno = 0, 212 .ud_cs = { { 213 .ucs_flags = UMC_CS_F_DECODE_EN, 214 .ucs_base = { 215 .udb_base = 0, 216 .udb_valid = B_TRUE 217 }, 218 .ucs_base_mask = 0x3ffffffff, 219 .ucs_nbanks = 0x4, 220 .ucs_ncol = 0xa, 221 .ucs_nrow_lo = 0x11, 222 .ucs_nbank_groups = 0x2, 223 .ucs_row_hi_bit = 0x18, 224 .ucs_row_low_bit = 0x11, 225 .ucs_bank_bits = { 0xf, 0x10, 0xd, 226 0xe }, 227 .ucs_col_bits = { 0x3, 0x4, 0x5, 0x6, 228 0x7, 0x8, 0x9, 0xa, 0xb, 0xc } 229 } } 230 } }, 231 } } 232 } } 233 }; 234 235 /* 236 * This case is a little insidious to be honest. Here we're using a DFv4 style 237 * DRAM hole. Technically the hole needs to be taken into account before 238 * interleaving here (unlike DFv3). So we shrink the hole's size to 4 KiB and 239 * set up interleaving at address 12. This ensures that stuff around the hole 240 * will catch this and adjust for interleve. Yes, this is smaller than the hole 241 * is allowed to be in hardware, but here we're all just integers. Basically the 242 * whole covers the last 4 KiB of low memory. We use hex here to make these 243 * easier to deal with. 244 */ 245 static const zen_umc_t zen_umc_hole_dfv4 = { 246 .umc_tom = 0xfffff000, 247 .umc_tom2 = 0x1000001000, 248 .umc_df_rev = DF_REV_4, 249 .umc_decomp = { 250 .dfd_sock_mask = 0x01, 251 .dfd_die_mask = 0x00, 252 .dfd_node_mask = 0x20, 253 .dfd_comp_mask = 0x1f, 254 .dfd_sock_shift = 0, 255 .dfd_die_shift = 0, 256 .dfd_node_shift = 5, 257 .dfd_comp_shift = 0 258 }, 259 .umc_ndfs = 1, 260 .umc_dfs = { { 261 .zud_flags = ZEN_UMC_DF_F_HOLE_VALID, 262 .zud_dfno = 0, 263 .zud_dram_nrules = 1, 264 .zud_nchan = 4, 265 .zud_cs_nremap = 0, 266 .zud_hole_base = 0xfffff000, 267 .zud_rules = { { 268 .ddr_flags = DF_DRAM_F_VALID | DF_DRAM_F_HOLE, 269 .ddr_base = 0, 270 .ddr_limit = 0x1000001000, 271 .ddr_dest_fabid = 0, 272 .ddr_sock_ileave_bits = 0, 273 .ddr_die_ileave_bits = 0, 274 .ddr_addr_start = 12, 275 .ddr_chan_ileave = DF_CHAN_ILEAVE_4CH 276 } }, 277 .zud_chan = { { 278 .chan_flags = UMC_CHAN_F_ECC_EN, 279 .chan_fabid = 0, 280 .chan_instid = 0, 281 .chan_logid = 0, 282 .chan_nrules = 1, 283 .chan_type = UMC_DIMM_T_DDR4, 284 .chan_rules = { { 285 .ddr_flags = DF_DRAM_F_VALID | DF_DRAM_F_HOLE, 286 .ddr_base = 0, 287 .ddr_limit = 0x1000001000, 288 .ddr_dest_fabid = 0, 289 .ddr_sock_ileave_bits = 0, 290 .ddr_die_ileave_bits = 0, 291 .ddr_addr_start = 12, 292 .ddr_chan_ileave = DF_CHAN_ILEAVE_4CH 293 } }, 294 .chan_dimms = { { 295 .ud_flags = UMC_DIMM_F_VALID, 296 .ud_width = UMC_DIMM_W_X4, 297 .ud_kind = UMC_DIMM_K_RDIMM, 298 .ud_dimmno = 0, 299 .ud_cs = { { 300 .ucs_flags = UMC_CS_F_DECODE_EN, 301 .ucs_base = { 302 .udb_base = 0, 303 .udb_valid = B_TRUE 304 }, 305 .ucs_base_mask = 0x3ffffffff, 306 .ucs_nbanks = 0x4, 307 .ucs_ncol = 0xa, 308 .ucs_nrow_lo = 0x11, 309 .ucs_nbank_groups = 0x2, 310 .ucs_row_hi_bit = 0x18, 311 .ucs_row_low_bit = 0x11, 312 .ucs_bank_bits = { 0xf, 0x10, 0xd, 313 0xe }, 314 .ucs_col_bits = { 0x3, 0x4, 0x5, 0x6, 315 0x7, 0x8, 0x9, 0xa, 0xb, 0xc } 316 } } 317 } }, 318 }, { 319 .chan_flags = UMC_CHAN_F_ECC_EN, 320 .chan_fabid = 1, 321 .chan_instid = 1, 322 .chan_logid = 1, 323 .chan_nrules = 1, 324 .chan_type = UMC_DIMM_T_DDR4, 325 .chan_rules = { { 326 .ddr_flags = DF_DRAM_F_VALID | DF_DRAM_F_HOLE, 327 .ddr_base = 0, 328 .ddr_limit = 0x1000001000, 329 .ddr_dest_fabid = 0, 330 .ddr_sock_ileave_bits = 0, 331 .ddr_die_ileave_bits = 0, 332 .ddr_addr_start = 12, 333 .ddr_chan_ileave = DF_CHAN_ILEAVE_4CH 334 } }, 335 .chan_dimms = { { 336 .ud_flags = UMC_DIMM_F_VALID, 337 .ud_width = UMC_DIMM_W_X4, 338 .ud_kind = UMC_DIMM_K_RDIMM, 339 .ud_dimmno = 0, 340 .ud_cs = { { 341 .ucs_flags = UMC_CS_F_DECODE_EN, 342 .ucs_base = { 343 .udb_base = 0, 344 .udb_valid = B_TRUE 345 }, 346 .ucs_base_mask = 0x3ffffffff, 347 .ucs_nbanks = 0x4, 348 .ucs_ncol = 0xa, 349 .ucs_nrow_lo = 0x11, 350 .ucs_nbank_groups = 0x2, 351 .ucs_row_hi_bit = 0x18, 352 .ucs_row_low_bit = 0x11, 353 .ucs_bank_bits = { 0xf, 0x10, 0xd, 354 0xe }, 355 .ucs_col_bits = { 0x3, 0x4, 0x5, 0x6, 356 0x7, 0x8, 0x9, 0xa, 0xb, 0xc } 357 } } 358 } }, 359 }, { 360 .chan_flags = UMC_CHAN_F_ECC_EN, 361 .chan_fabid = 2, 362 .chan_instid = 2, 363 .chan_logid = 2, 364 .chan_nrules = 1, 365 .chan_type = UMC_DIMM_T_DDR4, 366 .chan_rules = { { 367 .ddr_flags = DF_DRAM_F_VALID | DF_DRAM_F_HOLE, 368 .ddr_base = 0, 369 .ddr_limit = 0x1000001000, 370 .ddr_dest_fabid = 0, 371 .ddr_sock_ileave_bits = 0, 372 .ddr_die_ileave_bits = 0, 373 .ddr_addr_start = 12, 374 .ddr_chan_ileave = DF_CHAN_ILEAVE_4CH 375 } }, 376 .chan_dimms = { { 377 .ud_flags = UMC_DIMM_F_VALID, 378 .ud_width = UMC_DIMM_W_X4, 379 .ud_kind = UMC_DIMM_K_RDIMM, 380 .ud_dimmno = 0, 381 .ud_cs = { { 382 .ucs_flags = UMC_CS_F_DECODE_EN, 383 .ucs_base = { 384 .udb_base = 0, 385 .udb_valid = B_TRUE 386 }, 387 .ucs_base_mask = 0x3ffffffff, 388 .ucs_nbanks = 0x4, 389 .ucs_ncol = 0xa, 390 .ucs_nrow_lo = 0x11, 391 .ucs_nbank_groups = 0x2, 392 .ucs_row_hi_bit = 0x18, 393 .ucs_row_low_bit = 0x11, 394 .ucs_bank_bits = { 0xf, 0x10, 0xd, 395 0xe }, 396 .ucs_col_bits = { 0x3, 0x4, 0x5, 0x6, 397 0x7, 0x8, 0x9, 0xa, 0xb, 0xc } 398 } } 399 } }, 400 }, { 401 .chan_flags = UMC_CHAN_F_ECC_EN, 402 .chan_fabid = 3, 403 .chan_instid = 3, 404 .chan_logid = 3, 405 .chan_nrules = 1, 406 .chan_type = UMC_DIMM_T_DDR4, 407 .chan_rules = { { 408 .ddr_flags = DF_DRAM_F_VALID | DF_DRAM_F_HOLE, 409 .ddr_base = 0, 410 .ddr_limit = 0x1000001000, 411 .ddr_dest_fabid = 0, 412 .ddr_sock_ileave_bits = 0, 413 .ddr_die_ileave_bits = 0, 414 .ddr_addr_start = 12, 415 .ddr_chan_ileave = DF_CHAN_ILEAVE_4CH 416 } }, 417 .chan_dimms = { { 418 .ud_flags = UMC_DIMM_F_VALID, 419 .ud_width = UMC_DIMM_W_X4, 420 .ud_kind = UMC_DIMM_K_RDIMM, 421 .ud_dimmno = 0, 422 .ud_cs = { { 423 .ucs_flags = UMC_CS_F_DECODE_EN, 424 .ucs_base = { 425 .udb_base = 0, 426 .udb_valid = B_TRUE 427 }, 428 .ucs_base_mask = 0x3ffffffff, 429 .ucs_nbanks = 0x4, 430 .ucs_ncol = 0xa, 431 .ucs_nrow_lo = 0x11, 432 .ucs_nbank_groups = 0x2, 433 .ucs_row_hi_bit = 0x18, 434 .ucs_row_low_bit = 0x11, 435 .ucs_bank_bits = { 0xf, 0x10, 0xd, 436 0xe }, 437 .ucs_col_bits = { 0x3, 0x4, 0x5, 0x6, 438 0x7, 0x8, 0x9, 0xa, 0xb, 0xc } 439 } } 440 } }, 441 } } 442 } } 443 }; 444 445 446 const umc_decode_test_t zen_umc_test_hole[] = { { 447 .udt_desc = "Memory in hole doesn't decode (0)", 448 .udt_umc = &zen_umc_hole_dfv3, 449 .udt_pa = 0xb0000000, 450 .udt_pass = B_FALSE, 451 .udt_fail = ZEN_UMC_DECODE_F_OUTSIDE_DRAM 452 }, { 453 .udt_desc = "Memory in hole doesn't decode (1)", 454 .udt_umc = &zen_umc_hole_dfv3, 455 .udt_pa = 0x80000000, 456 .udt_pass = B_FALSE, 457 .udt_fail = ZEN_UMC_DECODE_F_OUTSIDE_DRAM 458 }, { 459 .udt_desc = "Memory in hole doesn't decode (2)", 460 .udt_umc = &zen_umc_hole_dfv3, 461 .udt_pa = 0xffffffff, 462 .udt_pass = B_FALSE, 463 .udt_fail = ZEN_UMC_DECODE_F_OUTSIDE_DRAM 464 }, { 465 .udt_desc = "Memory in hole doesn't decode (3)", 466 .udt_umc = &zen_umc_hole_dfv3, 467 .udt_pa = 0xcba89754, 468 .udt_pass = B_FALSE, 469 .udt_fail = ZEN_UMC_DECODE_F_OUTSIDE_DRAM 470 }, { 471 .udt_desc = "DRAM Hole DFv3 4ch (0)", 472 .udt_umc = &zen_umc_hole_dfv3, 473 .udt_pa = 0x7fffffff, 474 .udt_pass = B_TRUE, 475 .udt_norm_addr = 0x1fffffff, 476 .udt_sock = 0, 477 .udt_die = 0, 478 .udt_comp = 3, 479 .udt_dimm_no = 0, 480 .udt_dimm_col = 0x3ff, 481 .udt_dimm_row = 0xfff, 482 .udt_dimm_bank = 3, 483 .udt_dimm_bank_group = 3, 484 .udt_dimm_subchan = 0, 485 .udt_dimm_rm = 0, 486 .udt_dimm_cs = 0 487 }, { 488 .udt_desc = "DRAM Hole DFv3 4ch (1)", 489 .udt_umc = &zen_umc_hole_dfv3, 490 .udt_pa = 0x7ffffdff, 491 .udt_pass = B_TRUE, 492 .udt_norm_addr = 0x1fffffff, 493 .udt_sock = 0, 494 .udt_die = 0, 495 .udt_comp = 2, 496 .udt_dimm_no = 0, 497 .udt_dimm_col = 0x3ff, 498 .udt_dimm_row = 0xfff, 499 .udt_dimm_bank = 3, 500 .udt_dimm_bank_group = 3, 501 .udt_dimm_subchan = 0, 502 .udt_dimm_rm = 0, 503 .udt_dimm_cs = 0 504 }, { 505 .udt_desc = "DRAM Hole DFv3 4ch (2)", 506 .udt_umc = &zen_umc_hole_dfv3, 507 .udt_pa = 0x7ffffbff, 508 .udt_pass = B_TRUE, 509 .udt_norm_addr = 0x1fffffff, 510 .udt_sock = 0, 511 .udt_die = 0, 512 .udt_comp = 1, 513 .udt_dimm_no = 0, 514 .udt_dimm_col = 0x3ff, 515 .udt_dimm_row = 0xfff, 516 .udt_dimm_bank = 3, 517 .udt_dimm_bank_group = 3, 518 .udt_dimm_subchan = 0, 519 .udt_dimm_rm = 0, 520 .udt_dimm_cs = 0 521 }, { 522 .udt_desc = "DRAM Hole DFv3 4ch (3)", 523 .udt_umc = &zen_umc_hole_dfv3, 524 .udt_pa = 0x7ffff9ff, 525 .udt_pass = B_TRUE, 526 .udt_norm_addr = 0x1fffffff, 527 .udt_sock = 0, 528 .udt_die = 0, 529 .udt_comp = 0, 530 .udt_dimm_no = 0, 531 .udt_dimm_col = 0x3ff, 532 .udt_dimm_row = 0xfff, 533 .udt_dimm_bank = 3, 534 .udt_dimm_bank_group = 3, 535 .udt_dimm_subchan = 0, 536 .udt_dimm_rm = 0, 537 .udt_dimm_cs = 0 538 }, { 539 .udt_desc = "DRAM Hole DFv3 4ch (4)", 540 .udt_umc = &zen_umc_hole_dfv3, 541 .udt_pa = 0x100000000, 542 .udt_pass = B_TRUE, 543 .udt_norm_addr = 0x20000000, 544 .udt_sock = 0, 545 .udt_die = 0, 546 .udt_comp = 0, 547 .udt_dimm_no = 0, 548 .udt_dimm_col = 0x0, 549 .udt_dimm_row = 0x1000, 550 .udt_dimm_bank = 0, 551 .udt_dimm_bank_group = 0, 552 .udt_dimm_subchan = 0, 553 .udt_dimm_rm = 0, 554 .udt_dimm_cs = 0 555 }, { 556 .udt_desc = "DRAM Hole DFv3 4ch (5)", 557 .udt_umc = &zen_umc_hole_dfv3, 558 .udt_pa = 0x100000200, 559 .udt_pass = B_TRUE, 560 .udt_norm_addr = 0x20000000, 561 .udt_sock = 0, 562 .udt_die = 0, 563 .udt_comp = 1, 564 .udt_dimm_no = 0, 565 .udt_dimm_col = 0x0, 566 .udt_dimm_row = 0x1000, 567 .udt_dimm_bank = 0, 568 .udt_dimm_bank_group = 0, 569 .udt_dimm_subchan = 0, 570 .udt_dimm_rm = 0, 571 .udt_dimm_cs = 0 572 }, { 573 .udt_desc = "DRAM Hole DFv3 4ch (6)", 574 .udt_umc = &zen_umc_hole_dfv3, 575 .udt_pa = 0x100000400, 576 .udt_pass = B_TRUE, 577 .udt_norm_addr = 0x20000000, 578 .udt_sock = 0, 579 .udt_die = 0, 580 .udt_comp = 2, 581 .udt_dimm_no = 0, 582 .udt_dimm_col = 0x0, 583 .udt_dimm_row = 0x1000, 584 .udt_dimm_bank = 0, 585 .udt_dimm_bank_group = 0, 586 .udt_dimm_subchan = 0, 587 .udt_dimm_rm = 0, 588 .udt_dimm_cs = 0 589 }, { 590 .udt_desc = "DRAM Hole DFv3 4ch (7)", 591 .udt_umc = &zen_umc_hole_dfv3, 592 .udt_pa = 0x100000600, 593 .udt_pass = B_TRUE, 594 .udt_norm_addr = 0x20000000, 595 .udt_sock = 0, 596 .udt_die = 0, 597 .udt_comp = 3, 598 .udt_dimm_no = 0, 599 .udt_dimm_col = 0x0, 600 .udt_dimm_row = 0x1000, 601 .udt_dimm_bank = 0, 602 .udt_dimm_bank_group = 0, 603 .udt_dimm_subchan = 0, 604 .udt_dimm_rm = 0, 605 .udt_dimm_cs = 0 606 }, { 607 .udt_desc = "DRAM Hole DFv4 4ch Shenanigans (0)", 608 .udt_umc = &zen_umc_hole_dfv4, 609 .udt_pa = 0x100000000, 610 .udt_pass = B_TRUE, 611 .udt_norm_addr = 0x3ffff000, 612 .udt_sock = 0, 613 .udt_die = 0, 614 .udt_comp = 3, 615 .udt_dimm_no = 0, 616 .udt_dimm_col = 0x200, 617 .udt_dimm_row = 0x1fff, 618 .udt_dimm_bank = 3, 619 .udt_dimm_bank_group = 3, 620 .udt_dimm_subchan = 0, 621 .udt_dimm_rm = 0, 622 .udt_dimm_cs = 0 623 }, { 624 .udt_desc = "DRAM Hole DFv4 4ch Shenanigans (1)", 625 .udt_umc = &zen_umc_hole_dfv4, 626 .udt_pa = 0x100001000, 627 .udt_pass = B_TRUE, 628 .udt_norm_addr = 0x40000000, 629 .udt_sock = 0, 630 .udt_die = 0, 631 .udt_comp = 0, 632 .udt_dimm_no = 0, 633 .udt_dimm_col = 0x0, 634 .udt_dimm_row = 0x2000, 635 .udt_dimm_bank = 0, 636 .udt_dimm_bank_group = 0, 637 .udt_dimm_subchan = 0, 638 .udt_dimm_rm = 0, 639 .udt_dimm_cs = 0 640 }, { 641 .udt_desc = "DRAM Hole DFv4 4ch Shenanigans (2)", 642 .udt_umc = &zen_umc_hole_dfv4, 643 .udt_pa = 0x100002000, 644 .udt_pass = B_TRUE, 645 .udt_norm_addr = 0x40000000, 646 .udt_sock = 0, 647 .udt_die = 0, 648 .udt_comp = 1, 649 .udt_dimm_no = 0, 650 .udt_dimm_col = 0x0, 651 .udt_dimm_row = 0x2000, 652 .udt_dimm_bank = 0, 653 .udt_dimm_bank_group = 0, 654 .udt_dimm_subchan = 0, 655 .udt_dimm_rm = 0, 656 .udt_dimm_cs = 0 657 }, { 658 .udt_desc = "DRAM Hole DFv4 4ch Shenanigans (3)", 659 .udt_umc = &zen_umc_hole_dfv4, 660 .udt_pa = 0x100003000, 661 .udt_pass = B_TRUE, 662 .udt_norm_addr = 0x40000000, 663 .udt_sock = 0, 664 .udt_die = 0, 665 .udt_comp = 2, 666 .udt_dimm_no = 0, 667 .udt_dimm_col = 0x0, 668 .udt_dimm_row = 0x2000, 669 .udt_dimm_bank = 0, 670 .udt_dimm_bank_group = 0, 671 .udt_dimm_subchan = 0, 672 .udt_dimm_rm = 0, 673 .udt_dimm_cs = 0 674 }, { 675 .udt_desc = NULL 676 } }; 677