1/* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21/* 22 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26#pragma ident "%Z%%M% %I% %E% SMI" 27 28#pragma dictionary "SUN4U" 29 30#define AGENT_ID_MASK 0x1f 31#define AGENT_ID_SHIFT 24 32 33#define HB_FIT 1000 34#define HBUS_FIT 1000 35#define PCI_BUS_FIT 500 36#define PCI_DEV_FIT 1000 37#define CPU_FIT 500 38 39#define PCI_HB_DEV_PATH hostbridge/pcibus/pcidev[32]/pcifn[0] 40 41fru hostbridge; 42asru hostbridge; 43 44event fault.io.xmits@hostbridge, 45 FITrate=HB_FIT, FRU=hostbridge, ASRU=hostbridge; 46 47event error.io.xmits.saf.dstat@hostbridge; 48event error.io.xmits.saf.to@hostbridge; 49event error.io.xmits.saf.bus@hostbridge; 50event error.io.xmits.ecc.thresh@hostbridge; 51event error.io.pci.device-ta@hostbridge/pcibus/pcidev/pcifn; 52 53event ereport.io.xmits.saf.ape@hostbridge{within(5s)}; 54event ereport.io.xmits.saf.to@hostbridge{within(5s)}; 55event ereport.io.xmits.saf.bus@hostbridge{within(5s)}; 56event ereport.io.xmits.saf.bca@hostbridge{within(5s)}; 57event ereport.io.xmits.saf.bcb@hostbridge{within(5s)}; 58event ereport.io.xmits.saf.ciq-to@hostbridge{within(5s)}; 59event ereport.io.xmits.saf.lpq-to@hostbridge{within(5s)}; 60event ereport.io.xmits.saf.sfpq-to@hostbridge{within(5s)}; 61event ereport.io.xmits.ecc.pce@hostbridge{within(5s)}; 62event ereport.io.xmits.ecc.pue@hostbridge{within(5s)}; 63event ereport.io.xmits.ecc.s-pce@hostbridge{within(5s)}; 64event ereport.io.xmits.ecc.s-pue@hostbridge{within(5s)}; 65event ereport.io.xmits.saf.para@hostbridge{within(5s)}; 66event ereport.io.xmits.saf.parb@hostbridge{within(5s)}; 67event ereport.io.xmits.saf.pars@hostbridge{within(5s)}; 68event ereport.io.xmits.saf.plla@hostbridge{within(5s)}; 69event ereport.io.xmits.saf.pllb@hostbridge{within(5s)}; 70event ereport.io.xmits.saf.plls@hostbridge{within(5s)}; 71event ereport.io.xmits.ecc.thresh@hostbridge{within(5s)}; 72event ereport.io.xmits.saf.dstat@hostbridge{within(5s)}; 73event ereport.io.xmits.pbmx.stdst@PCI_HB_DEV_PATH{within(5s)}; 74event ereport.io.xmits.pbmx.cndst@PCI_HB_DEV_PATH{within(5s)}; 75event ereport.io.xmits.pbmx.tato@PCI_HB_DEV_PATH{within(5s)}; 76event ereport.io.xmits.pbmx.stmmu@PCI_HB_DEV_PATH{within(5s)}; 77event ereport.io.xmits.pbmx.cnmmu@PCI_HB_DEV_PATH{within(5s)}; 78 79/* 80 * A faulty Xmits hostbridge may cause: 81 * 82 * - para: a parity error on the internal memories of PCI block A. 83 * - parb: a parity error on the internal memories of PCI block B. 84 * - pars: a parity error on the internal memories of the Safari block. 85 * - plla: a PLL lock error on the PCIA Leaf PLL. 86 * - pllb: a PLL lock error on the PCIB Leaf PLL. 87 * - plls: a PLL lock error on the Safari block PLL. 88 * - stdst a streaming DMA split completion encounters a DSTAT error 89 * - cndst a consistant DMA split completion encounters a DSTAT error 90 * - bca: bad safari command from PCI block A. 91 * - bcb: bad safari command from PCI block B. 92 * - ciq-to: coherent input queue timeout. 93 * - lpq-to: local PIO queue timeout. 94 * - sfpq-to: safari foreign PIO queue timeout. 95 * - ape: address parity error. 96 * - pue: PIO uncorrectable error, bad reader. 97 * - s-pue: secondary PIO UE, bad reader. 98 * - ecc: multiple PIO CEs. 99 * - to: safari bus timeout. 100 * - bus: safari bus error. 101 * - dstat: errant dstat on incoming data. 102 * 103 * The to, bus and dstat errors can cause a target abort to be sent onto the 104 * pci bus in response to a dma request. We represent this using a device-ta 105 * error to propagate into the generic pci.esc rules. 106 */ 107prop fault.io.xmits@hostbridge (0)-> 108 ereport.io.xmits.saf.para@hostbridge, 109 ereport.io.xmits.saf.parb@hostbridge, 110 ereport.io.xmits.saf.pars@hostbridge, 111 ereport.io.xmits.saf.plla@hostbridge, 112 ereport.io.xmits.saf.pllb@hostbridge, 113 ereport.io.xmits.saf.plls@hostbridge, 114 ereport.io.xmits.saf.bca@hostbridge, 115 ereport.io.xmits.saf.bcb@hostbridge, 116 ereport.io.xmits.saf.ciq-to@hostbridge, 117 ereport.io.xmits.saf.lpq-to@hostbridge, 118 ereport.io.xmits.saf.sfpq-to@hostbridge, 119 ereport.io.xmits.saf.ape@hostbridge, 120 ereport.io.xmits.ecc.pue@hostbridge, 121 ereport.io.xmits.ecc.s-pue@hostbridge, 122 ereport.io.xmits.pbmx.stdst@PCI_HB_DEV_PATH, 123 ereport.io.xmits.pbmx.cndst@PCI_HB_DEV_PATH, 124 error.io.xmits.ecc.thresh@hostbridge, 125 error.io.xmits.saf.to@hostbridge, 126 error.io.xmits.saf.bus@hostbridge, 127 error.io.xmits.saf.dstat@hostbridge; 128 129prop error.io.xmits.ecc.thresh@hostbridge (2)-> 130 ereport.io.xmits.ecc.thresh@hostbridge, 131 ereport.io.xmits.ecc.pce@hostbridge; 132 133prop error.io.xmits.saf.to@hostbridge (2)-> 134 ereport.io.xmits.saf.to@hostbridge, 135 error.io.pci.device-ta@PCI_HB_DEV_PATH; 136 137prop error.io.xmits.saf.bus@hostbridge (2)-> 138 ereport.io.xmits.saf.bus@hostbridge, 139 error.io.pci.device-ta@PCI_HB_DEV_PATH; 140 141prop error.io.xmits.saf.dstat@hostbridge (1)-> 142 ereport.io.xmits.saf.dstat@hostbridge; 143 144prop error.io.xmits.saf.dstat@hostbridge (0)-> 145 error.io.pci.device-ta@PCI_HB_DEV_PATH; 146 147engine serd.io.xmits.ecc@hostbridge, 148 N=3, T=1day, method=persistent, 149 trip=ereport.io.xmits.ecc.thresh@hostbridge; 150 151event upset.io.xmits@hostbridge, 152 engine=serd.io.xmits.ecc@hostbridge; 153 154/* 155 * An upset xmits may cause: 156 * 157 * - pce: PIO correctable error. 158 */ 159prop upset.io.xmits@hostbridge (0)-> 160 ereport.io.xmits.ecc.pce@hostbridge; 161 162fru cpu; 163 164event fault.io.datapath@cpu, FITrate=CPU_FIT, FRU=cpu, retire=0; 165 166event error.io.cpu.ecc.thresh@cpu; 167event ereport.io.xmits.saf.ssm-dis@hostbridge{within(5s)}; 168 169/* 170 * A faulty CPU may cause: 171 * 172 * - to: safari bus timeout. 173 * - bus: safari bus error. 174 * - dstat: incorrect dstat sent to hostbridge. 175 * - ssm-dis: ssm command sent to hostbridge when not enabled. 176 * - ape: safari address parity error. 177 * - pue: PIO uncorrectable error. 178 * - ecc: multiple PIO CEs. 179 */ 180prop fault.io.datapath@cpu (0)-> 181 error.io.xmits.saf.to@hostbridge, 182 error.io.xmits.saf.bus@hostbridge, 183 error.io.xmits.saf.dstat@hostbridge, 184 ereport.io.xmits.saf.ssm-dis@hostbridge, 185 ereport.io.xmits.saf.ape@hostbridge; 186 187prop fault.io.datapath@cpu[cpuid] (0)-> 188 ereport.io.xmits.ecc.pue@hostbridge 189 {((payloadprop("ecc-afsr") >> AGENT_ID_SHIFT) & AGENT_ID_MASK) == cpuid}; 190 191prop fault.io.datapath@cpu (0)-> 192 error.io.cpu.ecc.thresh@cpu; 193 194prop error.io.cpu.ecc.thresh@cpu (1)-> 195 ereport.io.xmits.ecc.thresh@hostbridge<>; 196 197prop error.io.cpu.ecc.thresh@cpu[cpuid] (1)-> 198 ereport.io.xmits.ecc.pce@hostbridge<> 199 {((payloadprop("ecc-afsr") >> AGENT_ID_SHIFT) & AGENT_ID_MASK) == cpuid}; 200 201event fault.io.hbus@hostbridge, 202 FITrate=HBUS_FIT, FRU=hostbridge, ASRU=hostbridge; 203 204/* 205 * A faulty host bus may cause: 206 * 207 * - ape: address parity error. 208 * - pue: PIO uncorrectable error. 209 * - s-pue: secondary PIO UE. 210 * - ecc: multiple PIO CEs. 211 */ 212prop fault.io.hbus@hostbridge (0)-> 213 ereport.io.xmits.saf.ape@hostbridge, 214 ereport.io.xmits.ecc.pue@hostbridge, 215 ereport.io.xmits.ecc.s-pue@hostbridge, 216 error.io.xmits.ecc.thresh@hostbridge; 217 218/* 219 * A defective PCI driver may cause: 220 * 221 * - um: safari unmapped address error. 222 * - mmu: a iommu translation error. 223 */ 224event error.io.pci.badreq-pw-u@hostbridge/pcibus/pcidev/pcifn; 225event error.io.pci.badreq-drw-u@hostbridge/pcibus/pcidev/pcifn; 226 227event ereport.io.xmits.mmu@hostbridge/pcibus/pcidev/pcifn{within(5s)}; 228event ereport.io.xmits.saf.um@hostbridge{within(5s)}; 229event ereport.io.pci.rserr@hostbridge/pcibus/pcidev/pcifn{within(5s)}; 230 231prop error.io.pci.badreq-pw-u@hostbridge/pcibus/pcidev/pcifn (0)-> 232 ereport.io.xmits.saf.um@hostbridge; 233 234prop error.io.pci.badreq-pw-u@hostbridge/pcibus/pcidev/pcifn (0)-> 235 ereport.io.xmits.mmu@PCI_HB_DEV_PATH; 236 237prop error.io.pci.badreq-drw-u@hostbridge/pcibus/pcidev/pcifn (0)-> 238 ereport.io.xmits.saf.um@hostbridge; 239 240prop error.io.pci.badreq-drw-u@hostbridge/pcibus/pcidev/pcifn (0)-> 241 ereport.io.xmits.mmu@PCI_HB_DEV_PATH; 242 243event defect.io.pci.driver@hostbridge; 244 245/* 246 * A defective PCI nexus driver may cause: 247 * 248 * - stmmu: A streaming DMA split completion transaction 249 * encounters an MMU error. 250 * - cnmmu: A consistant DMA split completion transaction 251 * encounters an MMU error. 252 */ 253prop defect.io.pci.driver@hostbridge (0)-> 254 ereport.io.xmits.pbmx.stmmu@PCI_HB_DEV_PATH, 255 ereport.io.xmits.pbmx.cnmmu@PCI_HB_DEV_PATH; 256 257fru pcibus; 258asru pcibus; 259 260event fault.io.pci.bus@hostbridge/pcibus, 261 FITrate=PCI_BUS_FIT, FRU=pcibus, ASRU=pcibus; 262 263event ereport.io.xmits.bu@hostbridge/pcibus/pcidev/pcifn{within(5s)}; 264event ereport.io.xmits.s-bu@hostbridge/pcibus/pcidev/pcifn{within(5s)}; 265 266/* 267 * A faulty PCI bus may cause: 268 * 269 * - bu: PCI bus unusable error. 270 * - s-bu: secondary PCI bus unusable error. 271 * - tato: DMA split completion target timeout error 272 */ 273prop fault.io.pci.bus@hostbridge/pcibus (0)-> 274 ereport.io.xmits.bu@PCI_HB_DEV_PATH, 275 ereport.io.xmits.s-bu@PCI_HB_DEV_PATH, 276 ereport.io.xmits.pbmx.tato@PCI_HB_DEV_PATH; 277 278fru pcibus/pcidev; 279asru pcibus/pcidev/pcifn; 280 281event fault.io.pci.device-interr@hostbridge/pcibus/pcidev/pcifn, 282 FITrate=PCI_DEV_FIT, FRU=pcibus/pcidev, ASRU=pcibus/pcidev/pcifn; 283 284event fault.io.pci.device-interr@pcibus/pcidev/pcifn, 285 FITrate=PCI_DEV_FIT, FRU=pcibus/pcidev, ASRU=pcibus/pcidev/pcifn; 286 287event error.io.xmits.pbm.rl@hostbridge/pcibus/pcidev/pcifn; 288event error.io.xmits.pbm.rl@pcibus/pcidev/pcifn; 289event error.io.xmits.pbm.rl@pcibus/pcidev/pcifn/pcibus/pcidev/pcifn; 290event error.io.xmits.pbm.target-rl@pcibus/pcidev/pcifn; 291event error.io.xmits.pbm.target-rl@pcibus/pcidev/pcifn/pcibus/pcidev/pcifn; 292event error.io.xmits.pbm.tto@hostbridge/pcibus/pcidev/pcifn; 293event error.io.xmits.pbm.target-tto@hostbridge/pcibus/pcidev/pcifn; 294event error.io.xmits.pbm.target-tto@pcibus/pcidev/pcifn; 295event error.io.xmits.pbm.target-tto@pcibus/pcidev/pcifn/pcibus/pcidev/pcifn; 296event error.xmits.cpu.berr@cpu; 297event error.io.pci.ma-u@hostbridge/pcibus/pcidev/pcifn; 298event error.io.pci.perr-pw-u@hostbridge/pcibus/pcidev/pcifn; 299event error.io.pci.perr-dw-u@hostbridge/pcibus/pcidev/pcifn; 300event error.io.pci.dpdata-dr-u@hostbridge/pcibus/pcidev/pcifn; 301event error.io.pci.ta-u@hostbridge/pcibus/pcidev/pcifn; 302event error.io.pci.serr-u@hostbridge/pcibus/pcidev/pcifn; 303event error.io.pci.retry-to-d@hostbridge/pcibus/pcidev/pcifn; 304 305event ereport.io.xmits.sbh@hostbridge/pcibus/pcidev/pcifn{within(5s)}; 306event ereport.io.xmits.pbm.rl@hostbridge/pcibus/pcidev/pcifn{within(5s)}; 307event ereport.io.xmits.pbm.tto@hostbridge/pcibus/pcidev/pcifn{within(5s)}; 308event ereport.io.xmits.pbm.s-rl@hostbridge/pcibus/pcidev/pcifn{within(5s)}; 309event ereport.io.xmits.pbm.s-tto@hostbridge/pcibus/pcidev/pcifn{within(5s)}; 310event ereport.io.xmits.pbm.s-ma@hostbridge/pcibus/pcidev/pcifn{within(5s)}; 311event ereport.io.xmits.pbm.s-rta@hostbridge/pcibus/pcidev/pcifn{within(5s)}; 312event ereport.io.xmits.pbm.s-mdpe@hostbridge/pcibus/pcidev/pcifn{within(5s)}; 313event ereport.io.xmits.pbm.target-rl@pcibus/pcidev/pcifn{within(5s)}; 314event ereport.io.xmits.pbm.target-tto@pcibus/pcidev/pcifn{within(5s)}; 315event ereport.io.pci.sserr@hostbridge/pcibus/pcidev/pcifn{within(5s)}; 316event ereport.cpu.ultraSPARC-III.berr@cpu{within(5s)}; 317event ereport.cpu.ultraSPARC-IIIplus.berr@cpu{within(5s)}; 318event ereport.cpu.ultraSPARC-IV.berr@cpu{within(5s)}; 319event ereport.cpu.ultraSPARC-IVplus.berr@cpu{within(5s)}; 320 321/* 322 * A faulty PCI device may cause: 323 * 324 * - sbh: a streaming byte hole error. 325 * - rl: it to exceed the number retriesfor a transaction. 326 * - tto: it to not assert trdy# within the alloted timeout. 327 * 328 * For rl and tto, there may be a target- ereport on a child device. For rl, 329 * there may also be an associated dto - the retry-to-d error propagates into 330 * the pci.esc rules to handle this. 331 */ 332prop fault.io.pci.device-interr@hostbridge/pcibus/pcidev/pcifn (0)-> 333 ereport.io.xmits.sbh@PCI_HB_DEV_PATH; 334 335prop fault.io.pci.device-interr@pcibus/pcidev[fromdev]/pcifn (0)-> 336 error.io.xmits.pbm.rl@pcibus/pcidev<todev>/pcifn { 337 fromdev == todev && fromdev != 32 }, 338 error.io.xmits.pbm.target-rl@pcibus/pcidev<todev>/pcifn { 339 fromdev == todev && fromdev != 32 }; 340 341prop error.io.xmits.pbm.rl@pcibus/pcidev/pcifn/pcibus/pcidev/pcifn (1)-> 342 error.io.xmits.pbm.rl@pcibus/pcidev/pcifn; 343 344prop error.io.xmits.pbm.rl@hostbridge/pcibus/pcidev/pcifn (1)-> 345 ereport.io.xmits.pbm.rl@PCI_HB_DEV_PATH, 346 ereport.io.xmits.pbm.s-rl@PCI_HB_DEV_PATH; 347 348prop error.io.xmits.pbm.target-rl@pcibus/pcidev/pcifn (1)-> 349 error.io.xmits.pbm.target-rl@pcibus/pcidev/pcifn/pcibus<>/pcidev<>/pcifn<>; 350 351prop error.io.xmits.pbm.target-rl@pcibus/pcidev/pcifn (0)-> 352 ereport.io.xmits.pbm.target-rl@pcibus/pcidev/pcifn; 353 354prop error.io.xmits.pbm.rl@hostbridge/pcibus/pcidev/pcifn (0)-> 355 error.io.pci.retry-to-d@hostbridge/pcibus/pcidev/pcifn; 356 357prop error.io.xmits.pbm.rl@hostbridge/pcibus/pcidev/pcifn (0)-> 358 error.xmits.cpu.berr@cpu; 359 360prop fault.io.pci.device-interr@hostbridge/pcibus/pcidev[fromdev]/pcifn (0)-> 361 error.io.xmits.pbm.tto@hostbridge/pcibus/pcidev<todev>/pcifn { 362 fromdev == todev && fromdev != 32 }; 363 364prop error.io.xmits.pbm.tto@hostbridge/pcibus/pcidev/pcifn (1)-> 365 ereport.io.xmits.pbm.tto@PCI_HB_DEV_PATH, 366 ereport.io.xmits.pbm.s-tto@PCI_HB_DEV_PATH; 367 368prop error.io.xmits.pbm.tto@hostbridge/pcibus/pcidev/pcifn (1)-> 369 ereport.io.xmits.bu@PCI_HB_DEV_PATH; 370 371prop error.io.xmits.pbm.tto@hostbridge/pcibus/pcidev/pcifn (1)-> 372 error.io.xmits.pbm.target-tto@hostbridge/pcibus/pcidev/pcifn; 373 374prop error.io.xmits.pbm.target-tto@pcibus/pcidev/pcifn (0)-> 375 ereport.io.xmits.pbm.target-tto@pcibus/pcidev/pcifn; 376 377prop error.io.xmits.pbm.target-tto@pcibus/pcidev/pcifn (1)-> 378 error.io.xmits.pbm.target-tto@pcibus/pcidev/pcifn/pcibus<>/pcidev<>/pcifn<>; 379 380/* 381 * Need to add the following xmits specific propagations to complete the PCI 382 * fault tree. These are to allow propagations to secondary errors and cpu 383 * bus errors, and to represent the way the chip can raise both rserr and sserr 384 * on detection of SERR# 385 */ 386prop error.io.pci.ma-u@hostbridge/pcibus/pcidev/pcifn (0)-> 387 ereport.io.xmits.pbm.s-ma@PCI_HB_DEV_PATH; 388 389prop error.io.pci.ta-u@hostbridge/pcibus/pcidev/pcifn (0)-> 390 ereport.io.xmits.pbm.s-rta@PCI_HB_DEV_PATH; 391 392prop error.io.pci.perr-dw-u@hostbridge/pcibus/pcidev/pcifn (0)-> 393 ereport.io.xmits.pbm.s-mdpe@PCI_HB_DEV_PATH; 394 395prop error.io.pci.perr-pw-u@hostbridge/pcibus/pcidev/pcifn (0)-> 396 ereport.io.xmits.pbm.s-mdpe@PCI_HB_DEV_PATH; 397 398prop error.io.pci.dpdata-dr-u@hostbridge/pcibus/pcidev/pcifn (0)-> 399 ereport.io.xmits.pbm.s-mdpe@PCI_HB_DEV_PATH; 400 401prop error.io.pci.ta-u@hostbridge/pcibus/pcidev/pcifn (0)-> 402 error.xmits.cpu.berr@cpu; 403 404prop error.io.pci.dpdata-dr-u@hostbridge/pcibus/pcidev/pcifn (0)-> 405 error.xmits.cpu.berr@cpu; 406 407prop error.io.pci.ma-u@hostbridge/pcibus/pcidev/pcifn (0)-> 408 error.xmits.cpu.berr@cpu; 409 410prop error.io.pci.serr-u@hostbridge/pcibus/pcidev/pcifn (1)-> 411 ereport.io.pci.rserr@PCI_HB_DEV_PATH; 412 413prop error.io.pci.serr-u@hostbridge/pcibus/pcidev/pcifn (0)-> 414 ereport.io.pci.sserr@PCI_HB_DEV_PATH; 415 416prop error.xmits.cpu.berr@cpu (1)-> 417 ereport.cpu.ultraSPARC-III.berr@cpu, 418 ereport.cpu.ultraSPARC-IIIplus.berr@cpu, 419 ereport.cpu.ultraSPARC-IV.berr@cpu, 420 ereport.cpu.ultraSPARC-IVplus.berr@cpu; 421 422event error.io.xmits.ecc.drue@hostbridge; 423event ereport.io.xmits.ecc.drue@hostbridge{within(5s)}; 424event ereport.io.xmits.nodiag@hostbridge; 425 426/* 427 * Upset used to hide ereports that can not be currently diagnosed. 428 * 429 * The drue error can cause a target abort to be sent onto the 430 * pci bus in response to a dma request. We represent this using a device-ta 431 * error to propagate into the generic pci.esc rules. 432 */ 433engine serd.io.xmits.nodiag@hostbridge, 434 N=1000, T=1hour, method=persistent, 435 trip=ereport.io.xmits.nodiag@hostbridge; 436 437event upset.io.xmits.nodiag@hostbridge, 438 engine=serd.io.xmits.nodiag@hostbridge; 439 440prop upset.io.xmits.nodiag@hostbridge (0)-> 441 ereport.io.xmits.ecc.s-pce@hostbridge, 442 error.io.xmits.ecc.drue@hostbridge, 443 ereport.io.xmits.nodiag@hostbridge; 444 445prop error.io.xmits.ecc.drue@hostbridge (1)-> 446 ereport.io.xmits.ecc.drue@hostbridge; 447 448prop error.io.xmits.ecc.drue@hostbridge (0)-> 449 error.io.pci.device-ta@PCI_HB_DEV_PATH; 450