xref: /linux/drivers/iio/adc/xilinx-xadc.h (revision 0ea5c948cb64bab5bc7a5516774eb8536f05aa0d)
1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3  * Xilinx XADC driver
4  *
5  * Copyright 2013 Analog Devices Inc.
6  *  Author: Lars-Peter Clausen <lars@metafoo.de>
7  */
8 
9 #ifndef __IIO_XILINX_XADC__
10 #define __IIO_XILINX_XADC__
11 
12 #include <linux/interrupt.h>
13 #include <linux/mutex.h>
14 #include <linux/spinlock.h>
15 
16 struct iio_dev;
17 struct clk;
18 struct xadc_ops;
19 struct platform_device;
20 
21 void xadc_handle_events(struct iio_dev *indio_dev, unsigned long events);
22 
23 int xadc_read_event_config(struct iio_dev *indio_dev,
24 	const struct iio_chan_spec *chan, enum iio_event_type type,
25 	enum iio_event_direction dir);
26 int xadc_write_event_config(struct iio_dev *indio_dev,
27 	const struct iio_chan_spec *chan, enum iio_event_type type,
28 	enum iio_event_direction dir, int state);
29 int xadc_read_event_value(struct iio_dev *indio_dev,
30 	const struct iio_chan_spec *chan, enum iio_event_type type,
31 	enum iio_event_direction dir, enum iio_event_info info,
32 	int *val, int *val2);
33 int xadc_write_event_value(struct iio_dev *indio_dev,
34 	const struct iio_chan_spec *chan, enum iio_event_type type,
35 	enum iio_event_direction dir, enum iio_event_info info,
36 	int val, int val2);
37 
38 enum xadc_external_mux_mode {
39 	XADC_EXTERNAL_MUX_NONE,
40 	XADC_EXTERNAL_MUX_SINGLE,
41 	XADC_EXTERNAL_MUX_DUAL,
42 };
43 
44 struct xadc {
45 	void __iomem *base;
46 	struct clk *clk;
47 
48 	const struct xadc_ops *ops;
49 
50 	uint16_t threshold[16];
51 	uint16_t temp_hysteresis;
52 	unsigned int alarm_mask;
53 
54 	uint16_t *data;
55 
56 	struct iio_trigger *trigger;
57 	struct iio_trigger *convst_trigger;
58 	struct iio_trigger *samplerate_trigger;
59 
60 	enum xadc_external_mux_mode external_mux_mode;
61 
62 	unsigned int zynq_masked_alarm;
63 	unsigned int zynq_intmask;
64 	struct delayed_work zynq_unmask_work;
65 
66 	struct mutex mutex;
67 	spinlock_t lock;
68 
69 	struct completion completion;
70 };
71 
72 enum xadc_type {
73 	XADC_TYPE_S7, /* Series 7 */
74 	XADC_TYPE_US, /* UltraScale and UltraScale+ */
75 };
76 
77 struct xadc_ops {
78 	int (*read)(struct xadc *xadc, unsigned int reg, uint16_t *val);
79 	int (*write)(struct xadc *xadc, unsigned int reg, uint16_t val);
80 	int (*setup)(struct platform_device *pdev, struct iio_dev *indio_dev,
81 			int irq);
82 	void (*update_alarm)(struct xadc *xadc, unsigned int alarm);
83 	unsigned long (*get_dclk_rate)(struct xadc *xadc);
84 	irqreturn_t (*interrupt_handler)(int irq, void *devid);
85 
86 	unsigned int flags;
87 	enum xadc_type type;
88 	int temp_scale;
89 	int temp_offset;
90 };
91 
_xadc_read_adc_reg(struct xadc * xadc,unsigned int reg,uint16_t * val)92 static inline int _xadc_read_adc_reg(struct xadc *xadc, unsigned int reg,
93 	uint16_t *val)
94 {
95 	lockdep_assert_held(&xadc->mutex);
96 	return xadc->ops->read(xadc, reg, val);
97 }
98 
_xadc_write_adc_reg(struct xadc * xadc,unsigned int reg,uint16_t val)99 static inline int _xadc_write_adc_reg(struct xadc *xadc, unsigned int reg,
100 	uint16_t val)
101 {
102 	lockdep_assert_held(&xadc->mutex);
103 	return xadc->ops->write(xadc, reg, val);
104 }
105 
xadc_read_adc_reg(struct xadc * xadc,unsigned int reg,uint16_t * val)106 static inline int xadc_read_adc_reg(struct xadc *xadc, unsigned int reg,
107 	uint16_t *val)
108 {
109 	int ret;
110 
111 	mutex_lock(&xadc->mutex);
112 	ret = _xadc_read_adc_reg(xadc, reg, val);
113 	mutex_unlock(&xadc->mutex);
114 	return ret;
115 }
116 
xadc_write_adc_reg(struct xadc * xadc,unsigned int reg,uint16_t val)117 static inline int xadc_write_adc_reg(struct xadc *xadc, unsigned int reg,
118 	uint16_t val)
119 {
120 	int ret;
121 
122 	mutex_lock(&xadc->mutex);
123 	ret = _xadc_write_adc_reg(xadc, reg, val);
124 	mutex_unlock(&xadc->mutex);
125 	return ret;
126 }
127 
128 /* XADC hardmacro register definitions */
129 #define XADC_REG_TEMP		0x00
130 #define XADC_REG_VCCINT		0x01
131 #define XADC_REG_VCCAUX		0x02
132 #define XADC_REG_VPVN		0x03
133 #define XADC_REG_VREFP		0x04
134 #define XADC_REG_VREFN		0x05
135 #define XADC_REG_VCCBRAM	0x06
136 
137 #define XADC_REG_VCCPINT	0x0d
138 #define XADC_REG_VCCPAUX	0x0e
139 #define XADC_REG_VCCO_DDR	0x0f
140 #define XADC_REG_VAUX(x)	(0x10 + (x))
141 
142 #define XADC_REG_MAX_TEMP	0x20
143 #define XADC_REG_MAX_VCCINT	0x21
144 #define XADC_REG_MAX_VCCAUX	0x22
145 #define XADC_REG_MAX_VCCBRAM	0x23
146 #define XADC_REG_MIN_TEMP	0x24
147 #define XADC_REG_MIN_VCCINT	0x25
148 #define XADC_REG_MIN_VCCAUX	0x26
149 #define XADC_REG_MIN_VCCBRAM	0x27
150 #define XADC_REG_MAX_VCCPINT	0x28
151 #define XADC_REG_MAX_VCCPAUX	0x29
152 #define XADC_REG_MAX_VCCO_DDR	0x2a
153 #define XADC_REG_MIN_VCCPINT	0x2c
154 #define XADC_REG_MIN_VCCPAUX	0x2d
155 #define XADC_REG_MIN_VCCO_DDR	0x2e
156 
157 #define XADC_REG_CONF0		0x40
158 #define XADC_REG_CONF1		0x41
159 #define XADC_REG_CONF2		0x42
160 #define XADC_REG_SEQ(x)		(0x48 + (x))
161 #define XADC_REG_INPUT_MODE(x)	(0x4c + (x))
162 #define XADC_REG_THRESHOLD(x)	(0x50 + (x))
163 
164 #define XADC_REG_FLAG		0x3f
165 
166 #define XADC_CONF0_EC			BIT(9)
167 #define XADC_CONF0_ACQ			BIT(8)
168 #define XADC_CONF0_MUX			BIT(11)
169 #define XADC_CONF0_CHAN(x)		(x)
170 
171 #define XADC_CONF1_SEQ_MASK		(0xf << 12)
172 #define XADC_CONF1_SEQ_DEFAULT		(0 << 12)
173 #define XADC_CONF1_SEQ_SINGLE_PASS	(1 << 12)
174 #define XADC_CONF1_SEQ_CONTINUOUS	(2 << 12)
175 #define XADC_CONF1_SEQ_SINGLE_CHANNEL	(3 << 12)
176 #define XADC_CONF1_SEQ_SIMULTANEOUS	(4 << 12)
177 #define XADC_CONF1_SEQ_INDEPENDENT	(8 << 12)
178 #define XADC_CONF1_ALARM_MASK		0x0f0f
179 
180 #define XADC_CONF2_DIV_MASK	0xff00
181 #define XADC_CONF2_DIV_OFFSET	8
182 
183 #define XADC_CONF2_PD_MASK	(0x3 << 4)
184 #define XADC_CONF2_PD_NONE	(0x0 << 4)
185 #define XADC_CONF2_PD_ADC_B	(0x2 << 4)
186 #define XADC_CONF2_PD_BOTH	(0x3 << 4)
187 
188 #define XADC_ALARM_TEMP_MASK		BIT(0)
189 #define XADC_ALARM_VCCINT_MASK		BIT(1)
190 #define XADC_ALARM_VCCAUX_MASK		BIT(2)
191 #define XADC_ALARM_OT_MASK		BIT(3)
192 #define XADC_ALARM_VCCBRAM_MASK		BIT(4)
193 #define XADC_ALARM_VCCPINT_MASK		BIT(5)
194 #define XADC_ALARM_VCCPAUX_MASK		BIT(6)
195 #define XADC_ALARM_VCCODDR_MASK		BIT(7)
196 
197 #define XADC_THRESHOLD_TEMP_MAX		0x0
198 #define XADC_THRESHOLD_VCCINT_MAX	0x1
199 #define XADC_THRESHOLD_VCCAUX_MAX	0x2
200 #define XADC_THRESHOLD_OT_MAX		0x3
201 #define XADC_THRESHOLD_TEMP_MIN		0x4
202 #define XADC_THRESHOLD_VCCINT_MIN	0x5
203 #define XADC_THRESHOLD_VCCAUX_MIN	0x6
204 #define XADC_THRESHOLD_OT_MIN		0x7
205 #define XADC_THRESHOLD_VCCBRAM_MAX	0x8
206 #define XADC_THRESHOLD_VCCPINT_MAX	0x9
207 #define XADC_THRESHOLD_VCCPAUX_MAX	0xa
208 #define XADC_THRESHOLD_VCCODDR_MAX	0xb
209 #define XADC_THRESHOLD_VCCBRAM_MIN	0xc
210 #define XADC_THRESHOLD_VCCPINT_MIN	0xd
211 #define XADC_THRESHOLD_VCCPAUX_MIN	0xe
212 #define XADC_THRESHOLD_VCCODDR_MIN	0xf
213 
214 #endif
215