1 /*
2 * Copyright © 2013 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Author: Jani Nikula <jani.nikula@intel.com>
24 */
25
26 #include <linux/dmi.h>
27 #include <linux/slab.h>
28
29 #include <drm/drm_atomic_helper.h>
30 #include <drm/drm_crtc.h>
31 #include <drm/drm_edid.h>
32 #include <drm/drm_mipi_dsi.h>
33 #include <drm/drm_probe_helper.h>
34
35 #include "i915_drv.h"
36 #include "i915_reg.h"
37 #include "intel_atomic.h"
38 #include "intel_backlight.h"
39 #include "intel_connector.h"
40 #include "intel_crtc.h"
41 #include "intel_de.h"
42 #include "intel_display_types.h"
43 #include "intel_dsi.h"
44 #include "intel_dsi_vbt.h"
45 #include "intel_fifo_underrun.h"
46 #include "intel_panel.h"
47 #include "intel_pfit.h"
48 #include "skl_scaler.h"
49 #include "vlv_dsi.h"
50 #include "vlv_dsi_pll.h"
51 #include "vlv_dsi_regs.h"
52 #include "vlv_sideband.h"
53
54 /* return pixels in terms of txbyteclkhs */
txbyteclkhs(u16 pixels,int bpp,int lane_count,u16 burst_mode_ratio)55 static u16 txbyteclkhs(u16 pixels, int bpp, int lane_count,
56 u16 burst_mode_ratio)
57 {
58 return DIV_ROUND_UP(DIV_ROUND_UP(pixels * bpp * burst_mode_ratio,
59 8 * 100), lane_count);
60 }
61
62 /* return pixels equivalent to txbyteclkhs */
pixels_from_txbyteclkhs(u16 clk_hs,int bpp,int lane_count,u16 burst_mode_ratio)63 static u16 pixels_from_txbyteclkhs(u16 clk_hs, int bpp, int lane_count,
64 u16 burst_mode_ratio)
65 {
66 return DIV_ROUND_UP((clk_hs * lane_count * 8 * 100),
67 (bpp * burst_mode_ratio));
68 }
69
pixel_format_from_register_bits(u32 fmt)70 static enum mipi_dsi_pixel_format pixel_format_from_register_bits(u32 fmt)
71 {
72 switch (fmt) {
73 case VID_MODE_FORMAT_RGB888:
74 return MIPI_DSI_FMT_RGB888;
75 case VID_MODE_FORMAT_RGB666:
76 return MIPI_DSI_FMT_RGB666;
77 case VID_MODE_FORMAT_RGB666_PACKED:
78 return MIPI_DSI_FMT_RGB666_PACKED;
79 case VID_MODE_FORMAT_RGB565:
80 return MIPI_DSI_FMT_RGB565;
81 default:
82 MISSING_CASE(fmt);
83 return MIPI_DSI_FMT_RGB666;
84 }
85 }
86
vlv_dsi_wait_for_fifo_empty(struct intel_dsi * intel_dsi,enum port port)87 void vlv_dsi_wait_for_fifo_empty(struct intel_dsi *intel_dsi, enum port port)
88 {
89 struct intel_display *display = to_intel_display(&intel_dsi->base);
90 u32 mask;
91
92 mask = LP_CTRL_FIFO_EMPTY | HS_CTRL_FIFO_EMPTY |
93 LP_DATA_FIFO_EMPTY | HS_DATA_FIFO_EMPTY;
94
95 if (intel_de_wait_for_set(display, MIPI_GEN_FIFO_STAT(display, port),
96 mask, 100))
97 drm_err(display->drm, "DPI FIFOs are not empty\n");
98 }
99
write_data(struct intel_display * display,i915_reg_t reg,const u8 * data,u32 len)100 static void write_data(struct intel_display *display,
101 i915_reg_t reg,
102 const u8 *data, u32 len)
103 {
104 u32 i, j;
105
106 for (i = 0; i < len; i += 4) {
107 u32 val = 0;
108
109 for (j = 0; j < min_t(u32, len - i, 4); j++)
110 val |= *data++ << 8 * j;
111
112 intel_de_write(display, reg, val);
113 }
114 }
115
read_data(struct intel_display * display,i915_reg_t reg,u8 * data,u32 len)116 static void read_data(struct intel_display *display,
117 i915_reg_t reg,
118 u8 *data, u32 len)
119 {
120 u32 i, j;
121
122 for (i = 0; i < len; i += 4) {
123 u32 val = intel_de_read(display, reg);
124
125 for (j = 0; j < min_t(u32, len - i, 4); j++)
126 *data++ = val >> 8 * j;
127 }
128 }
129
intel_dsi_host_transfer(struct mipi_dsi_host * host,const struct mipi_dsi_msg * msg)130 static ssize_t intel_dsi_host_transfer(struct mipi_dsi_host *host,
131 const struct mipi_dsi_msg *msg)
132 {
133 struct intel_dsi_host *intel_dsi_host = to_intel_dsi_host(host);
134 struct intel_dsi *intel_dsi = intel_dsi_host->intel_dsi;
135 struct intel_display *display = to_intel_display(&intel_dsi->base);
136 enum port port = intel_dsi_host->port;
137 struct mipi_dsi_packet packet;
138 ssize_t ret;
139 const u8 *header;
140 i915_reg_t data_reg, ctrl_reg;
141 u32 data_mask, ctrl_mask;
142
143 ret = mipi_dsi_create_packet(&packet, msg);
144 if (ret < 0)
145 return ret;
146
147 header = packet.header;
148
149 if (msg->flags & MIPI_DSI_MSG_USE_LPM) {
150 data_reg = MIPI_LP_GEN_DATA(display, port);
151 data_mask = LP_DATA_FIFO_FULL;
152 ctrl_reg = MIPI_LP_GEN_CTRL(display, port);
153 ctrl_mask = LP_CTRL_FIFO_FULL;
154 } else {
155 data_reg = MIPI_HS_GEN_DATA(display, port);
156 data_mask = HS_DATA_FIFO_FULL;
157 ctrl_reg = MIPI_HS_GEN_CTRL(display, port);
158 ctrl_mask = HS_CTRL_FIFO_FULL;
159 }
160
161 /* note: this is never true for reads */
162 if (packet.payload_length) {
163 if (intel_de_wait_for_clear(display, MIPI_GEN_FIFO_STAT(display, port),
164 data_mask, 50))
165 drm_err(display->drm,
166 "Timeout waiting for HS/LP DATA FIFO !full\n");
167
168 write_data(display, data_reg, packet.payload,
169 packet.payload_length);
170 }
171
172 if (msg->rx_len) {
173 intel_de_write(display, MIPI_INTR_STAT(display, port),
174 GEN_READ_DATA_AVAIL);
175 }
176
177 if (intel_de_wait_for_clear(display, MIPI_GEN_FIFO_STAT(display, port),
178 ctrl_mask, 50)) {
179 drm_err(display->drm,
180 "Timeout waiting for HS/LP CTRL FIFO !full\n");
181 }
182
183 intel_de_write(display, ctrl_reg,
184 header[2] << 16 | header[1] << 8 | header[0]);
185
186 /* ->rx_len is set only for reads */
187 if (msg->rx_len) {
188 data_mask = GEN_READ_DATA_AVAIL;
189 if (intel_de_wait_for_set(display, MIPI_INTR_STAT(display, port),
190 data_mask, 50))
191 drm_err(display->drm,
192 "Timeout waiting for read data.\n");
193
194 read_data(display, data_reg, msg->rx_buf, msg->rx_len);
195 }
196
197 /* XXX: fix for reads and writes */
198 return 4 + packet.payload_length;
199 }
200
intel_dsi_host_attach(struct mipi_dsi_host * host,struct mipi_dsi_device * dsi)201 static int intel_dsi_host_attach(struct mipi_dsi_host *host,
202 struct mipi_dsi_device *dsi)
203 {
204 return 0;
205 }
206
intel_dsi_host_detach(struct mipi_dsi_host * host,struct mipi_dsi_device * dsi)207 static int intel_dsi_host_detach(struct mipi_dsi_host *host,
208 struct mipi_dsi_device *dsi)
209 {
210 return 0;
211 }
212
213 static const struct mipi_dsi_host_ops intel_dsi_host_ops = {
214 .attach = intel_dsi_host_attach,
215 .detach = intel_dsi_host_detach,
216 .transfer = intel_dsi_host_transfer,
217 };
218
219 /*
220 * send a video mode command
221 *
222 * XXX: commands with data in MIPI_DPI_DATA?
223 */
dpi_send_cmd(struct intel_dsi * intel_dsi,u32 cmd,bool hs,enum port port)224 static int dpi_send_cmd(struct intel_dsi *intel_dsi, u32 cmd, bool hs,
225 enum port port)
226 {
227 struct intel_display *display = to_intel_display(&intel_dsi->base);
228 u32 mask;
229
230 /* XXX: pipe, hs */
231 if (hs)
232 cmd &= ~DPI_LP_MODE;
233 else
234 cmd |= DPI_LP_MODE;
235
236 /* clear bit */
237 intel_de_write(display, MIPI_INTR_STAT(display, port), SPL_PKT_SENT_INTERRUPT);
238
239 /* XXX: old code skips write if control unchanged */
240 if (cmd == intel_de_read(display, MIPI_DPI_CONTROL(display, port)))
241 drm_dbg_kms(display->drm,
242 "Same special packet %02x twice in a row.\n", cmd);
243
244 intel_de_write(display, MIPI_DPI_CONTROL(display, port), cmd);
245
246 mask = SPL_PKT_SENT_INTERRUPT;
247 if (intel_de_wait_for_set(display, MIPI_INTR_STAT(display, port), mask, 100))
248 drm_err(display->drm,
249 "Video mode command 0x%08x send failed.\n", cmd);
250
251 return 0;
252 }
253
band_gap_reset(struct intel_display * display)254 static void band_gap_reset(struct intel_display *display)
255 {
256 struct drm_i915_private *dev_priv = to_i915(display->drm);
257
258 vlv_flisdsi_get(dev_priv);
259
260 vlv_flisdsi_write(dev_priv, 0x08, 0x0001);
261 vlv_flisdsi_write(dev_priv, 0x0F, 0x0005);
262 vlv_flisdsi_write(dev_priv, 0x0F, 0x0025);
263 udelay(150);
264 vlv_flisdsi_write(dev_priv, 0x0F, 0x0000);
265 vlv_flisdsi_write(dev_priv, 0x08, 0x0000);
266
267 vlv_flisdsi_put(dev_priv);
268 }
269
intel_dsi_compute_config(struct intel_encoder * encoder,struct intel_crtc_state * pipe_config,struct drm_connector_state * conn_state)270 static int intel_dsi_compute_config(struct intel_encoder *encoder,
271 struct intel_crtc_state *pipe_config,
272 struct drm_connector_state *conn_state)
273 {
274 struct intel_display *display = to_intel_display(encoder);
275 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
276 struct intel_connector *intel_connector = intel_dsi->attached_connector;
277 struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
278 int ret;
279
280 drm_dbg_kms(display->drm, "\n");
281 pipe_config->sink_format = INTEL_OUTPUT_FORMAT_RGB;
282 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
283
284 ret = intel_panel_compute_config(intel_connector, adjusted_mode);
285 if (ret)
286 return ret;
287
288 ret = intel_pfit_compute_config(pipe_config, conn_state);
289 if (ret)
290 return ret;
291
292 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
293 return -EINVAL;
294
295 /* DSI uses short packets for sync events, so clear mode flags for DSI */
296 adjusted_mode->flags = 0;
297
298 if (intel_dsi->pixel_format == MIPI_DSI_FMT_RGB888)
299 pipe_config->pipe_bpp = 24;
300 else
301 pipe_config->pipe_bpp = 18;
302
303 if (display->platform.geminilake || display->platform.broxton) {
304 /* Enable Frame time stamp based scanline reporting */
305 pipe_config->mode_flags |=
306 I915_MODE_FLAG_GET_SCANLINE_FROM_TIMESTAMP;
307
308 /* Dual link goes to DSI transcoder A. */
309 if (intel_dsi->ports == BIT(PORT_C))
310 pipe_config->cpu_transcoder = TRANSCODER_DSI_C;
311 else
312 pipe_config->cpu_transcoder = TRANSCODER_DSI_A;
313
314 ret = bxt_dsi_pll_compute(encoder, pipe_config);
315 if (ret)
316 return -EINVAL;
317 } else {
318 ret = vlv_dsi_pll_compute(encoder, pipe_config);
319 if (ret)
320 return -EINVAL;
321 }
322
323 pipe_config->clock_set = true;
324
325 return 0;
326 }
327
glk_dsi_enable_io(struct intel_encoder * encoder)328 static bool glk_dsi_enable_io(struct intel_encoder *encoder)
329 {
330 struct intel_display *display = to_intel_display(encoder);
331 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
332 enum port port;
333 bool cold_boot = false;
334
335 /* Set the MIPI mode
336 * If MIPI_Mode is off, then writing to LP_Wake bit is not reflecting.
337 * Power ON MIPI IO first and then write into IO reset and LP wake bits
338 */
339 for_each_dsi_port(port, intel_dsi->ports)
340 intel_de_rmw(display, MIPI_CTRL(display, port), 0, GLK_MIPIIO_ENABLE);
341
342 /* Put the IO into reset */
343 intel_de_rmw(display, MIPI_CTRL(display, PORT_A), GLK_MIPIIO_RESET_RELEASED, 0);
344
345 /* Program LP Wake */
346 for_each_dsi_port(port, intel_dsi->ports) {
347 u32 tmp = intel_de_read(display, MIPI_DEVICE_READY(display, port));
348
349 intel_de_rmw(display, MIPI_CTRL(display, port),
350 GLK_LP_WAKE, (tmp & DEVICE_READY) ? GLK_LP_WAKE : 0);
351 }
352
353 /* Wait for Pwr ACK */
354 for_each_dsi_port(port, intel_dsi->ports) {
355 if (intel_de_wait_for_set(display, MIPI_CTRL(display, port),
356 GLK_MIPIIO_PORT_POWERED, 20))
357 drm_err(display->drm, "MIPIO port is powergated\n");
358 }
359
360 /* Check for cold boot scenario */
361 for_each_dsi_port(port, intel_dsi->ports) {
362 cold_boot |=
363 !(intel_de_read(display, MIPI_DEVICE_READY(display, port)) & DEVICE_READY);
364 }
365
366 return cold_boot;
367 }
368
glk_dsi_device_ready(struct intel_encoder * encoder)369 static void glk_dsi_device_ready(struct intel_encoder *encoder)
370 {
371 struct intel_display *display = to_intel_display(encoder);
372 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
373 enum port port;
374
375 /* Wait for MIPI PHY status bit to set */
376 for_each_dsi_port(port, intel_dsi->ports) {
377 if (intel_de_wait_for_set(display, MIPI_CTRL(display, port),
378 GLK_PHY_STATUS_PORT_READY, 20))
379 drm_err(display->drm, "PHY is not ON\n");
380 }
381
382 /* Get IO out of reset */
383 intel_de_rmw(display, MIPI_CTRL(display, PORT_A), 0, GLK_MIPIIO_RESET_RELEASED);
384
385 /* Get IO out of Low power state*/
386 for_each_dsi_port(port, intel_dsi->ports) {
387 if (!(intel_de_read(display, MIPI_DEVICE_READY(display, port)) & DEVICE_READY)) {
388 intel_de_rmw(display, MIPI_DEVICE_READY(display, port),
389 ULPS_STATE_MASK, DEVICE_READY);
390 usleep_range(10, 15);
391 } else {
392 /* Enter ULPS */
393 intel_de_rmw(display, MIPI_DEVICE_READY(display, port),
394 ULPS_STATE_MASK, ULPS_STATE_ENTER | DEVICE_READY);
395
396 /* Wait for ULPS active */
397 if (intel_de_wait_for_clear(display, MIPI_CTRL(display, port),
398 GLK_ULPS_NOT_ACTIVE, 20))
399 drm_err(display->drm, "ULPS not active\n");
400
401 /* Exit ULPS */
402 intel_de_rmw(display, MIPI_DEVICE_READY(display, port),
403 ULPS_STATE_MASK, ULPS_STATE_EXIT | DEVICE_READY);
404
405 /* Enter Normal Mode */
406 intel_de_rmw(display, MIPI_DEVICE_READY(display, port),
407 ULPS_STATE_MASK,
408 ULPS_STATE_NORMAL_OPERATION | DEVICE_READY);
409
410 intel_de_rmw(display, MIPI_CTRL(display, port), GLK_LP_WAKE, 0);
411 }
412 }
413
414 /* Wait for Stop state */
415 for_each_dsi_port(port, intel_dsi->ports) {
416 if (intel_de_wait_for_set(display, MIPI_CTRL(display, port),
417 GLK_DATA_LANE_STOP_STATE, 20))
418 drm_err(display->drm,
419 "Date lane not in STOP state\n");
420 }
421
422 /* Wait for AFE LATCH */
423 for_each_dsi_port(port, intel_dsi->ports) {
424 if (intel_de_wait_for_set(display, BXT_MIPI_PORT_CTRL(port),
425 AFE_LATCHOUT, 20))
426 drm_err(display->drm,
427 "D-PHY not entering LP-11 state\n");
428 }
429 }
430
bxt_dsi_device_ready(struct intel_encoder * encoder)431 static void bxt_dsi_device_ready(struct intel_encoder *encoder)
432 {
433 struct intel_display *display = to_intel_display(encoder);
434 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
435 enum port port;
436 u32 val;
437
438 drm_dbg_kms(display->drm, "\n");
439
440 /* Enable MIPI PHY transparent latch */
441 for_each_dsi_port(port, intel_dsi->ports) {
442 intel_de_rmw(display, BXT_MIPI_PORT_CTRL(port), 0, LP_OUTPUT_HOLD);
443 usleep_range(2000, 2500);
444 }
445
446 /* Clear ULPS and set device ready */
447 for_each_dsi_port(port, intel_dsi->ports) {
448 val = intel_de_read(display, MIPI_DEVICE_READY(display, port));
449 val &= ~ULPS_STATE_MASK;
450 intel_de_write(display, MIPI_DEVICE_READY(display, port), val);
451 usleep_range(2000, 2500);
452 val |= DEVICE_READY;
453 intel_de_write(display, MIPI_DEVICE_READY(display, port), val);
454 }
455 }
456
vlv_dsi_device_ready(struct intel_encoder * encoder)457 static void vlv_dsi_device_ready(struct intel_encoder *encoder)
458 {
459 struct intel_display *display = to_intel_display(encoder);
460 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
461 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
462 enum port port;
463
464 drm_dbg_kms(display->drm, "\n");
465
466 vlv_flisdsi_get(dev_priv);
467 /* program rcomp for compliance, reduce from 50 ohms to 45 ohms
468 * needed everytime after power gate */
469 vlv_flisdsi_write(dev_priv, 0x04, 0x0004);
470 vlv_flisdsi_put(dev_priv);
471
472 /* bandgap reset is needed after everytime we do power gate */
473 band_gap_reset(display);
474
475 for_each_dsi_port(port, intel_dsi->ports) {
476
477 intel_de_write(display, MIPI_DEVICE_READY(display, port),
478 ULPS_STATE_ENTER);
479 usleep_range(2500, 3000);
480
481 /* Enable MIPI PHY transparent latch
482 * Common bit for both MIPI Port A & MIPI Port C
483 * No similar bit in MIPI Port C reg
484 */
485 intel_de_rmw(display, VLV_MIPI_PORT_CTRL(PORT_A), 0, LP_OUTPUT_HOLD);
486 usleep_range(1000, 1500);
487
488 intel_de_write(display, MIPI_DEVICE_READY(display, port),
489 ULPS_STATE_EXIT);
490 usleep_range(2500, 3000);
491
492 intel_de_write(display, MIPI_DEVICE_READY(display, port),
493 DEVICE_READY);
494 usleep_range(2500, 3000);
495 }
496 }
497
intel_dsi_device_ready(struct intel_encoder * encoder)498 static void intel_dsi_device_ready(struct intel_encoder *encoder)
499 {
500 struct intel_display *display = to_intel_display(encoder);
501
502 if (display->platform.geminilake)
503 glk_dsi_device_ready(encoder);
504 else if (display->platform.geminilake || display->platform.broxton)
505 bxt_dsi_device_ready(encoder);
506 else
507 vlv_dsi_device_ready(encoder);
508 }
509
glk_dsi_enter_low_power_mode(struct intel_encoder * encoder)510 static void glk_dsi_enter_low_power_mode(struct intel_encoder *encoder)
511 {
512 struct intel_display *display = to_intel_display(encoder);
513 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
514 enum port port;
515
516 /* Enter ULPS */
517 for_each_dsi_port(port, intel_dsi->ports)
518 intel_de_rmw(display, MIPI_DEVICE_READY(display, port),
519 ULPS_STATE_MASK, ULPS_STATE_ENTER | DEVICE_READY);
520
521 /* Wait for MIPI PHY status bit to unset */
522 for_each_dsi_port(port, intel_dsi->ports) {
523 if (intel_de_wait_for_clear(display, MIPI_CTRL(display, port),
524 GLK_PHY_STATUS_PORT_READY, 20))
525 drm_err(display->drm, "PHY is not turning OFF\n");
526 }
527
528 /* Wait for Pwr ACK bit to unset */
529 for_each_dsi_port(port, intel_dsi->ports) {
530 if (intel_de_wait_for_clear(display, MIPI_CTRL(display, port),
531 GLK_MIPIIO_PORT_POWERED, 20))
532 drm_err(display->drm,
533 "MIPI IO Port is not powergated\n");
534 }
535 }
536
glk_dsi_disable_mipi_io(struct intel_encoder * encoder)537 static void glk_dsi_disable_mipi_io(struct intel_encoder *encoder)
538 {
539 struct intel_display *display = to_intel_display(encoder);
540 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
541 enum port port;
542
543 /* Put the IO into reset */
544 intel_de_rmw(display, MIPI_CTRL(display, PORT_A), GLK_MIPIIO_RESET_RELEASED, 0);
545
546 /* Wait for MIPI PHY status bit to unset */
547 for_each_dsi_port(port, intel_dsi->ports) {
548 if (intel_de_wait_for_clear(display, MIPI_CTRL(display, port),
549 GLK_PHY_STATUS_PORT_READY, 20))
550 drm_err(display->drm, "PHY is not turning OFF\n");
551 }
552
553 /* Clear MIPI mode */
554 for_each_dsi_port(port, intel_dsi->ports)
555 intel_de_rmw(display, MIPI_CTRL(display, port), GLK_MIPIIO_ENABLE, 0);
556 }
557
glk_dsi_clear_device_ready(struct intel_encoder * encoder)558 static void glk_dsi_clear_device_ready(struct intel_encoder *encoder)
559 {
560 glk_dsi_enter_low_power_mode(encoder);
561 glk_dsi_disable_mipi_io(encoder);
562 }
563
port_ctrl_reg(struct intel_display * display,enum port port)564 static i915_reg_t port_ctrl_reg(struct intel_display *display, enum port port)
565 {
566 return display->platform.geminilake || display->platform.broxton ?
567 BXT_MIPI_PORT_CTRL(port) : VLV_MIPI_PORT_CTRL(port);
568 }
569
vlv_dsi_clear_device_ready(struct intel_encoder * encoder)570 static void vlv_dsi_clear_device_ready(struct intel_encoder *encoder)
571 {
572 struct intel_display *display = to_intel_display(encoder);
573 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
574 enum port port;
575
576 drm_dbg_kms(display->drm, "\n");
577 for_each_dsi_port(port, intel_dsi->ports) {
578 /* Common bit for both MIPI Port A & MIPI Port C on VLV/CHV */
579 i915_reg_t port_ctrl = display->platform.broxton ?
580 BXT_MIPI_PORT_CTRL(port) : VLV_MIPI_PORT_CTRL(PORT_A);
581
582 intel_de_write(display, MIPI_DEVICE_READY(display, port),
583 DEVICE_READY | ULPS_STATE_ENTER);
584 usleep_range(2000, 2500);
585
586 intel_de_write(display, MIPI_DEVICE_READY(display, port),
587 DEVICE_READY | ULPS_STATE_EXIT);
588 usleep_range(2000, 2500);
589
590 intel_de_write(display, MIPI_DEVICE_READY(display, port),
591 DEVICE_READY | ULPS_STATE_ENTER);
592 usleep_range(2000, 2500);
593
594 /*
595 * On VLV/CHV, wait till Clock lanes are in LP-00 state for MIPI
596 * Port A only. MIPI Port C has no similar bit for checking.
597 */
598 if ((display->platform.broxton || port == PORT_A) &&
599 intel_de_wait_for_clear(display, port_ctrl,
600 AFE_LATCHOUT, 30))
601 drm_err(display->drm, "DSI LP not going Low\n");
602
603 /* Disable MIPI PHY transparent latch */
604 intel_de_rmw(display, port_ctrl, LP_OUTPUT_HOLD, 0);
605 usleep_range(1000, 1500);
606
607 intel_de_write(display, MIPI_DEVICE_READY(display, port), 0x00);
608 usleep_range(2000, 2500);
609 }
610 }
611
intel_dsi_port_enable(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state)612 static void intel_dsi_port_enable(struct intel_encoder *encoder,
613 const struct intel_crtc_state *crtc_state)
614 {
615 struct intel_display *display = to_intel_display(encoder);
616 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
617 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
618 enum port port;
619
620 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) {
621 u32 temp = intel_dsi->pixel_overlap;
622
623 if (display->platform.geminilake || display->platform.broxton) {
624 for_each_dsi_port(port, intel_dsi->ports)
625 intel_de_rmw(display, MIPI_CTRL(display, port),
626 BXT_PIXEL_OVERLAP_CNT_MASK,
627 temp << BXT_PIXEL_OVERLAP_CNT_SHIFT);
628 } else {
629 intel_de_rmw(display, VLV_CHICKEN_3,
630 PIXEL_OVERLAP_CNT_MASK,
631 temp << PIXEL_OVERLAP_CNT_SHIFT);
632 }
633 }
634
635 for_each_dsi_port(port, intel_dsi->ports) {
636 i915_reg_t port_ctrl = port_ctrl_reg(display, port);
637 u32 temp;
638
639 temp = intel_de_read(display, port_ctrl);
640
641 temp &= ~LANE_CONFIGURATION_MASK;
642 temp &= ~DUAL_LINK_MODE_MASK;
643
644 if (intel_dsi->ports == (BIT(PORT_A) | BIT(PORT_C))) {
645 temp |= (intel_dsi->dual_link - 1)
646 << DUAL_LINK_MODE_SHIFT;
647 if (display->platform.broxton)
648 temp |= LANE_CONFIGURATION_DUAL_LINK_A;
649 else
650 temp |= crtc->pipe ?
651 LANE_CONFIGURATION_DUAL_LINK_B :
652 LANE_CONFIGURATION_DUAL_LINK_A;
653 }
654
655 if (intel_dsi->pixel_format != MIPI_DSI_FMT_RGB888)
656 temp |= DITHERING_ENABLE;
657
658 /* assert ip_tg_enable signal */
659 intel_de_write(display, port_ctrl, temp | DPI_ENABLE);
660 intel_de_posting_read(display, port_ctrl);
661 }
662 }
663
intel_dsi_port_disable(struct intel_encoder * encoder)664 static void intel_dsi_port_disable(struct intel_encoder *encoder)
665 {
666 struct intel_display *display = to_intel_display(encoder);
667 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
668 enum port port;
669
670 for_each_dsi_port(port, intel_dsi->ports) {
671 i915_reg_t port_ctrl = port_ctrl_reg(display, port);
672
673 /* de-assert ip_tg_enable signal */
674 intel_de_rmw(display, port_ctrl, DPI_ENABLE, 0);
675 intel_de_posting_read(display, port_ctrl);
676 }
677 }
678
679 static void intel_dsi_prepare(struct intel_encoder *encoder,
680 const struct intel_crtc_state *pipe_config);
681 static void intel_dsi_unprepare(struct intel_encoder *encoder);
682
683 /*
684 * Panel enable/disable sequences from the VBT spec.
685 *
686 * Note the spec has AssertReset / DeassertReset swapped from their
687 * usual naming. We use the normal names to avoid confusion (so below
688 * they are swapped compared to the spec).
689 *
690 * Steps starting with MIPI refer to VBT sequences, note that for v2
691 * VBTs several steps which have a VBT in v2 are expected to be handled
692 * directly by the driver, by directly driving gpios for example.
693 *
694 * v2 video mode seq v3 video mode seq command mode seq
695 * - power on - MIPIPanelPowerOn - power on
696 * - wait t1+t2 - wait t1+t2
697 * - MIPIDeassertResetPin - MIPIDeassertResetPin - MIPIDeassertResetPin
698 * - io lines to lp-11 - io lines to lp-11 - io lines to lp-11
699 * - MIPISendInitialDcsCmds - MIPISendInitialDcsCmds - MIPISendInitialDcsCmds
700 * - MIPITearOn
701 * - MIPIDisplayOn
702 * - turn on DPI - turn on DPI - set pipe to dsr mode
703 * - MIPIDisplayOn - MIPIDisplayOn
704 * - wait t5 - wait t5
705 * - backlight on - MIPIBacklightOn - backlight on
706 * ... ... ... issue mem cmds ...
707 * - backlight off - MIPIBacklightOff - backlight off
708 * - wait t6 - wait t6
709 * - MIPIDisplayOff
710 * - turn off DPI - turn off DPI - disable pipe dsr mode
711 * - MIPITearOff
712 * - MIPIDisplayOff - MIPIDisplayOff
713 * - io lines to lp-00 - io lines to lp-00 - io lines to lp-00
714 * - MIPIAssertResetPin - MIPIAssertResetPin - MIPIAssertResetPin
715 * - wait t3 - wait t3
716 * - power off - MIPIPanelPowerOff - power off
717 * - wait t4 - wait t4
718 */
719
720 /*
721 * DSI port enable has to be done before pipe and plane enable, so we do it in
722 * the pre_enable hook instead of the enable hook.
723 */
intel_dsi_pre_enable(struct intel_atomic_state * state,struct intel_encoder * encoder,const struct intel_crtc_state * pipe_config,const struct drm_connector_state * conn_state)724 static void intel_dsi_pre_enable(struct intel_atomic_state *state,
725 struct intel_encoder *encoder,
726 const struct intel_crtc_state *pipe_config,
727 const struct drm_connector_state *conn_state)
728 {
729 struct intel_display *display = to_intel_display(encoder);
730 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
731 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
732 enum pipe pipe = crtc->pipe;
733 enum port port;
734 bool glk_cold_boot = false;
735
736 drm_dbg_kms(display->drm, "\n");
737
738 intel_dsi_wait_panel_power_cycle(intel_dsi);
739
740 intel_set_cpu_fifo_underrun_reporting(display, pipe, true);
741
742 /*
743 * The BIOS may leave the PLL in a wonky state where it doesn't
744 * lock. It needs to be fully powered down to fix it.
745 */
746 if (display->platform.geminilake || display->platform.broxton) {
747 bxt_dsi_pll_disable(encoder);
748 bxt_dsi_pll_enable(encoder, pipe_config);
749 } else {
750 vlv_dsi_pll_disable(encoder);
751 vlv_dsi_pll_enable(encoder, pipe_config);
752 }
753
754 if (display->platform.broxton) {
755 /* Add MIPI IO reset programming for modeset */
756 intel_de_rmw(display, BXT_P_CR_GT_DISP_PWRON, 0, MIPIO_RST_CTRL);
757
758 /* Power up DSI regulator */
759 intel_de_write(display, BXT_P_DSI_REGULATOR_CFG, STAP_SELECT);
760 intel_de_write(display, BXT_P_DSI_REGULATOR_TX_CTRL, 0);
761 }
762
763 if (display->platform.valleyview || display->platform.cherryview) {
764 /* Disable DPOunit clock gating, can stall pipe */
765 intel_de_rmw(display, DSPCLK_GATE_D(display),
766 0, DPOUNIT_CLOCK_GATE_DISABLE);
767 }
768
769 if (!display->platform.geminilake)
770 intel_dsi_prepare(encoder, pipe_config);
771
772 /* Give the panel time to power-on and then deassert its reset */
773 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_POWER_ON);
774 msleep(intel_dsi->panel_on_delay);
775 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DEASSERT_RESET);
776
777 if (display->platform.geminilake) {
778 glk_cold_boot = glk_dsi_enable_io(encoder);
779
780 /* Prepare port in cold boot(s3/s4) scenario */
781 if (glk_cold_boot)
782 intel_dsi_prepare(encoder, pipe_config);
783 }
784
785 /* Put device in ready state (LP-11) */
786 intel_dsi_device_ready(encoder);
787
788 /* Prepare port in normal boot scenario */
789 if (display->platform.geminilake && !glk_cold_boot)
790 intel_dsi_prepare(encoder, pipe_config);
791
792 /* Send initialization commands in LP mode */
793 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_INIT_OTP);
794
795 /*
796 * Enable port in pre-enable phase itself because as per hw team
797 * recommendation, port should be enabled before plane & pipe
798 */
799 if (is_cmd_mode(intel_dsi)) {
800 for_each_dsi_port(port, intel_dsi->ports)
801 intel_de_write(display,
802 MIPI_MAX_RETURN_PKT_SIZE(display, port), 8 * 4);
803 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_TEAR_ON);
804 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DISPLAY_ON);
805 } else {
806 msleep(20); /* XXX */
807 for_each_dsi_port(port, intel_dsi->ports)
808 dpi_send_cmd(intel_dsi, TURN_ON, false, port);
809 msleep(100);
810
811 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DISPLAY_ON);
812
813 intel_dsi_port_enable(encoder, pipe_config);
814 }
815
816 intel_backlight_enable(pipe_config, conn_state);
817 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_BACKLIGHT_ON);
818 }
819
bxt_dsi_enable(struct intel_atomic_state * state,struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state,const struct drm_connector_state * conn_state)820 static void bxt_dsi_enable(struct intel_atomic_state *state,
821 struct intel_encoder *encoder,
822 const struct intel_crtc_state *crtc_state,
823 const struct drm_connector_state *conn_state)
824 {
825 intel_crtc_vblank_on(crtc_state);
826 }
827
828 /*
829 * DSI port disable has to be done after pipe and plane disable, so we do it in
830 * the post_disable hook.
831 */
intel_dsi_disable(struct intel_atomic_state * state,struct intel_encoder * encoder,const struct intel_crtc_state * old_crtc_state,const struct drm_connector_state * old_conn_state)832 static void intel_dsi_disable(struct intel_atomic_state *state,
833 struct intel_encoder *encoder,
834 const struct intel_crtc_state *old_crtc_state,
835 const struct drm_connector_state *old_conn_state)
836 {
837 struct intel_display *display = to_intel_display(encoder);
838 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
839 enum port port;
840
841 drm_dbg_kms(display->drm, "\n");
842
843 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_BACKLIGHT_OFF);
844 intel_backlight_disable(old_conn_state);
845
846 /*
847 * According to the spec we should send SHUTDOWN before
848 * MIPI_SEQ_DISPLAY_OFF only for v3+ VBTs, but field testing
849 * has shown that the v3 sequence works for v2 VBTs too
850 */
851 if (is_vid_mode(intel_dsi)) {
852 /* Send Shutdown command to the panel in LP mode */
853 for_each_dsi_port(port, intel_dsi->ports)
854 dpi_send_cmd(intel_dsi, SHUTDOWN, false, port);
855 msleep(10);
856 }
857 }
858
intel_dsi_clear_device_ready(struct intel_encoder * encoder)859 static void intel_dsi_clear_device_ready(struct intel_encoder *encoder)
860 {
861 struct intel_display *display = to_intel_display(encoder);
862
863 if (display->platform.geminilake)
864 glk_dsi_clear_device_ready(encoder);
865 else
866 vlv_dsi_clear_device_ready(encoder);
867 }
868
intel_dsi_post_disable(struct intel_atomic_state * state,struct intel_encoder * encoder,const struct intel_crtc_state * old_crtc_state,const struct drm_connector_state * old_conn_state)869 static void intel_dsi_post_disable(struct intel_atomic_state *state,
870 struct intel_encoder *encoder,
871 const struct intel_crtc_state *old_crtc_state,
872 const struct drm_connector_state *old_conn_state)
873 {
874 struct intel_display *display = to_intel_display(encoder);
875 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
876 enum port port;
877
878 drm_dbg_kms(display->drm, "\n");
879
880 if (display->platform.geminilake || display->platform.broxton) {
881 intel_crtc_vblank_off(old_crtc_state);
882
883 skl_scaler_disable(old_crtc_state);
884 }
885
886 if (is_vid_mode(intel_dsi)) {
887 for_each_dsi_port(port, intel_dsi->ports)
888 vlv_dsi_wait_for_fifo_empty(intel_dsi, port);
889
890 intel_dsi_port_disable(encoder);
891 usleep_range(2000, 5000);
892 }
893
894 intel_dsi_unprepare(encoder);
895
896 /*
897 * if disable packets are sent before sending shutdown packet then in
898 * some next enable sequence send turn on packet error is observed
899 */
900 if (is_cmd_mode(intel_dsi))
901 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_TEAR_OFF);
902 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DISPLAY_OFF);
903
904 /* Transition to LP-00 */
905 intel_dsi_clear_device_ready(encoder);
906
907 if (display->platform.broxton) {
908 /* Power down DSI regulator to save power */
909 intel_de_write(display, BXT_P_DSI_REGULATOR_CFG, STAP_SELECT);
910 intel_de_write(display, BXT_P_DSI_REGULATOR_TX_CTRL,
911 HS_IO_CTRL_SELECT);
912
913 /* Add MIPI IO reset programming for modeset */
914 intel_de_rmw(display, BXT_P_CR_GT_DISP_PWRON, MIPIO_RST_CTRL, 0);
915 }
916
917 if (display->platform.geminilake || display->platform.broxton) {
918 bxt_dsi_pll_disable(encoder);
919 } else {
920 vlv_dsi_pll_disable(encoder);
921
922 intel_de_rmw(display, DSPCLK_GATE_D(display),
923 DPOUNIT_CLOCK_GATE_DISABLE, 0);
924 }
925
926 /* Assert reset */
927 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_ASSERT_RESET);
928
929 msleep(intel_dsi->panel_off_delay);
930 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_POWER_OFF);
931
932 intel_dsi->panel_power_off_time = ktime_get_boottime();
933 }
934
intel_dsi_get_hw_state(struct intel_encoder * encoder,enum pipe * pipe)935 static bool intel_dsi_get_hw_state(struct intel_encoder *encoder,
936 enum pipe *pipe)
937 {
938 struct intel_display *display = to_intel_display(encoder);
939 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
940 intel_wakeref_t wakeref;
941 enum port port;
942 bool active = false;
943
944 drm_dbg_kms(display->drm, "\n");
945
946 wakeref = intel_display_power_get_if_enabled(display,
947 encoder->power_domain);
948 if (!wakeref)
949 return false;
950
951 /*
952 * On Broxton the PLL needs to be enabled with a valid divider
953 * configuration, otherwise accessing DSI registers will hang the
954 * machine. See BSpec North Display Engine registers/MIPI[BXT].
955 */
956 if ((display->platform.geminilake || display->platform.broxton) &&
957 !bxt_dsi_pll_is_enabled(display))
958 goto out_put_power;
959
960 /* XXX: this only works for one DSI output */
961 for_each_dsi_port(port, intel_dsi->ports) {
962 i915_reg_t port_ctrl = port_ctrl_reg(display, port);
963 bool enabled = intel_de_read(display, port_ctrl) & DPI_ENABLE;
964
965 /*
966 * Due to some hardware limitations on VLV/CHV, the DPI enable
967 * bit in port C control register does not get set. As a
968 * workaround, check pipe B conf instead.
969 */
970 if ((display->platform.valleyview || display->platform.cherryview) &&
971 port == PORT_C)
972 enabled = intel_de_read(display,
973 TRANSCONF(display, PIPE_B)) & TRANSCONF_ENABLE;
974
975 /* Try command mode if video mode not enabled */
976 if (!enabled) {
977 u32 tmp = intel_de_read(display,
978 MIPI_DSI_FUNC_PRG(display, port));
979 enabled = tmp & CMD_MODE_DATA_WIDTH_MASK;
980 }
981
982 if (!enabled)
983 continue;
984
985 if (!(intel_de_read(display, MIPI_DEVICE_READY(display, port)) & DEVICE_READY))
986 continue;
987
988 if (display->platform.geminilake || display->platform.broxton) {
989 u32 tmp = intel_de_read(display, MIPI_CTRL(display, port));
990 tmp &= BXT_PIPE_SELECT_MASK;
991 tmp >>= BXT_PIPE_SELECT_SHIFT;
992
993 if (drm_WARN_ON(display->drm, tmp > PIPE_C))
994 continue;
995
996 *pipe = tmp;
997 } else {
998 *pipe = port == PORT_A ? PIPE_A : PIPE_B;
999 }
1000
1001 active = true;
1002 break;
1003 }
1004
1005 out_put_power:
1006 intel_display_power_put(display, encoder->power_domain, wakeref);
1007
1008 return active;
1009 }
1010
bxt_dsi_get_pipe_config(struct intel_encoder * encoder,struct intel_crtc_state * pipe_config)1011 static void bxt_dsi_get_pipe_config(struct intel_encoder *encoder,
1012 struct intel_crtc_state *pipe_config)
1013 {
1014 struct intel_display *display = to_intel_display(encoder);
1015 struct drm_display_mode *adjusted_mode =
1016 &pipe_config->hw.adjusted_mode;
1017 struct drm_display_mode *adjusted_mode_sw;
1018 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
1019 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1020 unsigned int lane_count = intel_dsi->lane_count;
1021 unsigned int bpp, fmt;
1022 enum port port;
1023 u16 hactive, hfp, hsync, hbp, vfp, vsync;
1024 u16 hfp_sw, hsync_sw, hbp_sw;
1025 u16 crtc_htotal_sw, crtc_hsync_start_sw, crtc_hsync_end_sw,
1026 crtc_hblank_start_sw, crtc_hblank_end_sw;
1027
1028 /* FIXME: hw readout should not depend on SW state */
1029 adjusted_mode_sw = &crtc->config->hw.adjusted_mode;
1030
1031 /*
1032 * Atleast one port is active as encoder->get_config called only if
1033 * encoder->get_hw_state() returns true.
1034 */
1035 for_each_dsi_port(port, intel_dsi->ports) {
1036 if (intel_de_read(display, BXT_MIPI_PORT_CTRL(port)) & DPI_ENABLE)
1037 break;
1038 }
1039
1040 fmt = intel_de_read(display, MIPI_DSI_FUNC_PRG(display, port)) & VID_MODE_FORMAT_MASK;
1041 bpp = mipi_dsi_pixel_format_to_bpp(
1042 pixel_format_from_register_bits(fmt));
1043
1044 pipe_config->pipe_bpp = bdw_get_pipe_misc_bpp(crtc);
1045
1046 /* Enable Frame time stamo based scanline reporting */
1047 pipe_config->mode_flags |=
1048 I915_MODE_FLAG_GET_SCANLINE_FROM_TIMESTAMP;
1049
1050 /* In terms of pixels */
1051 adjusted_mode->crtc_hdisplay =
1052 intel_de_read(display,
1053 BXT_MIPI_TRANS_HACTIVE(port));
1054 adjusted_mode->crtc_vdisplay =
1055 intel_de_read(display,
1056 BXT_MIPI_TRANS_VACTIVE(port));
1057 adjusted_mode->crtc_vtotal =
1058 intel_de_read(display,
1059 BXT_MIPI_TRANS_VTOTAL(port)) + 1;
1060
1061 hactive = adjusted_mode->crtc_hdisplay;
1062 hfp = intel_de_read(display, MIPI_HFP_COUNT(display, port));
1063
1064 /*
1065 * Meaningful for video mode non-burst sync pulse mode only,
1066 * can be zero for non-burst sync events and burst modes
1067 */
1068 hsync = intel_de_read(display, MIPI_HSYNC_PADDING_COUNT(display, port));
1069 hbp = intel_de_read(display, MIPI_HBP_COUNT(display, port));
1070
1071 /* horizontal values are in terms of high speed byte clock */
1072 hfp = pixels_from_txbyteclkhs(hfp, bpp, lane_count,
1073 intel_dsi->burst_mode_ratio);
1074 hsync = pixels_from_txbyteclkhs(hsync, bpp, lane_count,
1075 intel_dsi->burst_mode_ratio);
1076 hbp = pixels_from_txbyteclkhs(hbp, bpp, lane_count,
1077 intel_dsi->burst_mode_ratio);
1078
1079 if (intel_dsi->dual_link) {
1080 hfp *= 2;
1081 hsync *= 2;
1082 hbp *= 2;
1083 }
1084
1085 /* vertical values are in terms of lines */
1086 vfp = intel_de_read(display, MIPI_VFP_COUNT(display, port));
1087 vsync = intel_de_read(display, MIPI_VSYNC_PADDING_COUNT(display, port));
1088
1089 adjusted_mode->crtc_htotal = hactive + hfp + hsync + hbp;
1090 adjusted_mode->crtc_hsync_start = hfp + adjusted_mode->crtc_hdisplay;
1091 adjusted_mode->crtc_hsync_end = hsync + adjusted_mode->crtc_hsync_start;
1092 adjusted_mode->crtc_hblank_start = adjusted_mode->crtc_hdisplay;
1093 adjusted_mode->crtc_hblank_end = adjusted_mode->crtc_htotal;
1094
1095 adjusted_mode->crtc_vsync_start = vfp + adjusted_mode->crtc_vdisplay;
1096 adjusted_mode->crtc_vsync_end = vsync + adjusted_mode->crtc_vsync_start;
1097 adjusted_mode->crtc_vblank_start = adjusted_mode->crtc_vdisplay;
1098 adjusted_mode->crtc_vblank_end = adjusted_mode->crtc_vtotal;
1099
1100 /*
1101 * In BXT DSI there is no regs programmed with few horizontal timings
1102 * in Pixels but txbyteclkhs.. So retrieval process adds some
1103 * ROUND_UP ERRORS in the process of PIXELS<==>txbyteclkhs.
1104 * Actually here for the given adjusted_mode, we are calculating the
1105 * value programmed to the port and then back to the horizontal timing
1106 * param in pixels. This is the expected value, including roundup errors
1107 * And if that is same as retrieved value from port, then
1108 * (HW state) adjusted_mode's horizontal timings are corrected to
1109 * match with SW state to nullify the errors.
1110 */
1111 /* Calculating the value programmed to the Port register */
1112 hfp_sw = adjusted_mode_sw->crtc_hsync_start -
1113 adjusted_mode_sw->crtc_hdisplay;
1114 hsync_sw = adjusted_mode_sw->crtc_hsync_end -
1115 adjusted_mode_sw->crtc_hsync_start;
1116 hbp_sw = adjusted_mode_sw->crtc_htotal -
1117 adjusted_mode_sw->crtc_hsync_end;
1118
1119 if (intel_dsi->dual_link) {
1120 hfp_sw /= 2;
1121 hsync_sw /= 2;
1122 hbp_sw /= 2;
1123 }
1124
1125 hfp_sw = txbyteclkhs(hfp_sw, bpp, lane_count,
1126 intel_dsi->burst_mode_ratio);
1127 hsync_sw = txbyteclkhs(hsync_sw, bpp, lane_count,
1128 intel_dsi->burst_mode_ratio);
1129 hbp_sw = txbyteclkhs(hbp_sw, bpp, lane_count,
1130 intel_dsi->burst_mode_ratio);
1131
1132 /* Reverse calculating the adjusted mode parameters from port reg vals*/
1133 hfp_sw = pixels_from_txbyteclkhs(hfp_sw, bpp, lane_count,
1134 intel_dsi->burst_mode_ratio);
1135 hsync_sw = pixels_from_txbyteclkhs(hsync_sw, bpp, lane_count,
1136 intel_dsi->burst_mode_ratio);
1137 hbp_sw = pixels_from_txbyteclkhs(hbp_sw, bpp, lane_count,
1138 intel_dsi->burst_mode_ratio);
1139
1140 if (intel_dsi->dual_link) {
1141 hfp_sw *= 2;
1142 hsync_sw *= 2;
1143 hbp_sw *= 2;
1144 }
1145
1146 crtc_htotal_sw = adjusted_mode_sw->crtc_hdisplay + hfp_sw +
1147 hsync_sw + hbp_sw;
1148 crtc_hsync_start_sw = hfp_sw + adjusted_mode_sw->crtc_hdisplay;
1149 crtc_hsync_end_sw = hsync_sw + crtc_hsync_start_sw;
1150 crtc_hblank_start_sw = adjusted_mode_sw->crtc_hdisplay;
1151 crtc_hblank_end_sw = crtc_htotal_sw;
1152
1153 if (adjusted_mode->crtc_htotal == crtc_htotal_sw)
1154 adjusted_mode->crtc_htotal = adjusted_mode_sw->crtc_htotal;
1155
1156 if (adjusted_mode->crtc_hsync_start == crtc_hsync_start_sw)
1157 adjusted_mode->crtc_hsync_start =
1158 adjusted_mode_sw->crtc_hsync_start;
1159
1160 if (adjusted_mode->crtc_hsync_end == crtc_hsync_end_sw)
1161 adjusted_mode->crtc_hsync_end =
1162 adjusted_mode_sw->crtc_hsync_end;
1163
1164 if (adjusted_mode->crtc_hblank_start == crtc_hblank_start_sw)
1165 adjusted_mode->crtc_hblank_start =
1166 adjusted_mode_sw->crtc_hblank_start;
1167
1168 if (adjusted_mode->crtc_hblank_end == crtc_hblank_end_sw)
1169 adjusted_mode->crtc_hblank_end =
1170 adjusted_mode_sw->crtc_hblank_end;
1171 }
1172
intel_dsi_get_config(struct intel_encoder * encoder,struct intel_crtc_state * pipe_config)1173 static void intel_dsi_get_config(struct intel_encoder *encoder,
1174 struct intel_crtc_state *pipe_config)
1175 {
1176 struct intel_display *display = to_intel_display(encoder);
1177 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1178 u32 pclk;
1179
1180 drm_dbg_kms(display->drm, "\n");
1181
1182 pipe_config->output_types |= BIT(INTEL_OUTPUT_DSI);
1183
1184 if (display->platform.geminilake || display->platform.broxton) {
1185 bxt_dsi_get_pipe_config(encoder, pipe_config);
1186 pclk = bxt_dsi_get_pclk(encoder, pipe_config);
1187 } else {
1188 pclk = vlv_dsi_get_pclk(encoder, pipe_config);
1189 }
1190
1191 pipe_config->port_clock = pclk;
1192
1193 /* FIXME definitely not right for burst/cmd mode/pixel overlap */
1194 pipe_config->hw.adjusted_mode.crtc_clock = pclk;
1195 if (intel_dsi->dual_link)
1196 pipe_config->hw.adjusted_mode.crtc_clock *= 2;
1197 }
1198
1199 /* return txclkesc cycles in terms of divider and duration in us */
txclkesc(u32 divider,unsigned int us)1200 static u16 txclkesc(u32 divider, unsigned int us)
1201 {
1202 switch (divider) {
1203 case ESCAPE_CLOCK_DIVIDER_1:
1204 default:
1205 return 20 * us;
1206 case ESCAPE_CLOCK_DIVIDER_2:
1207 return 10 * us;
1208 case ESCAPE_CLOCK_DIVIDER_4:
1209 return 5 * us;
1210 }
1211 }
1212
set_dsi_timings(struct intel_encoder * encoder,const struct drm_display_mode * adjusted_mode)1213 static void set_dsi_timings(struct intel_encoder *encoder,
1214 const struct drm_display_mode *adjusted_mode)
1215 {
1216 struct intel_display *display = to_intel_display(encoder);
1217 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1218 enum port port;
1219 unsigned int bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
1220 unsigned int lane_count = intel_dsi->lane_count;
1221
1222 u16 hactive, hfp, hsync, hbp, vfp, vsync, vbp;
1223
1224 hactive = adjusted_mode->crtc_hdisplay;
1225 hfp = adjusted_mode->crtc_hsync_start - adjusted_mode->crtc_hdisplay;
1226 hsync = adjusted_mode->crtc_hsync_end - adjusted_mode->crtc_hsync_start;
1227 hbp = adjusted_mode->crtc_htotal - adjusted_mode->crtc_hsync_end;
1228
1229 if (intel_dsi->dual_link) {
1230 hactive /= 2;
1231 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK)
1232 hactive += intel_dsi->pixel_overlap;
1233 hfp /= 2;
1234 hsync /= 2;
1235 hbp /= 2;
1236 }
1237
1238 vfp = adjusted_mode->crtc_vsync_start - adjusted_mode->crtc_vdisplay;
1239 vsync = adjusted_mode->crtc_vsync_end - adjusted_mode->crtc_vsync_start;
1240 vbp = adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vsync_end;
1241
1242 /* horizontal values are in terms of high speed byte clock */
1243 hactive = txbyteclkhs(hactive, bpp, lane_count,
1244 intel_dsi->burst_mode_ratio);
1245 hfp = txbyteclkhs(hfp, bpp, lane_count, intel_dsi->burst_mode_ratio);
1246 hsync = txbyteclkhs(hsync, bpp, lane_count,
1247 intel_dsi->burst_mode_ratio);
1248 hbp = txbyteclkhs(hbp, bpp, lane_count, intel_dsi->burst_mode_ratio);
1249
1250 for_each_dsi_port(port, intel_dsi->ports) {
1251 if (display->platform.geminilake || display->platform.broxton) {
1252 /*
1253 * Program hdisplay and vdisplay on MIPI transcoder.
1254 * This is different from calculated hactive and
1255 * vactive, as they are calculated per channel basis,
1256 * whereas these values should be based on resolution.
1257 */
1258 intel_de_write(display, BXT_MIPI_TRANS_HACTIVE(port),
1259 adjusted_mode->crtc_hdisplay);
1260 intel_de_write(display, BXT_MIPI_TRANS_VACTIVE(port),
1261 adjusted_mode->crtc_vdisplay);
1262 intel_de_write(display, BXT_MIPI_TRANS_VTOTAL(port),
1263 adjusted_mode->crtc_vtotal - 1);
1264 }
1265
1266 intel_de_write(display, MIPI_HACTIVE_AREA_COUNT(display, port),
1267 hactive);
1268 intel_de_write(display, MIPI_HFP_COUNT(display, port), hfp);
1269
1270 /* meaningful for video mode non-burst sync pulse mode only,
1271 * can be zero for non-burst sync events and burst modes */
1272 intel_de_write(display, MIPI_HSYNC_PADDING_COUNT(display, port),
1273 hsync);
1274 intel_de_write(display, MIPI_HBP_COUNT(display, port), hbp);
1275
1276 /* vertical values are in terms of lines */
1277 intel_de_write(display, MIPI_VFP_COUNT(display, port), vfp);
1278 intel_de_write(display, MIPI_VSYNC_PADDING_COUNT(display, port),
1279 vsync);
1280 intel_de_write(display, MIPI_VBP_COUNT(display, port), vbp);
1281 }
1282 }
1283
pixel_format_to_reg(enum mipi_dsi_pixel_format fmt)1284 static u32 pixel_format_to_reg(enum mipi_dsi_pixel_format fmt)
1285 {
1286 switch (fmt) {
1287 case MIPI_DSI_FMT_RGB888:
1288 return VID_MODE_FORMAT_RGB888;
1289 case MIPI_DSI_FMT_RGB666:
1290 return VID_MODE_FORMAT_RGB666;
1291 case MIPI_DSI_FMT_RGB666_PACKED:
1292 return VID_MODE_FORMAT_RGB666_PACKED;
1293 case MIPI_DSI_FMT_RGB565:
1294 return VID_MODE_FORMAT_RGB565;
1295 default:
1296 MISSING_CASE(fmt);
1297 return VID_MODE_FORMAT_RGB666;
1298 }
1299 }
1300
intel_dsi_prepare(struct intel_encoder * encoder,const struct intel_crtc_state * pipe_config)1301 static void intel_dsi_prepare(struct intel_encoder *encoder,
1302 const struct intel_crtc_state *pipe_config)
1303 {
1304 struct intel_display *display = to_intel_display(encoder);
1305 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
1306 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1307 const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
1308 enum port port;
1309 unsigned int bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
1310 u32 val, tmp;
1311 u16 mode_hdisplay;
1312
1313 drm_dbg_kms(display->drm, "pipe %c\n", pipe_name(crtc->pipe));
1314
1315 mode_hdisplay = adjusted_mode->crtc_hdisplay;
1316
1317 if (intel_dsi->dual_link) {
1318 mode_hdisplay /= 2;
1319 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK)
1320 mode_hdisplay += intel_dsi->pixel_overlap;
1321 }
1322
1323 for_each_dsi_port(port, intel_dsi->ports) {
1324 if (display->platform.valleyview || display->platform.cherryview) {
1325 /*
1326 * escape clock divider, 20MHz, shared for A and C.
1327 * device ready must be off when doing this! txclkesc?
1328 */
1329 tmp = intel_de_read(display, MIPI_CTRL(display, PORT_A));
1330 tmp &= ~ESCAPE_CLOCK_DIVIDER_MASK;
1331 intel_de_write(display, MIPI_CTRL(display, PORT_A),
1332 tmp | ESCAPE_CLOCK_DIVIDER_1);
1333
1334 /* read request priority is per pipe */
1335 tmp = intel_de_read(display, MIPI_CTRL(display, port));
1336 tmp &= ~READ_REQUEST_PRIORITY_MASK;
1337 intel_de_write(display, MIPI_CTRL(display, port),
1338 tmp | READ_REQUEST_PRIORITY_HIGH);
1339 } else if (display->platform.geminilake || display->platform.broxton) {
1340 enum pipe pipe = crtc->pipe;
1341
1342 intel_de_rmw(display, MIPI_CTRL(display, port),
1343 BXT_PIPE_SELECT_MASK, BXT_PIPE_SELECT(pipe));
1344 }
1345
1346 /* XXX: why here, why like this? handling in irq handler?! */
1347 intel_de_write(display, MIPI_INTR_STAT(display, port), 0xffffffff);
1348 intel_de_write(display, MIPI_INTR_EN(display, port), 0xffffffff);
1349
1350 intel_de_write(display, MIPI_DPHY_PARAM(display, port),
1351 intel_dsi->dphy_reg);
1352
1353 intel_de_write(display, MIPI_DPI_RESOLUTION(display, port),
1354 adjusted_mode->crtc_vdisplay << VERTICAL_ADDRESS_SHIFT | mode_hdisplay << HORIZONTAL_ADDRESS_SHIFT);
1355 }
1356
1357 set_dsi_timings(encoder, adjusted_mode);
1358
1359 val = intel_dsi->lane_count << DATA_LANES_PRG_REG_SHIFT;
1360 if (is_cmd_mode(intel_dsi)) {
1361 val |= intel_dsi->channel << CMD_MODE_CHANNEL_NUMBER_SHIFT;
1362 val |= CMD_MODE_DATA_WIDTH_8_BIT; /* XXX */
1363 } else {
1364 val |= intel_dsi->channel << VID_MODE_CHANNEL_NUMBER_SHIFT;
1365 val |= pixel_format_to_reg(intel_dsi->pixel_format);
1366 }
1367
1368 tmp = 0;
1369 if (intel_dsi->eotp_pkt == 0)
1370 tmp |= EOT_DISABLE;
1371 if (intel_dsi->clock_stop)
1372 tmp |= CLOCKSTOP;
1373
1374 if (display->platform.geminilake || display->platform.broxton) {
1375 tmp |= BXT_DPHY_DEFEATURE_EN;
1376 if (!is_cmd_mode(intel_dsi))
1377 tmp |= BXT_DEFEATURE_DPI_FIFO_CTR;
1378 }
1379
1380 for_each_dsi_port(port, intel_dsi->ports) {
1381 intel_de_write(display, MIPI_DSI_FUNC_PRG(display, port), val);
1382
1383 /* timeouts for recovery. one frame IIUC. if counter expires,
1384 * EOT and stop state. */
1385
1386 /*
1387 * In burst mode, value greater than one DPI line Time in byte
1388 * clock (txbyteclkhs) To timeout this timer 1+ of the above
1389 * said value is recommended.
1390 *
1391 * In non-burst mode, Value greater than one DPI frame time in
1392 * byte clock(txbyteclkhs) To timeout this timer 1+ of the above
1393 * said value is recommended.
1394 *
1395 * In DBI only mode, value greater than one DBI frame time in
1396 * byte clock(txbyteclkhs) To timeout this timer 1+ of the above
1397 * said value is recommended.
1398 */
1399
1400 if (is_vid_mode(intel_dsi) &&
1401 intel_dsi->video_mode == BURST_MODE) {
1402 intel_de_write(display, MIPI_HS_TX_TIMEOUT(display, port),
1403 txbyteclkhs(adjusted_mode->crtc_htotal, bpp, intel_dsi->lane_count, intel_dsi->burst_mode_ratio) + 1);
1404 } else {
1405 intel_de_write(display, MIPI_HS_TX_TIMEOUT(display, port),
1406 txbyteclkhs(adjusted_mode->crtc_vtotal * adjusted_mode->crtc_htotal, bpp, intel_dsi->lane_count, intel_dsi->burst_mode_ratio) + 1);
1407 }
1408 intel_de_write(display, MIPI_LP_RX_TIMEOUT(display, port),
1409 intel_dsi->lp_rx_timeout);
1410 intel_de_write(display, MIPI_TURN_AROUND_TIMEOUT(display, port),
1411 intel_dsi->turn_arnd_val);
1412 intel_de_write(display, MIPI_DEVICE_RESET_TIMER(display, port),
1413 intel_dsi->rst_timer_val);
1414
1415 /* dphy stuff */
1416
1417 /* in terms of low power clock */
1418 intel_de_write(display, MIPI_INIT_COUNT(display, port),
1419 txclkesc(intel_dsi->escape_clk_div, 100));
1420
1421 if ((display->platform.geminilake || display->platform.broxton) &&
1422 !intel_dsi->dual_link) {
1423 /*
1424 * BXT spec says write MIPI_INIT_COUNT for
1425 * both the ports, even if only one is
1426 * getting used. So write the other port
1427 * if not in dual link mode.
1428 */
1429 intel_de_write(display,
1430 MIPI_INIT_COUNT(display, port == PORT_A ? PORT_C : PORT_A),
1431 intel_dsi->init_count);
1432 }
1433
1434 /* recovery disables */
1435 intel_de_write(display, MIPI_EOT_DISABLE(display, port), tmp);
1436
1437 /* in terms of low power clock */
1438 intel_de_write(display, MIPI_INIT_COUNT(display, port),
1439 intel_dsi->init_count);
1440
1441 /* in terms of txbyteclkhs. actual high to low switch +
1442 * MIPI_STOP_STATE_STALL * MIPI_LP_BYTECLK.
1443 *
1444 * XXX: write MIPI_STOP_STATE_STALL?
1445 */
1446 intel_de_write(display, MIPI_HIGH_LOW_SWITCH_COUNT(display, port),
1447 intel_dsi->hs_to_lp_count);
1448
1449 /* XXX: low power clock equivalence in terms of byte clock.
1450 * the number of byte clocks occupied in one low power clock.
1451 * based on txbyteclkhs and txclkesc.
1452 * txclkesc time / txbyteclk time * (105 + MIPI_STOP_STATE_STALL
1453 * ) / 105.???
1454 */
1455 intel_de_write(display, MIPI_LP_BYTECLK(display, port),
1456 intel_dsi->lp_byte_clk);
1457
1458 if (display->platform.geminilake) {
1459 intel_de_write(display, MIPI_TLPX_TIME_COUNT(display, port),
1460 intel_dsi->lp_byte_clk);
1461 /* Shadow of DPHY reg */
1462 intel_de_write(display, MIPI_CLK_LANE_TIMING(display, port),
1463 intel_dsi->dphy_reg);
1464 }
1465
1466 /* the bw essential for transmitting 16 long packets containing
1467 * 252 bytes meant for dcs write memory command is programmed in
1468 * this register in terms of byte clocks. based on dsi transfer
1469 * rate and the number of lanes configured the time taken to
1470 * transmit 16 long packets in a dsi stream varies. */
1471 intel_de_write(display, MIPI_DBI_BW_CTRL(display, port),
1472 intel_dsi->bw_timer);
1473
1474 intel_de_write(display, MIPI_CLK_LANE_SWITCH_TIME_CNT(display, port),
1475 intel_dsi->clk_lp_to_hs_count << LP_HS_SSW_CNT_SHIFT | intel_dsi->clk_hs_to_lp_count << HS_LP_PWR_SW_CNT_SHIFT);
1476
1477 if (is_vid_mode(intel_dsi)) {
1478 u32 fmt = intel_dsi->video_frmt_cfg_bits | IP_TG_CONFIG;
1479
1480 /*
1481 * Some panels might have resolution which is not a
1482 * multiple of 64 like 1366 x 768. Enable RANDOM
1483 * resolution support for such panels by default.
1484 */
1485 fmt |= RANDOM_DPI_DISPLAY_RESOLUTION;
1486
1487 switch (intel_dsi->video_mode) {
1488 default:
1489 MISSING_CASE(intel_dsi->video_mode);
1490 fallthrough;
1491 case NON_BURST_SYNC_EVENTS:
1492 fmt |= VIDEO_MODE_NON_BURST_WITH_SYNC_EVENTS;
1493 break;
1494 case NON_BURST_SYNC_PULSE:
1495 fmt |= VIDEO_MODE_NON_BURST_WITH_SYNC_PULSE;
1496 break;
1497 case BURST_MODE:
1498 fmt |= VIDEO_MODE_BURST;
1499 break;
1500 }
1501
1502 intel_de_write(display, MIPI_VIDEO_MODE_FORMAT(display, port), fmt);
1503 }
1504 }
1505 }
1506
intel_dsi_unprepare(struct intel_encoder * encoder)1507 static void intel_dsi_unprepare(struct intel_encoder *encoder)
1508 {
1509 struct intel_display *display = to_intel_display(encoder);
1510 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1511 enum port port;
1512
1513 if (display->platform.geminilake)
1514 return;
1515
1516 for_each_dsi_port(port, intel_dsi->ports) {
1517 /* Panel commands can be sent when clock is in LP11 */
1518 intel_de_write(display, MIPI_DEVICE_READY(display, port), 0x0);
1519
1520 if (display->platform.geminilake || display->platform.broxton)
1521 bxt_dsi_reset_clocks(encoder, port);
1522 else
1523 vlv_dsi_reset_clocks(encoder, port);
1524 intel_de_write(display, MIPI_EOT_DISABLE(display, port), CLOCKSTOP);
1525
1526 intel_de_rmw(display, MIPI_DSI_FUNC_PRG(display, port), VID_MODE_FORMAT_MASK, 0);
1527
1528 intel_de_write(display, MIPI_DEVICE_READY(display, port), 0x1);
1529 }
1530 }
1531
1532 static const struct drm_encoder_funcs intel_dsi_funcs = {
1533 .destroy = intel_encoder_destroy,
1534 };
1535
vlv_dsi_mode_valid(struct drm_connector * connector,const struct drm_display_mode * mode)1536 static enum drm_mode_status vlv_dsi_mode_valid(struct drm_connector *connector,
1537 const struct drm_display_mode *mode)
1538 {
1539 struct intel_display *display = to_intel_display(connector->dev);
1540
1541 if (display->platform.valleyview || display->platform.cherryview) {
1542 enum drm_mode_status status;
1543
1544 status = intel_cpu_transcoder_mode_valid(display, mode);
1545 if (status != MODE_OK)
1546 return status;
1547 }
1548
1549 return intel_dsi_mode_valid(connector, mode);
1550 }
1551
1552 static const struct drm_connector_helper_funcs intel_dsi_connector_helper_funcs = {
1553 .get_modes = intel_dsi_get_modes,
1554 .mode_valid = vlv_dsi_mode_valid,
1555 .atomic_check = intel_digital_connector_atomic_check,
1556 };
1557
1558 static const struct drm_connector_funcs intel_dsi_connector_funcs = {
1559 .detect = intel_panel_detect,
1560 .late_register = intel_connector_register,
1561 .early_unregister = intel_connector_unregister,
1562 .destroy = intel_connector_destroy,
1563 .fill_modes = drm_helper_probe_single_connector_modes,
1564 .atomic_get_property = intel_digital_connector_atomic_get_property,
1565 .atomic_set_property = intel_digital_connector_atomic_set_property,
1566 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1567 .atomic_duplicate_state = intel_digital_connector_duplicate_state,
1568 };
1569
vlv_dsi_add_properties(struct intel_connector * connector)1570 static void vlv_dsi_add_properties(struct intel_connector *connector)
1571 {
1572 const struct drm_display_mode *fixed_mode =
1573 intel_panel_preferred_fixed_mode(connector);
1574
1575 intel_attach_scaling_mode_property(&connector->base);
1576
1577 drm_connector_set_panel_orientation_with_quirk(&connector->base,
1578 intel_dsi_get_panel_orientation(connector),
1579 fixed_mode->hdisplay,
1580 fixed_mode->vdisplay);
1581 }
1582
1583 #define NS_KHZ_RATIO 1000000
1584
1585 #define PREPARE_CNT_MAX 0x3F
1586 #define EXIT_ZERO_CNT_MAX 0x3F
1587 #define CLK_ZERO_CNT_MAX 0xFF
1588 #define TRAIL_CNT_MAX 0x1F
1589
vlv_dphy_param_init(struct intel_dsi * intel_dsi)1590 static void vlv_dphy_param_init(struct intel_dsi *intel_dsi)
1591 {
1592 struct intel_connector *connector = intel_dsi->attached_connector;
1593 struct intel_display *display = to_intel_display(connector);
1594 struct mipi_config *mipi_config = connector->panel.vbt.dsi.config;
1595 u32 tlpx_ns, extra_byte_count, tlpx_ui;
1596 u32 ui_num, ui_den;
1597 u32 prepare_cnt, exit_zero_cnt, clk_zero_cnt, trail_cnt;
1598 u32 ths_prepare_ns, tclk_trail_ns;
1599 u32 tclk_prepare_clkzero, ths_prepare_hszero;
1600 u32 lp_to_hs_switch, hs_to_lp_switch;
1601 u32 mul;
1602
1603 tlpx_ns = intel_dsi_tlpx_ns(intel_dsi);
1604
1605 switch (intel_dsi->lane_count) {
1606 case 1:
1607 case 2:
1608 extra_byte_count = 2;
1609 break;
1610 case 3:
1611 extra_byte_count = 4;
1612 break;
1613 case 4:
1614 default:
1615 extra_byte_count = 3;
1616 break;
1617 }
1618
1619 /* in Kbps */
1620 ui_num = NS_KHZ_RATIO;
1621 ui_den = intel_dsi_bitrate(intel_dsi);
1622
1623 tclk_prepare_clkzero = mipi_config->tclk_prepare_clkzero;
1624 ths_prepare_hszero = mipi_config->ths_prepare_hszero;
1625
1626 /*
1627 * B060
1628 * LP byte clock = TLPX/ (8UI)
1629 */
1630 intel_dsi->lp_byte_clk = DIV_ROUND_UP(tlpx_ns * ui_den, 8 * ui_num);
1631
1632 /* DDR clock period = 2 * UI
1633 * UI(sec) = 1/(bitrate * 10^3) (bitrate is in KHZ)
1634 * UI(nsec) = 10^6 / bitrate
1635 * DDR clock period (nsec) = 2 * UI = (2 * 10^6)/ bitrate
1636 * DDR clock count = ns_value / DDR clock period
1637 *
1638 * For GEMINILAKE dphy_param_reg will be programmed in terms of
1639 * HS byte clock count for other platform in HS ddr clock count
1640 */
1641 mul = display->platform.geminilake ? 8 : 2;
1642 ths_prepare_ns = max(mipi_config->ths_prepare,
1643 mipi_config->tclk_prepare);
1644
1645 /* prepare count */
1646 prepare_cnt = DIV_ROUND_UP(ths_prepare_ns * ui_den, ui_num * mul);
1647
1648 if (prepare_cnt > PREPARE_CNT_MAX) {
1649 drm_dbg_kms(display->drm, "prepare count too high %u\n",
1650 prepare_cnt);
1651 prepare_cnt = PREPARE_CNT_MAX;
1652 }
1653
1654 /* exit zero count */
1655 exit_zero_cnt = DIV_ROUND_UP(
1656 (ths_prepare_hszero - ths_prepare_ns) * ui_den,
1657 ui_num * mul
1658 );
1659
1660 /*
1661 * Exit zero is unified val ths_zero and ths_exit
1662 * minimum value for ths_exit = 110ns
1663 * min (exit_zero_cnt * 2) = 110/UI
1664 * exit_zero_cnt = 55/UI
1665 */
1666 if (exit_zero_cnt < (55 * ui_den / ui_num) && (55 * ui_den) % ui_num)
1667 exit_zero_cnt += 1;
1668
1669 if (exit_zero_cnt > EXIT_ZERO_CNT_MAX) {
1670 drm_dbg_kms(display->drm, "exit zero count too high %u\n",
1671 exit_zero_cnt);
1672 exit_zero_cnt = EXIT_ZERO_CNT_MAX;
1673 }
1674
1675 /* clk zero count */
1676 clk_zero_cnt = DIV_ROUND_UP(
1677 (tclk_prepare_clkzero - ths_prepare_ns)
1678 * ui_den, ui_num * mul);
1679
1680 if (clk_zero_cnt > CLK_ZERO_CNT_MAX) {
1681 drm_dbg_kms(display->drm, "clock zero count too high %u\n",
1682 clk_zero_cnt);
1683 clk_zero_cnt = CLK_ZERO_CNT_MAX;
1684 }
1685
1686 /* trail count */
1687 tclk_trail_ns = max(mipi_config->tclk_trail, mipi_config->ths_trail);
1688 trail_cnt = DIV_ROUND_UP(tclk_trail_ns * ui_den, ui_num * mul);
1689
1690 if (trail_cnt > TRAIL_CNT_MAX) {
1691 drm_dbg_kms(display->drm, "trail count too high %u\n",
1692 trail_cnt);
1693 trail_cnt = TRAIL_CNT_MAX;
1694 }
1695
1696 /* B080 */
1697 intel_dsi->dphy_reg = exit_zero_cnt << 24 | trail_cnt << 16 |
1698 clk_zero_cnt << 8 | prepare_cnt;
1699
1700 /*
1701 * LP to HS switch count = 4TLPX + PREP_COUNT * mul + EXIT_ZERO_COUNT *
1702 * mul + 10UI + Extra Byte Count
1703 *
1704 * HS to LP switch count = THS-TRAIL + 2TLPX + Extra Byte Count
1705 * Extra Byte Count is calculated according to number of lanes.
1706 * High Low Switch Count is the Max of LP to HS and
1707 * HS to LP switch count
1708 *
1709 */
1710 tlpx_ui = DIV_ROUND_UP(tlpx_ns * ui_den, ui_num);
1711
1712 /* B044 */
1713 /* FIXME:
1714 * The comment above does not match with the code */
1715 lp_to_hs_switch = DIV_ROUND_UP(4 * tlpx_ui + prepare_cnt * mul +
1716 exit_zero_cnt * mul + 10, 8);
1717
1718 hs_to_lp_switch = DIV_ROUND_UP(mipi_config->ths_trail + 2 * tlpx_ui, 8);
1719
1720 intel_dsi->hs_to_lp_count = max(lp_to_hs_switch, hs_to_lp_switch);
1721 intel_dsi->hs_to_lp_count += extra_byte_count;
1722
1723 /* B088 */
1724 /* LP -> HS for clock lanes
1725 * LP clk sync + LP11 + LP01 + tclk_prepare + tclk_zero +
1726 * extra byte count
1727 * 2TPLX + 1TLPX + 1 TPLX(in ns) + prepare_cnt * 2 + clk_zero_cnt *
1728 * 2(in UI) + extra byte count
1729 * In byteclks = (4TLPX + prepare_cnt * 2 + clk_zero_cnt *2 (in UI)) /
1730 * 8 + extra byte count
1731 */
1732 intel_dsi->clk_lp_to_hs_count =
1733 DIV_ROUND_UP(
1734 4 * tlpx_ui + prepare_cnt * 2 +
1735 clk_zero_cnt * 2,
1736 8);
1737
1738 intel_dsi->clk_lp_to_hs_count += extra_byte_count;
1739
1740 /* HS->LP for Clock Lanes
1741 * Low Power clock synchronisations + 1Tx byteclk + tclk_trail +
1742 * Extra byte count
1743 * 2TLPX + 8UI + (trail_count*2)(in UI) + Extra byte count
1744 * In byteclks = (2*TLpx(in UI) + trail_count*2 +8)(in UI)/8 +
1745 * Extra byte count
1746 */
1747 intel_dsi->clk_hs_to_lp_count =
1748 DIV_ROUND_UP(2 * tlpx_ui + trail_cnt * 2 + 8,
1749 8);
1750 intel_dsi->clk_hs_to_lp_count += extra_byte_count;
1751
1752 intel_dsi_log_params(intel_dsi);
1753 }
1754
vlv_dsi_min_cdclk(const struct intel_crtc_state * crtc_state)1755 int vlv_dsi_min_cdclk(const struct intel_crtc_state *crtc_state)
1756 {
1757 struct intel_display *display = to_intel_display(crtc_state);
1758
1759 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI))
1760 return 0;
1761
1762 /*
1763 * On Valleyview some DSI panels lose (v|h)sync when the clock is lower
1764 * than 320000KHz.
1765 */
1766 if (display->platform.valleyview)
1767 return 320000;
1768
1769 /*
1770 * On Geminilake once the CDCLK gets as low as 79200
1771 * picture gets unstable, despite that values are
1772 * correct for DSI PLL and DE PLL.
1773 */
1774 if (display->platform.geminilake)
1775 return 158400;
1776
1777 return 0;
1778 }
1779
1780 typedef void (*vlv_dsi_dmi_quirk_func)(struct intel_dsi *intel_dsi);
1781
1782 /*
1783 * Vtotal is wrong on the Asus TF103C leading to the last line of the display
1784 * being shown as the first line. The factory installed Android has a hardcoded
1785 * modeline, causing it to not suffer from this BIOS bug.
1786 *
1787 * Original mode: "1280x800": 60 67700 1280 1312 1328 1376 800 808 812 820 0x8 0xa
1788 * Fixed mode: "1280x800": 60 67700 1280 1312 1328 1376 800 808 812 816 0x8 0xa
1789 *
1790 * https://gitlab.freedesktop.org/drm/intel/-/issues/9381
1791 */
vlv_dsi_asus_tf103c_mode_fixup(struct intel_dsi * intel_dsi)1792 static void vlv_dsi_asus_tf103c_mode_fixup(struct intel_dsi *intel_dsi)
1793 {
1794 /* Cast away the const as we want to fixup the mode */
1795 struct drm_display_mode *fixed_mode = (struct drm_display_mode *)
1796 intel_panel_preferred_fixed_mode(intel_dsi->attached_connector);
1797
1798 if (fixed_mode->vtotal == 820)
1799 fixed_mode->vtotal -= 4;
1800 }
1801
1802 /*
1803 * On the Lenovo Yoga Tablet 2 830 / 1050 there are 2 problems:
1804 * 1. The I2C MIPI sequence elements reference bus 3. ACPI has I2C1 - I2C7
1805 * which under Linux become bus 0 - 6. And the MIPI sequence reference
1806 * to bus 3 is indented for I2C3 which is bus 2 under Linux.
1807 *
1808 * Note mipi_exec_i2c() cannot just subtract 1 from the bus
1809 * given in the I2C MIPI sequence element. Since on other
1810 * devices the I2C bus-numbers used in the MIPI sequences do
1811 * actually start at 0.
1812 *
1813 * 2. width_/height_mm contain a bogus 192mm x 120mm size. This is
1814 * especially a problem on the 8" 830 version which uses a 10:16
1815 * portrait screen where as the bogus size is 16:10.
1816 *
1817 * https://gitlab.freedesktop.org/drm/intel/-/issues/9379
1818 */
vlv_dsi_lenovo_yoga_tab2_size_fixup(struct intel_dsi * intel_dsi)1819 static void vlv_dsi_lenovo_yoga_tab2_size_fixup(struct intel_dsi *intel_dsi)
1820 {
1821 const struct drm_display_mode *fixed_mode =
1822 intel_panel_preferred_fixed_mode(intel_dsi->attached_connector);
1823 struct drm_display_info *info = &intel_dsi->attached_connector->base.display_info;
1824
1825 intel_dsi->i2c_bus_num = 2;
1826
1827 /*
1828 * The 10" 1050 uses a 1920x1200 landscape screen, where as the 8" 830
1829 * uses a 1200x1920 portrait screen.
1830 */
1831 if (fixed_mode->hdisplay == 1920) {
1832 info->width_mm = 216;
1833 info->height_mm = 135;
1834 } else {
1835 info->width_mm = 107;
1836 info->height_mm = 171;
1837 }
1838 }
1839
1840 /*
1841 * On the Lenovo Yoga Tab 3 Pro YT3-X90F there are 2 problems:
1842 * 1. i2c_acpi_find_adapter() picks the wrong adapter causing mipi_exec_i2c()
1843 * to not work. Fix this by setting i2c_bus_num.
1844 * 2. There is no backlight off MIPI sequence, causing the backlight to stay on.
1845 * Add a backlight off sequence mirroring the existing backlight on sequence.
1846 *
1847 * https://gitlab.freedesktop.org/drm/intel/-/issues/9380
1848 */
vlv_dsi_lenovo_yoga_tab3_backlight_fixup(struct intel_dsi * intel_dsi)1849 static void vlv_dsi_lenovo_yoga_tab3_backlight_fixup(struct intel_dsi *intel_dsi)
1850 {
1851 static const u8 backlight_off_sequence[16] = {
1852 /* Header Seq-id 7, length after header 11 bytes */
1853 0x07, 0x0b, 0x00, 0x00, 0x00,
1854 /* MIPI_SEQ_ELEM_I2C bus 0 addr 0x2c reg 0x00 data-len 1 data 0x00 */
1855 0x04, 0x08, 0x00, 0x00, 0x00, 0x2c, 0x00, 0x00, 0x01, 0x00,
1856 /* MIPI_SEQ_ELEM_END */
1857 0x00
1858 };
1859 struct intel_connector *connector = intel_dsi->attached_connector;
1860
1861 intel_dsi->i2c_bus_num = 0;
1862 connector->panel.vbt.dsi.sequence[MIPI_SEQ_BACKLIGHT_OFF] = backlight_off_sequence;
1863 }
1864
1865 static const struct dmi_system_id vlv_dsi_dmi_quirk_table[] = {
1866 {
1867 /* Asus Transformer Pad TF103C */
1868 .matches = {
1869 DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK COMPUTER INC."),
1870 DMI_MATCH(DMI_PRODUCT_NAME, "TF103C"),
1871 },
1872 .driver_data = (void *)vlv_dsi_asus_tf103c_mode_fixup,
1873 },
1874 {
1875 /*
1876 * Lenovo Yoga Tablet 2 830F/L or 1050F/L (The 8" and 10"
1877 * Lenovo Yoga Tablet 2 use the same mainboard)
1878 */
1879 .matches = {
1880 DMI_MATCH(DMI_SYS_VENDOR, "Intel Corp."),
1881 DMI_MATCH(DMI_PRODUCT_NAME, "VALLEYVIEW C0 PLATFORM"),
1882 DMI_MATCH(DMI_BOARD_NAME, "BYT-T FFD8"),
1883 /* Partial match on beginning of BIOS version */
1884 DMI_MATCH(DMI_BIOS_VERSION, "BLADE_21"),
1885 },
1886 .driver_data = (void *)vlv_dsi_lenovo_yoga_tab2_size_fixup,
1887 },
1888 {
1889 /* Lenovo Yoga Tab 3 Pro YT3-X90F */
1890 .matches = {
1891 DMI_MATCH(DMI_SYS_VENDOR, "Intel Corporation"),
1892 DMI_MATCH(DMI_PRODUCT_VERSION, "Blade3-10A-001"),
1893 },
1894 .driver_data = (void *)vlv_dsi_lenovo_yoga_tab3_backlight_fixup,
1895 },
1896 { }
1897 };
1898
vlv_dsi_init(struct intel_display * display)1899 void vlv_dsi_init(struct intel_display *display)
1900 {
1901 struct intel_dsi *intel_dsi;
1902 struct intel_encoder *encoder;
1903 struct intel_connector *connector;
1904 struct drm_display_mode *current_mode;
1905 const struct dmi_system_id *dmi_id;
1906 enum port port;
1907 enum pipe pipe;
1908
1909 drm_dbg_kms(display->drm, "\n");
1910
1911 /* There is no detection method for MIPI so rely on VBT */
1912 if (!intel_bios_is_dsi_present(display, &port))
1913 return;
1914
1915 if (display->platform.geminilake || display->platform.broxton)
1916 display->dsi.mmio_base = BXT_MIPI_BASE;
1917 else
1918 display->dsi.mmio_base = VLV_MIPI_BASE;
1919
1920 intel_dsi = kzalloc(sizeof(*intel_dsi), GFP_KERNEL);
1921 if (!intel_dsi)
1922 return;
1923
1924 connector = intel_connector_alloc();
1925 if (!connector) {
1926 kfree(intel_dsi);
1927 return;
1928 }
1929
1930 encoder = &intel_dsi->base;
1931 intel_dsi->attached_connector = connector;
1932
1933 drm_encoder_init(display->drm, &encoder->base, &intel_dsi_funcs,
1934 DRM_MODE_ENCODER_DSI, "DSI %c", port_name(port));
1935
1936 encoder->compute_config = intel_dsi_compute_config;
1937 encoder->pre_enable = intel_dsi_pre_enable;
1938 if (display->platform.geminilake || display->platform.broxton)
1939 encoder->enable = bxt_dsi_enable;
1940 encoder->disable = intel_dsi_disable;
1941 encoder->post_disable = intel_dsi_post_disable;
1942 encoder->get_hw_state = intel_dsi_get_hw_state;
1943 encoder->get_config = intel_dsi_get_config;
1944 encoder->update_pipe = intel_backlight_update;
1945 encoder->shutdown = intel_dsi_shutdown;
1946
1947 connector->get_hw_state = intel_connector_get_hw_state;
1948
1949 encoder->port = port;
1950 encoder->type = INTEL_OUTPUT_DSI;
1951 encoder->power_domain = POWER_DOMAIN_PORT_DSI;
1952 encoder->cloneable = 0;
1953
1954 /*
1955 * On BYT/CHV, pipe A maps to MIPI DSI port A, pipe B maps to MIPI DSI
1956 * port C. BXT isn't limited like this.
1957 */
1958 if (display->platform.geminilake || display->platform.broxton)
1959 encoder->pipe_mask = ~0;
1960 else if (port == PORT_A)
1961 encoder->pipe_mask = BIT(PIPE_A);
1962 else
1963 encoder->pipe_mask = BIT(PIPE_B);
1964
1965 intel_dsi->panel_power_off_time = ktime_get_boottime();
1966
1967 intel_bios_init_panel_late(display, &connector->panel, NULL, NULL);
1968
1969 if (connector->panel.vbt.dsi.config->dual_link)
1970 intel_dsi->ports = BIT(PORT_A) | BIT(PORT_C);
1971 else
1972 intel_dsi->ports = BIT(port);
1973
1974 if (drm_WARN_ON(display->drm, connector->panel.vbt.dsi.bl_ports & ~intel_dsi->ports))
1975 connector->panel.vbt.dsi.bl_ports &= intel_dsi->ports;
1976
1977 if (drm_WARN_ON(display->drm, connector->panel.vbt.dsi.cabc_ports & ~intel_dsi->ports))
1978 connector->panel.vbt.dsi.cabc_ports &= intel_dsi->ports;
1979
1980 /* Create a DSI host (and a device) for each port. */
1981 for_each_dsi_port(port, intel_dsi->ports) {
1982 struct intel_dsi_host *host;
1983
1984 host = intel_dsi_host_init(intel_dsi, &intel_dsi_host_ops,
1985 port);
1986 if (!host)
1987 goto err;
1988
1989 intel_dsi->dsi_hosts[port] = host;
1990 }
1991
1992 if (!intel_dsi_vbt_init(intel_dsi, MIPI_DSI_GENERIC_PANEL_ID)) {
1993 drm_dbg_kms(display->drm, "no device found\n");
1994 goto err;
1995 }
1996
1997 /* Use clock read-back from current hw-state for fastboot */
1998 current_mode = intel_encoder_current_mode(encoder);
1999 if (current_mode) {
2000 drm_dbg_kms(display->drm, "Calculated pclk %d GOP %d\n",
2001 intel_dsi->pclk, current_mode->clock);
2002 if (intel_fuzzy_clock_check(intel_dsi->pclk,
2003 current_mode->clock)) {
2004 drm_dbg_kms(display->drm, "Using GOP pclk\n");
2005 intel_dsi->pclk = current_mode->clock;
2006 }
2007
2008 kfree(current_mode);
2009 }
2010
2011 vlv_dphy_param_init(intel_dsi);
2012
2013 intel_dsi_vbt_gpio_init(intel_dsi,
2014 intel_dsi_get_hw_state(encoder, &pipe));
2015
2016 drm_connector_init(display->drm, &connector->base, &intel_dsi_connector_funcs,
2017 DRM_MODE_CONNECTOR_DSI);
2018
2019 drm_connector_helper_add(&connector->base, &intel_dsi_connector_helper_funcs);
2020
2021 connector->base.display_info.subpixel_order = SubPixelHorizontalRGB; /*XXX*/
2022
2023 intel_connector_attach_encoder(connector, encoder);
2024
2025 mutex_lock(&display->drm->mode_config.mutex);
2026 intel_panel_add_vbt_lfp_fixed_mode(connector);
2027 mutex_unlock(&display->drm->mode_config.mutex);
2028
2029 if (!intel_panel_preferred_fixed_mode(connector)) {
2030 drm_dbg_kms(display->drm, "no fixed mode\n");
2031 goto err_cleanup_connector;
2032 }
2033
2034 dmi_id = dmi_first_match(vlv_dsi_dmi_quirk_table);
2035 if (dmi_id) {
2036 vlv_dsi_dmi_quirk_func quirk_func =
2037 (vlv_dsi_dmi_quirk_func)dmi_id->driver_data;
2038
2039 quirk_func(intel_dsi);
2040 }
2041
2042 intel_panel_init(connector, NULL);
2043
2044 intel_backlight_setup(connector, INVALID_PIPE);
2045
2046 vlv_dsi_add_properties(connector);
2047
2048 return;
2049
2050 err_cleanup_connector:
2051 drm_connector_cleanup(&connector->base);
2052 err:
2053 drm_encoder_cleanup(&encoder->base);
2054 kfree(intel_dsi);
2055 kfree(connector);
2056 }
2057