1 /*
2 * Copyright © 2013 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Author: Jani Nikula <jani.nikula@intel.com>
24 */
25
26 #include <linux/dmi.h>
27 #include <linux/slab.h>
28
29 #include <drm/drm_atomic_helper.h>
30 #include <drm/drm_crtc.h>
31 #include <drm/drm_edid.h>
32 #include <drm/drm_mipi_dsi.h>
33 #include <drm/drm_probe_helper.h>
34
35 #include "i915_drv.h"
36 #include "i915_reg.h"
37 #include "intel_atomic.h"
38 #include "intel_backlight.h"
39 #include "intel_connector.h"
40 #include "intel_crtc.h"
41 #include "intel_de.h"
42 #include "intel_display_types.h"
43 #include "intel_dsi.h"
44 #include "intel_dsi_vbt.h"
45 #include "intel_fifo_underrun.h"
46 #include "intel_panel.h"
47 #include "intel_pfit.h"
48 #include "skl_scaler.h"
49 #include "vlv_dsi.h"
50 #include "vlv_dsi_pll.h"
51 #include "vlv_dsi_regs.h"
52 #include "vlv_sideband.h"
53
54 /* return pixels in terms of txbyteclkhs */
txbyteclkhs(u16 pixels,int bpp,int lane_count,u16 burst_mode_ratio)55 static u16 txbyteclkhs(u16 pixels, int bpp, int lane_count,
56 u16 burst_mode_ratio)
57 {
58 return DIV_ROUND_UP(DIV_ROUND_UP(pixels * bpp * burst_mode_ratio,
59 8 * 100), lane_count);
60 }
61
62 /* return pixels equvalent to txbyteclkhs */
pixels_from_txbyteclkhs(u16 clk_hs,int bpp,int lane_count,u16 burst_mode_ratio)63 static u16 pixels_from_txbyteclkhs(u16 clk_hs, int bpp, int lane_count,
64 u16 burst_mode_ratio)
65 {
66 return DIV_ROUND_UP((clk_hs * lane_count * 8 * 100),
67 (bpp * burst_mode_ratio));
68 }
69
pixel_format_from_register_bits(u32 fmt)70 static enum mipi_dsi_pixel_format pixel_format_from_register_bits(u32 fmt)
71 {
72 switch (fmt) {
73 case VID_MODE_FORMAT_RGB888:
74 return MIPI_DSI_FMT_RGB888;
75 case VID_MODE_FORMAT_RGB666:
76 return MIPI_DSI_FMT_RGB666;
77 case VID_MODE_FORMAT_RGB666_PACKED:
78 return MIPI_DSI_FMT_RGB666_PACKED;
79 case VID_MODE_FORMAT_RGB565:
80 return MIPI_DSI_FMT_RGB565;
81 default:
82 MISSING_CASE(fmt);
83 return MIPI_DSI_FMT_RGB666;
84 }
85 }
86
vlv_dsi_wait_for_fifo_empty(struct intel_dsi * intel_dsi,enum port port)87 void vlv_dsi_wait_for_fifo_empty(struct intel_dsi *intel_dsi, enum port port)
88 {
89 struct intel_display *display = to_intel_display(&intel_dsi->base);
90 u32 mask;
91
92 mask = LP_CTRL_FIFO_EMPTY | HS_CTRL_FIFO_EMPTY |
93 LP_DATA_FIFO_EMPTY | HS_DATA_FIFO_EMPTY;
94
95 if (intel_de_wait_for_set(display, MIPI_GEN_FIFO_STAT(display, port),
96 mask, 100))
97 drm_err(display->drm, "DPI FIFOs are not empty\n");
98 }
99
write_data(struct intel_display * display,i915_reg_t reg,const u8 * data,u32 len)100 static void write_data(struct intel_display *display,
101 i915_reg_t reg,
102 const u8 *data, u32 len)
103 {
104 u32 i, j;
105
106 for (i = 0; i < len; i += 4) {
107 u32 val = 0;
108
109 for (j = 0; j < min_t(u32, len - i, 4); j++)
110 val |= *data++ << 8 * j;
111
112 intel_de_write(display, reg, val);
113 }
114 }
115
read_data(struct intel_display * display,i915_reg_t reg,u8 * data,u32 len)116 static void read_data(struct intel_display *display,
117 i915_reg_t reg,
118 u8 *data, u32 len)
119 {
120 u32 i, j;
121
122 for (i = 0; i < len; i += 4) {
123 u32 val = intel_de_read(display, reg);
124
125 for (j = 0; j < min_t(u32, len - i, 4); j++)
126 *data++ = val >> 8 * j;
127 }
128 }
129
intel_dsi_host_transfer(struct mipi_dsi_host * host,const struct mipi_dsi_msg * msg)130 static ssize_t intel_dsi_host_transfer(struct mipi_dsi_host *host,
131 const struct mipi_dsi_msg *msg)
132 {
133 struct intel_dsi_host *intel_dsi_host = to_intel_dsi_host(host);
134 struct intel_dsi *intel_dsi = intel_dsi_host->intel_dsi;
135 struct intel_display *display = to_intel_display(&intel_dsi->base);
136 enum port port = intel_dsi_host->port;
137 struct mipi_dsi_packet packet;
138 ssize_t ret;
139 const u8 *header;
140 i915_reg_t data_reg, ctrl_reg;
141 u32 data_mask, ctrl_mask;
142
143 ret = mipi_dsi_create_packet(&packet, msg);
144 if (ret < 0)
145 return ret;
146
147 header = packet.header;
148
149 if (msg->flags & MIPI_DSI_MSG_USE_LPM) {
150 data_reg = MIPI_LP_GEN_DATA(display, port);
151 data_mask = LP_DATA_FIFO_FULL;
152 ctrl_reg = MIPI_LP_GEN_CTRL(display, port);
153 ctrl_mask = LP_CTRL_FIFO_FULL;
154 } else {
155 data_reg = MIPI_HS_GEN_DATA(display, port);
156 data_mask = HS_DATA_FIFO_FULL;
157 ctrl_reg = MIPI_HS_GEN_CTRL(display, port);
158 ctrl_mask = HS_CTRL_FIFO_FULL;
159 }
160
161 /* note: this is never true for reads */
162 if (packet.payload_length) {
163 if (intel_de_wait_for_clear(display, MIPI_GEN_FIFO_STAT(display, port),
164 data_mask, 50))
165 drm_err(display->drm,
166 "Timeout waiting for HS/LP DATA FIFO !full\n");
167
168 write_data(display, data_reg, packet.payload,
169 packet.payload_length);
170 }
171
172 if (msg->rx_len) {
173 intel_de_write(display, MIPI_INTR_STAT(display, port),
174 GEN_READ_DATA_AVAIL);
175 }
176
177 if (intel_de_wait_for_clear(display, MIPI_GEN_FIFO_STAT(display, port),
178 ctrl_mask, 50)) {
179 drm_err(display->drm,
180 "Timeout waiting for HS/LP CTRL FIFO !full\n");
181 }
182
183 intel_de_write(display, ctrl_reg,
184 header[2] << 16 | header[1] << 8 | header[0]);
185
186 /* ->rx_len is set only for reads */
187 if (msg->rx_len) {
188 data_mask = GEN_READ_DATA_AVAIL;
189 if (intel_de_wait_for_set(display, MIPI_INTR_STAT(display, port),
190 data_mask, 50))
191 drm_err(display->drm,
192 "Timeout waiting for read data.\n");
193
194 read_data(display, data_reg, msg->rx_buf, msg->rx_len);
195 }
196
197 /* XXX: fix for reads and writes */
198 return 4 + packet.payload_length;
199 }
200
intel_dsi_host_attach(struct mipi_dsi_host * host,struct mipi_dsi_device * dsi)201 static int intel_dsi_host_attach(struct mipi_dsi_host *host,
202 struct mipi_dsi_device *dsi)
203 {
204 return 0;
205 }
206
intel_dsi_host_detach(struct mipi_dsi_host * host,struct mipi_dsi_device * dsi)207 static int intel_dsi_host_detach(struct mipi_dsi_host *host,
208 struct mipi_dsi_device *dsi)
209 {
210 return 0;
211 }
212
213 static const struct mipi_dsi_host_ops intel_dsi_host_ops = {
214 .attach = intel_dsi_host_attach,
215 .detach = intel_dsi_host_detach,
216 .transfer = intel_dsi_host_transfer,
217 };
218
219 /*
220 * send a video mode command
221 *
222 * XXX: commands with data in MIPI_DPI_DATA?
223 */
dpi_send_cmd(struct intel_dsi * intel_dsi,u32 cmd,bool hs,enum port port)224 static int dpi_send_cmd(struct intel_dsi *intel_dsi, u32 cmd, bool hs,
225 enum port port)
226 {
227 struct intel_display *display = to_intel_display(&intel_dsi->base);
228 u32 mask;
229
230 /* XXX: pipe, hs */
231 if (hs)
232 cmd &= ~DPI_LP_MODE;
233 else
234 cmd |= DPI_LP_MODE;
235
236 /* clear bit */
237 intel_de_write(display, MIPI_INTR_STAT(display, port), SPL_PKT_SENT_INTERRUPT);
238
239 /* XXX: old code skips write if control unchanged */
240 if (cmd == intel_de_read(display, MIPI_DPI_CONTROL(display, port)))
241 drm_dbg_kms(display->drm,
242 "Same special packet %02x twice in a row.\n", cmd);
243
244 intel_de_write(display, MIPI_DPI_CONTROL(display, port), cmd);
245
246 mask = SPL_PKT_SENT_INTERRUPT;
247 if (intel_de_wait_for_set(display, MIPI_INTR_STAT(display, port), mask, 100))
248 drm_err(display->drm,
249 "Video mode command 0x%08x send failed.\n", cmd);
250
251 return 0;
252 }
253
band_gap_reset(struct drm_i915_private * dev_priv)254 static void band_gap_reset(struct drm_i915_private *dev_priv)
255 {
256 vlv_flisdsi_get(dev_priv);
257
258 vlv_flisdsi_write(dev_priv, 0x08, 0x0001);
259 vlv_flisdsi_write(dev_priv, 0x0F, 0x0005);
260 vlv_flisdsi_write(dev_priv, 0x0F, 0x0025);
261 udelay(150);
262 vlv_flisdsi_write(dev_priv, 0x0F, 0x0000);
263 vlv_flisdsi_write(dev_priv, 0x08, 0x0000);
264
265 vlv_flisdsi_put(dev_priv);
266 }
267
intel_dsi_compute_config(struct intel_encoder * encoder,struct intel_crtc_state * pipe_config,struct drm_connector_state * conn_state)268 static int intel_dsi_compute_config(struct intel_encoder *encoder,
269 struct intel_crtc_state *pipe_config,
270 struct drm_connector_state *conn_state)
271 {
272 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
273 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
274 struct intel_connector *intel_connector = intel_dsi->attached_connector;
275 struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
276 int ret;
277
278 drm_dbg_kms(&dev_priv->drm, "\n");
279 pipe_config->sink_format = INTEL_OUTPUT_FORMAT_RGB;
280 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
281
282 ret = intel_panel_compute_config(intel_connector, adjusted_mode);
283 if (ret)
284 return ret;
285
286 ret = intel_panel_fitting(pipe_config, conn_state);
287 if (ret)
288 return ret;
289
290 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
291 return -EINVAL;
292
293 /* DSI uses short packets for sync events, so clear mode flags for DSI */
294 adjusted_mode->flags = 0;
295
296 if (intel_dsi->pixel_format == MIPI_DSI_FMT_RGB888)
297 pipe_config->pipe_bpp = 24;
298 else
299 pipe_config->pipe_bpp = 18;
300
301 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
302 /* Enable Frame time stamp based scanline reporting */
303 pipe_config->mode_flags |=
304 I915_MODE_FLAG_GET_SCANLINE_FROM_TIMESTAMP;
305
306 /* Dual link goes to DSI transcoder A. */
307 if (intel_dsi->ports == BIT(PORT_C))
308 pipe_config->cpu_transcoder = TRANSCODER_DSI_C;
309 else
310 pipe_config->cpu_transcoder = TRANSCODER_DSI_A;
311
312 ret = bxt_dsi_pll_compute(encoder, pipe_config);
313 if (ret)
314 return -EINVAL;
315 } else {
316 ret = vlv_dsi_pll_compute(encoder, pipe_config);
317 if (ret)
318 return -EINVAL;
319 }
320
321 pipe_config->clock_set = true;
322
323 return 0;
324 }
325
glk_dsi_enable_io(struct intel_encoder * encoder)326 static bool glk_dsi_enable_io(struct intel_encoder *encoder)
327 {
328 struct intel_display *display = to_intel_display(encoder);
329 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
330 enum port port;
331 bool cold_boot = false;
332
333 /* Set the MIPI mode
334 * If MIPI_Mode is off, then writing to LP_Wake bit is not reflecting.
335 * Power ON MIPI IO first and then write into IO reset and LP wake bits
336 */
337 for_each_dsi_port(port, intel_dsi->ports)
338 intel_de_rmw(display, MIPI_CTRL(display, port), 0, GLK_MIPIIO_ENABLE);
339
340 /* Put the IO into reset */
341 intel_de_rmw(display, MIPI_CTRL(display, PORT_A), GLK_MIPIIO_RESET_RELEASED, 0);
342
343 /* Program LP Wake */
344 for_each_dsi_port(port, intel_dsi->ports) {
345 u32 tmp = intel_de_read(display, MIPI_DEVICE_READY(display, port));
346
347 intel_de_rmw(display, MIPI_CTRL(display, port),
348 GLK_LP_WAKE, (tmp & DEVICE_READY) ? GLK_LP_WAKE : 0);
349 }
350
351 /* Wait for Pwr ACK */
352 for_each_dsi_port(port, intel_dsi->ports) {
353 if (intel_de_wait_for_set(display, MIPI_CTRL(display, port),
354 GLK_MIPIIO_PORT_POWERED, 20))
355 drm_err(display->drm, "MIPIO port is powergated\n");
356 }
357
358 /* Check for cold boot scenario */
359 for_each_dsi_port(port, intel_dsi->ports) {
360 cold_boot |=
361 !(intel_de_read(display, MIPI_DEVICE_READY(display, port)) & DEVICE_READY);
362 }
363
364 return cold_boot;
365 }
366
glk_dsi_device_ready(struct intel_encoder * encoder)367 static void glk_dsi_device_ready(struct intel_encoder *encoder)
368 {
369 struct intel_display *display = to_intel_display(encoder);
370 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
371 enum port port;
372
373 /* Wait for MIPI PHY status bit to set */
374 for_each_dsi_port(port, intel_dsi->ports) {
375 if (intel_de_wait_for_set(display, MIPI_CTRL(display, port),
376 GLK_PHY_STATUS_PORT_READY, 20))
377 drm_err(display->drm, "PHY is not ON\n");
378 }
379
380 /* Get IO out of reset */
381 intel_de_rmw(display, MIPI_CTRL(display, PORT_A), 0, GLK_MIPIIO_RESET_RELEASED);
382
383 /* Get IO out of Low power state*/
384 for_each_dsi_port(port, intel_dsi->ports) {
385 if (!(intel_de_read(display, MIPI_DEVICE_READY(display, port)) & DEVICE_READY)) {
386 intel_de_rmw(display, MIPI_DEVICE_READY(display, port),
387 ULPS_STATE_MASK, DEVICE_READY);
388 usleep_range(10, 15);
389 } else {
390 /* Enter ULPS */
391 intel_de_rmw(display, MIPI_DEVICE_READY(display, port),
392 ULPS_STATE_MASK, ULPS_STATE_ENTER | DEVICE_READY);
393
394 /* Wait for ULPS active */
395 if (intel_de_wait_for_clear(display, MIPI_CTRL(display, port),
396 GLK_ULPS_NOT_ACTIVE, 20))
397 drm_err(display->drm, "ULPS not active\n");
398
399 /* Exit ULPS */
400 intel_de_rmw(display, MIPI_DEVICE_READY(display, port),
401 ULPS_STATE_MASK, ULPS_STATE_EXIT | DEVICE_READY);
402
403 /* Enter Normal Mode */
404 intel_de_rmw(display, MIPI_DEVICE_READY(display, port),
405 ULPS_STATE_MASK,
406 ULPS_STATE_NORMAL_OPERATION | DEVICE_READY);
407
408 intel_de_rmw(display, MIPI_CTRL(display, port), GLK_LP_WAKE, 0);
409 }
410 }
411
412 /* Wait for Stop state */
413 for_each_dsi_port(port, intel_dsi->ports) {
414 if (intel_de_wait_for_set(display, MIPI_CTRL(display, port),
415 GLK_DATA_LANE_STOP_STATE, 20))
416 drm_err(display->drm,
417 "Date lane not in STOP state\n");
418 }
419
420 /* Wait for AFE LATCH */
421 for_each_dsi_port(port, intel_dsi->ports) {
422 if (intel_de_wait_for_set(display, BXT_MIPI_PORT_CTRL(port),
423 AFE_LATCHOUT, 20))
424 drm_err(display->drm,
425 "D-PHY not entering LP-11 state\n");
426 }
427 }
428
bxt_dsi_device_ready(struct intel_encoder * encoder)429 static void bxt_dsi_device_ready(struct intel_encoder *encoder)
430 {
431 struct intel_display *display = to_intel_display(encoder);
432 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
433 enum port port;
434 u32 val;
435
436 drm_dbg_kms(display->drm, "\n");
437
438 /* Enable MIPI PHY transparent latch */
439 for_each_dsi_port(port, intel_dsi->ports) {
440 intel_de_rmw(display, BXT_MIPI_PORT_CTRL(port), 0, LP_OUTPUT_HOLD);
441 usleep_range(2000, 2500);
442 }
443
444 /* Clear ULPS and set device ready */
445 for_each_dsi_port(port, intel_dsi->ports) {
446 val = intel_de_read(display, MIPI_DEVICE_READY(display, port));
447 val &= ~ULPS_STATE_MASK;
448 intel_de_write(display, MIPI_DEVICE_READY(display, port), val);
449 usleep_range(2000, 2500);
450 val |= DEVICE_READY;
451 intel_de_write(display, MIPI_DEVICE_READY(display, port), val);
452 }
453 }
454
vlv_dsi_device_ready(struct intel_encoder * encoder)455 static void vlv_dsi_device_ready(struct intel_encoder *encoder)
456 {
457 struct intel_display *display = to_intel_display(encoder);
458 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
459 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
460 enum port port;
461
462 drm_dbg_kms(display->drm, "\n");
463
464 vlv_flisdsi_get(dev_priv);
465 /* program rcomp for compliance, reduce from 50 ohms to 45 ohms
466 * needed everytime after power gate */
467 vlv_flisdsi_write(dev_priv, 0x04, 0x0004);
468 vlv_flisdsi_put(dev_priv);
469
470 /* bandgap reset is needed after everytime we do power gate */
471 band_gap_reset(dev_priv);
472
473 for_each_dsi_port(port, intel_dsi->ports) {
474
475 intel_de_write(display, MIPI_DEVICE_READY(display, port),
476 ULPS_STATE_ENTER);
477 usleep_range(2500, 3000);
478
479 /* Enable MIPI PHY transparent latch
480 * Common bit for both MIPI Port A & MIPI Port C
481 * No similar bit in MIPI Port C reg
482 */
483 intel_de_rmw(display, VLV_MIPI_PORT_CTRL(PORT_A), 0, LP_OUTPUT_HOLD);
484 usleep_range(1000, 1500);
485
486 intel_de_write(display, MIPI_DEVICE_READY(display, port),
487 ULPS_STATE_EXIT);
488 usleep_range(2500, 3000);
489
490 intel_de_write(display, MIPI_DEVICE_READY(display, port),
491 DEVICE_READY);
492 usleep_range(2500, 3000);
493 }
494 }
495
intel_dsi_device_ready(struct intel_encoder * encoder)496 static void intel_dsi_device_ready(struct intel_encoder *encoder)
497 {
498 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
499
500 if (IS_GEMINILAKE(dev_priv))
501 glk_dsi_device_ready(encoder);
502 else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
503 bxt_dsi_device_ready(encoder);
504 else
505 vlv_dsi_device_ready(encoder);
506 }
507
glk_dsi_enter_low_power_mode(struct intel_encoder * encoder)508 static void glk_dsi_enter_low_power_mode(struct intel_encoder *encoder)
509 {
510 struct intel_display *display = to_intel_display(encoder);
511 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
512 enum port port;
513
514 /* Enter ULPS */
515 for_each_dsi_port(port, intel_dsi->ports)
516 intel_de_rmw(display, MIPI_DEVICE_READY(display, port),
517 ULPS_STATE_MASK, ULPS_STATE_ENTER | DEVICE_READY);
518
519 /* Wait for MIPI PHY status bit to unset */
520 for_each_dsi_port(port, intel_dsi->ports) {
521 if (intel_de_wait_for_clear(display, MIPI_CTRL(display, port),
522 GLK_PHY_STATUS_PORT_READY, 20))
523 drm_err(display->drm, "PHY is not turning OFF\n");
524 }
525
526 /* Wait for Pwr ACK bit to unset */
527 for_each_dsi_port(port, intel_dsi->ports) {
528 if (intel_de_wait_for_clear(display, MIPI_CTRL(display, port),
529 GLK_MIPIIO_PORT_POWERED, 20))
530 drm_err(display->drm,
531 "MIPI IO Port is not powergated\n");
532 }
533 }
534
glk_dsi_disable_mipi_io(struct intel_encoder * encoder)535 static void glk_dsi_disable_mipi_io(struct intel_encoder *encoder)
536 {
537 struct intel_display *display = to_intel_display(encoder);
538 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
539 enum port port;
540
541 /* Put the IO into reset */
542 intel_de_rmw(display, MIPI_CTRL(display, PORT_A), GLK_MIPIIO_RESET_RELEASED, 0);
543
544 /* Wait for MIPI PHY status bit to unset */
545 for_each_dsi_port(port, intel_dsi->ports) {
546 if (intel_de_wait_for_clear(display, MIPI_CTRL(display, port),
547 GLK_PHY_STATUS_PORT_READY, 20))
548 drm_err(display->drm, "PHY is not turning OFF\n");
549 }
550
551 /* Clear MIPI mode */
552 for_each_dsi_port(port, intel_dsi->ports)
553 intel_de_rmw(display, MIPI_CTRL(display, port), GLK_MIPIIO_ENABLE, 0);
554 }
555
glk_dsi_clear_device_ready(struct intel_encoder * encoder)556 static void glk_dsi_clear_device_ready(struct intel_encoder *encoder)
557 {
558 glk_dsi_enter_low_power_mode(encoder);
559 glk_dsi_disable_mipi_io(encoder);
560 }
561
port_ctrl_reg(struct drm_i915_private * i915,enum port port)562 static i915_reg_t port_ctrl_reg(struct drm_i915_private *i915, enum port port)
563 {
564 return IS_GEMINILAKE(i915) || IS_BROXTON(i915) ?
565 BXT_MIPI_PORT_CTRL(port) : VLV_MIPI_PORT_CTRL(port);
566 }
567
vlv_dsi_clear_device_ready(struct intel_encoder * encoder)568 static void vlv_dsi_clear_device_ready(struct intel_encoder *encoder)
569 {
570 struct intel_display *display = to_intel_display(encoder);
571 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
572 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
573 enum port port;
574
575 drm_dbg_kms(display->drm, "\n");
576 for_each_dsi_port(port, intel_dsi->ports) {
577 /* Common bit for both MIPI Port A & MIPI Port C on VLV/CHV */
578 i915_reg_t port_ctrl = IS_BROXTON(dev_priv) ?
579 BXT_MIPI_PORT_CTRL(port) : VLV_MIPI_PORT_CTRL(PORT_A);
580
581 intel_de_write(display, MIPI_DEVICE_READY(display, port),
582 DEVICE_READY | ULPS_STATE_ENTER);
583 usleep_range(2000, 2500);
584
585 intel_de_write(display, MIPI_DEVICE_READY(display, port),
586 DEVICE_READY | ULPS_STATE_EXIT);
587 usleep_range(2000, 2500);
588
589 intel_de_write(display, MIPI_DEVICE_READY(display, port),
590 DEVICE_READY | ULPS_STATE_ENTER);
591 usleep_range(2000, 2500);
592
593 /*
594 * On VLV/CHV, wait till Clock lanes are in LP-00 state for MIPI
595 * Port A only. MIPI Port C has no similar bit for checking.
596 */
597 if ((IS_BROXTON(dev_priv) || port == PORT_A) &&
598 intel_de_wait_for_clear(display, port_ctrl,
599 AFE_LATCHOUT, 30))
600 drm_err(display->drm, "DSI LP not going Low\n");
601
602 /* Disable MIPI PHY transparent latch */
603 intel_de_rmw(display, port_ctrl, LP_OUTPUT_HOLD, 0);
604 usleep_range(1000, 1500);
605
606 intel_de_write(display, MIPI_DEVICE_READY(display, port), 0x00);
607 usleep_range(2000, 2500);
608 }
609 }
610
intel_dsi_port_enable(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state)611 static void intel_dsi_port_enable(struct intel_encoder *encoder,
612 const struct intel_crtc_state *crtc_state)
613 {
614 struct intel_display *display = to_intel_display(encoder);
615 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
616 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
617 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
618 enum port port;
619
620 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) {
621 u32 temp = intel_dsi->pixel_overlap;
622
623 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
624 for_each_dsi_port(port, intel_dsi->ports)
625 intel_de_rmw(display, MIPI_CTRL(display, port),
626 BXT_PIXEL_OVERLAP_CNT_MASK,
627 temp << BXT_PIXEL_OVERLAP_CNT_SHIFT);
628 } else {
629 intel_de_rmw(display, VLV_CHICKEN_3,
630 PIXEL_OVERLAP_CNT_MASK,
631 temp << PIXEL_OVERLAP_CNT_SHIFT);
632 }
633 }
634
635 for_each_dsi_port(port, intel_dsi->ports) {
636 i915_reg_t port_ctrl = port_ctrl_reg(dev_priv, port);
637 u32 temp;
638
639 temp = intel_de_read(display, port_ctrl);
640
641 temp &= ~LANE_CONFIGURATION_MASK;
642 temp &= ~DUAL_LINK_MODE_MASK;
643
644 if (intel_dsi->ports == (BIT(PORT_A) | BIT(PORT_C))) {
645 temp |= (intel_dsi->dual_link - 1)
646 << DUAL_LINK_MODE_SHIFT;
647 if (IS_BROXTON(dev_priv))
648 temp |= LANE_CONFIGURATION_DUAL_LINK_A;
649 else
650 temp |= crtc->pipe ?
651 LANE_CONFIGURATION_DUAL_LINK_B :
652 LANE_CONFIGURATION_DUAL_LINK_A;
653 }
654
655 if (intel_dsi->pixel_format != MIPI_DSI_FMT_RGB888)
656 temp |= DITHERING_ENABLE;
657
658 /* assert ip_tg_enable signal */
659 intel_de_write(display, port_ctrl, temp | DPI_ENABLE);
660 intel_de_posting_read(display, port_ctrl);
661 }
662 }
663
intel_dsi_port_disable(struct intel_encoder * encoder)664 static void intel_dsi_port_disable(struct intel_encoder *encoder)
665 {
666 struct intel_display *display = to_intel_display(encoder);
667 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
668 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
669 enum port port;
670
671 for_each_dsi_port(port, intel_dsi->ports) {
672 i915_reg_t port_ctrl = port_ctrl_reg(dev_priv, port);
673
674 /* de-assert ip_tg_enable signal */
675 intel_de_rmw(display, port_ctrl, DPI_ENABLE, 0);
676 intel_de_posting_read(display, port_ctrl);
677 }
678 }
679
680 static void intel_dsi_prepare(struct intel_encoder *encoder,
681 const struct intel_crtc_state *pipe_config);
682 static void intel_dsi_unprepare(struct intel_encoder *encoder);
683
684 /*
685 * Panel enable/disable sequences from the VBT spec.
686 *
687 * Note the spec has AssertReset / DeassertReset swapped from their
688 * usual naming. We use the normal names to avoid confusion (so below
689 * they are swapped compared to the spec).
690 *
691 * Steps starting with MIPI refer to VBT sequences, note that for v2
692 * VBTs several steps which have a VBT in v2 are expected to be handled
693 * directly by the driver, by directly driving gpios for example.
694 *
695 * v2 video mode seq v3 video mode seq command mode seq
696 * - power on - MIPIPanelPowerOn - power on
697 * - wait t1+t2 - wait t1+t2
698 * - MIPIDeassertResetPin - MIPIDeassertResetPin - MIPIDeassertResetPin
699 * - io lines to lp-11 - io lines to lp-11 - io lines to lp-11
700 * - MIPISendInitialDcsCmds - MIPISendInitialDcsCmds - MIPISendInitialDcsCmds
701 * - MIPITearOn
702 * - MIPIDisplayOn
703 * - turn on DPI - turn on DPI - set pipe to dsr mode
704 * - MIPIDisplayOn - MIPIDisplayOn
705 * - wait t5 - wait t5
706 * - backlight on - MIPIBacklightOn - backlight on
707 * ... ... ... issue mem cmds ...
708 * - backlight off - MIPIBacklightOff - backlight off
709 * - wait t6 - wait t6
710 * - MIPIDisplayOff
711 * - turn off DPI - turn off DPI - disable pipe dsr mode
712 * - MIPITearOff
713 * - MIPIDisplayOff - MIPIDisplayOff
714 * - io lines to lp-00 - io lines to lp-00 - io lines to lp-00
715 * - MIPIAssertResetPin - MIPIAssertResetPin - MIPIAssertResetPin
716 * - wait t3 - wait t3
717 * - power off - MIPIPanelPowerOff - power off
718 * - wait t4 - wait t4
719 */
720
721 /*
722 * DSI port enable has to be done before pipe and plane enable, so we do it in
723 * the pre_enable hook instead of the enable hook.
724 */
intel_dsi_pre_enable(struct intel_atomic_state * state,struct intel_encoder * encoder,const struct intel_crtc_state * pipe_config,const struct drm_connector_state * conn_state)725 static void intel_dsi_pre_enable(struct intel_atomic_state *state,
726 struct intel_encoder *encoder,
727 const struct intel_crtc_state *pipe_config,
728 const struct drm_connector_state *conn_state)
729 {
730 struct intel_display *display = to_intel_display(encoder);
731 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
732 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
733 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
734 enum pipe pipe = crtc->pipe;
735 enum port port;
736 bool glk_cold_boot = false;
737
738 drm_dbg_kms(display->drm, "\n");
739
740 intel_dsi_wait_panel_power_cycle(intel_dsi);
741
742 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
743
744 /*
745 * The BIOS may leave the PLL in a wonky state where it doesn't
746 * lock. It needs to be fully powered down to fix it.
747 */
748 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
749 bxt_dsi_pll_disable(encoder);
750 bxt_dsi_pll_enable(encoder, pipe_config);
751 } else {
752 vlv_dsi_pll_disable(encoder);
753 vlv_dsi_pll_enable(encoder, pipe_config);
754 }
755
756 if (IS_BROXTON(dev_priv)) {
757 /* Add MIPI IO reset programming for modeset */
758 intel_de_rmw(display, BXT_P_CR_GT_DISP_PWRON, 0, MIPIO_RST_CTRL);
759
760 /* Power up DSI regulator */
761 intel_de_write(display, BXT_P_DSI_REGULATOR_CFG, STAP_SELECT);
762 intel_de_write(display, BXT_P_DSI_REGULATOR_TX_CTRL, 0);
763 }
764
765 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
766 /* Disable DPOunit clock gating, can stall pipe */
767 intel_de_rmw(display, DSPCLK_GATE_D(dev_priv),
768 0, DPOUNIT_CLOCK_GATE_DISABLE);
769 }
770
771 if (!IS_GEMINILAKE(dev_priv))
772 intel_dsi_prepare(encoder, pipe_config);
773
774 /* Give the panel time to power-on and then deassert its reset */
775 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_POWER_ON);
776 msleep(intel_dsi->panel_on_delay);
777 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DEASSERT_RESET);
778
779 if (IS_GEMINILAKE(dev_priv)) {
780 glk_cold_boot = glk_dsi_enable_io(encoder);
781
782 /* Prepare port in cold boot(s3/s4) scenario */
783 if (glk_cold_boot)
784 intel_dsi_prepare(encoder, pipe_config);
785 }
786
787 /* Put device in ready state (LP-11) */
788 intel_dsi_device_ready(encoder);
789
790 /* Prepare port in normal boot scenario */
791 if (IS_GEMINILAKE(dev_priv) && !glk_cold_boot)
792 intel_dsi_prepare(encoder, pipe_config);
793
794 /* Send initialization commands in LP mode */
795 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_INIT_OTP);
796
797 /*
798 * Enable port in pre-enable phase itself because as per hw team
799 * recommendation, port should be enabled before plane & pipe
800 */
801 if (is_cmd_mode(intel_dsi)) {
802 for_each_dsi_port(port, intel_dsi->ports)
803 intel_de_write(display,
804 MIPI_MAX_RETURN_PKT_SIZE(display, port), 8 * 4);
805 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_TEAR_ON);
806 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DISPLAY_ON);
807 } else {
808 msleep(20); /* XXX */
809 for_each_dsi_port(port, intel_dsi->ports)
810 dpi_send_cmd(intel_dsi, TURN_ON, false, port);
811 msleep(100);
812
813 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DISPLAY_ON);
814
815 intel_dsi_port_enable(encoder, pipe_config);
816 }
817
818 intel_backlight_enable(pipe_config, conn_state);
819 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_BACKLIGHT_ON);
820 }
821
bxt_dsi_enable(struct intel_atomic_state * state,struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state,const struct drm_connector_state * conn_state)822 static void bxt_dsi_enable(struct intel_atomic_state *state,
823 struct intel_encoder *encoder,
824 const struct intel_crtc_state *crtc_state,
825 const struct drm_connector_state *conn_state)
826 {
827 intel_crtc_vblank_on(crtc_state);
828 }
829
830 /*
831 * DSI port disable has to be done after pipe and plane disable, so we do it in
832 * the post_disable hook.
833 */
intel_dsi_disable(struct intel_atomic_state * state,struct intel_encoder * encoder,const struct intel_crtc_state * old_crtc_state,const struct drm_connector_state * old_conn_state)834 static void intel_dsi_disable(struct intel_atomic_state *state,
835 struct intel_encoder *encoder,
836 const struct intel_crtc_state *old_crtc_state,
837 const struct drm_connector_state *old_conn_state)
838 {
839 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
840 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
841 enum port port;
842
843 drm_dbg_kms(&i915->drm, "\n");
844
845 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_BACKLIGHT_OFF);
846 intel_backlight_disable(old_conn_state);
847
848 /*
849 * According to the spec we should send SHUTDOWN before
850 * MIPI_SEQ_DISPLAY_OFF only for v3+ VBTs, but field testing
851 * has shown that the v3 sequence works for v2 VBTs too
852 */
853 if (is_vid_mode(intel_dsi)) {
854 /* Send Shutdown command to the panel in LP mode */
855 for_each_dsi_port(port, intel_dsi->ports)
856 dpi_send_cmd(intel_dsi, SHUTDOWN, false, port);
857 msleep(10);
858 }
859 }
860
intel_dsi_clear_device_ready(struct intel_encoder * encoder)861 static void intel_dsi_clear_device_ready(struct intel_encoder *encoder)
862 {
863 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
864
865 if (IS_GEMINILAKE(dev_priv))
866 glk_dsi_clear_device_ready(encoder);
867 else
868 vlv_dsi_clear_device_ready(encoder);
869 }
870
intel_dsi_post_disable(struct intel_atomic_state * state,struct intel_encoder * encoder,const struct intel_crtc_state * old_crtc_state,const struct drm_connector_state * old_conn_state)871 static void intel_dsi_post_disable(struct intel_atomic_state *state,
872 struct intel_encoder *encoder,
873 const struct intel_crtc_state *old_crtc_state,
874 const struct drm_connector_state *old_conn_state)
875 {
876 struct intel_display *display = to_intel_display(encoder);
877 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
878 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
879 enum port port;
880
881 drm_dbg_kms(display->drm, "\n");
882
883 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
884 intel_crtc_vblank_off(old_crtc_state);
885
886 skl_scaler_disable(old_crtc_state);
887 }
888
889 if (is_vid_mode(intel_dsi)) {
890 for_each_dsi_port(port, intel_dsi->ports)
891 vlv_dsi_wait_for_fifo_empty(intel_dsi, port);
892
893 intel_dsi_port_disable(encoder);
894 usleep_range(2000, 5000);
895 }
896
897 intel_dsi_unprepare(encoder);
898
899 /*
900 * if disable packets are sent before sending shutdown packet then in
901 * some next enable sequence send turn on packet error is observed
902 */
903 if (is_cmd_mode(intel_dsi))
904 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_TEAR_OFF);
905 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DISPLAY_OFF);
906
907 /* Transition to LP-00 */
908 intel_dsi_clear_device_ready(encoder);
909
910 if (IS_BROXTON(dev_priv)) {
911 /* Power down DSI regulator to save power */
912 intel_de_write(display, BXT_P_DSI_REGULATOR_CFG, STAP_SELECT);
913 intel_de_write(display, BXT_P_DSI_REGULATOR_TX_CTRL,
914 HS_IO_CTRL_SELECT);
915
916 /* Add MIPI IO reset programming for modeset */
917 intel_de_rmw(display, BXT_P_CR_GT_DISP_PWRON, MIPIO_RST_CTRL, 0);
918 }
919
920 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
921 bxt_dsi_pll_disable(encoder);
922 } else {
923 vlv_dsi_pll_disable(encoder);
924
925 intel_de_rmw(display, DSPCLK_GATE_D(dev_priv),
926 DPOUNIT_CLOCK_GATE_DISABLE, 0);
927 }
928
929 /* Assert reset */
930 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_ASSERT_RESET);
931
932 msleep(intel_dsi->panel_off_delay);
933 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_POWER_OFF);
934
935 intel_dsi->panel_power_off_time = ktime_get_boottime();
936 }
937
intel_dsi_get_hw_state(struct intel_encoder * encoder,enum pipe * pipe)938 static bool intel_dsi_get_hw_state(struct intel_encoder *encoder,
939 enum pipe *pipe)
940 {
941 struct intel_display *display = to_intel_display(encoder);
942 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
943 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
944 intel_wakeref_t wakeref;
945 enum port port;
946 bool active = false;
947
948 drm_dbg_kms(display->drm, "\n");
949
950 wakeref = intel_display_power_get_if_enabled(dev_priv,
951 encoder->power_domain);
952 if (!wakeref)
953 return false;
954
955 /*
956 * On Broxton the PLL needs to be enabled with a valid divider
957 * configuration, otherwise accessing DSI registers will hang the
958 * machine. See BSpec North Display Engine registers/MIPI[BXT].
959 */
960 if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) &&
961 !bxt_dsi_pll_is_enabled(dev_priv))
962 goto out_put_power;
963
964 /* XXX: this only works for one DSI output */
965 for_each_dsi_port(port, intel_dsi->ports) {
966 i915_reg_t port_ctrl = port_ctrl_reg(dev_priv, port);
967 bool enabled = intel_de_read(display, port_ctrl) & DPI_ENABLE;
968
969 /*
970 * Due to some hardware limitations on VLV/CHV, the DPI enable
971 * bit in port C control register does not get set. As a
972 * workaround, check pipe B conf instead.
973 */
974 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
975 port == PORT_C)
976 enabled = intel_de_read(display,
977 TRANSCONF(dev_priv, PIPE_B)) & TRANSCONF_ENABLE;
978
979 /* Try command mode if video mode not enabled */
980 if (!enabled) {
981 u32 tmp = intel_de_read(display,
982 MIPI_DSI_FUNC_PRG(display, port));
983 enabled = tmp & CMD_MODE_DATA_WIDTH_MASK;
984 }
985
986 if (!enabled)
987 continue;
988
989 if (!(intel_de_read(display, MIPI_DEVICE_READY(display, port)) & DEVICE_READY))
990 continue;
991
992 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
993 u32 tmp = intel_de_read(display, MIPI_CTRL(display, port));
994 tmp &= BXT_PIPE_SELECT_MASK;
995 tmp >>= BXT_PIPE_SELECT_SHIFT;
996
997 if (drm_WARN_ON(display->drm, tmp > PIPE_C))
998 continue;
999
1000 *pipe = tmp;
1001 } else {
1002 *pipe = port == PORT_A ? PIPE_A : PIPE_B;
1003 }
1004
1005 active = true;
1006 break;
1007 }
1008
1009 out_put_power:
1010 intel_display_power_put(dev_priv, encoder->power_domain, wakeref);
1011
1012 return active;
1013 }
1014
bxt_dsi_get_pipe_config(struct intel_encoder * encoder,struct intel_crtc_state * pipe_config)1015 static void bxt_dsi_get_pipe_config(struct intel_encoder *encoder,
1016 struct intel_crtc_state *pipe_config)
1017 {
1018 struct intel_display *display = to_intel_display(encoder);
1019 struct drm_display_mode *adjusted_mode =
1020 &pipe_config->hw.adjusted_mode;
1021 struct drm_display_mode *adjusted_mode_sw;
1022 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
1023 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1024 unsigned int lane_count = intel_dsi->lane_count;
1025 unsigned int bpp, fmt;
1026 enum port port;
1027 u16 hactive, hfp, hsync, hbp, vfp, vsync;
1028 u16 hfp_sw, hsync_sw, hbp_sw;
1029 u16 crtc_htotal_sw, crtc_hsync_start_sw, crtc_hsync_end_sw,
1030 crtc_hblank_start_sw, crtc_hblank_end_sw;
1031
1032 /* FIXME: hw readout should not depend on SW state */
1033 adjusted_mode_sw = &crtc->config->hw.adjusted_mode;
1034
1035 /*
1036 * Atleast one port is active as encoder->get_config called only if
1037 * encoder->get_hw_state() returns true.
1038 */
1039 for_each_dsi_port(port, intel_dsi->ports) {
1040 if (intel_de_read(display, BXT_MIPI_PORT_CTRL(port)) & DPI_ENABLE)
1041 break;
1042 }
1043
1044 fmt = intel_de_read(display, MIPI_DSI_FUNC_PRG(display, port)) & VID_MODE_FORMAT_MASK;
1045 bpp = mipi_dsi_pixel_format_to_bpp(
1046 pixel_format_from_register_bits(fmt));
1047
1048 pipe_config->pipe_bpp = bdw_get_pipe_misc_bpp(crtc);
1049
1050 /* Enable Frame time stamo based scanline reporting */
1051 pipe_config->mode_flags |=
1052 I915_MODE_FLAG_GET_SCANLINE_FROM_TIMESTAMP;
1053
1054 /* In terms of pixels */
1055 adjusted_mode->crtc_hdisplay =
1056 intel_de_read(display,
1057 BXT_MIPI_TRANS_HACTIVE(port));
1058 adjusted_mode->crtc_vdisplay =
1059 intel_de_read(display,
1060 BXT_MIPI_TRANS_VACTIVE(port));
1061 adjusted_mode->crtc_vtotal =
1062 intel_de_read(display,
1063 BXT_MIPI_TRANS_VTOTAL(port));
1064
1065 hactive = adjusted_mode->crtc_hdisplay;
1066 hfp = intel_de_read(display, MIPI_HFP_COUNT(display, port));
1067
1068 /*
1069 * Meaningful for video mode non-burst sync pulse mode only,
1070 * can be zero for non-burst sync events and burst modes
1071 */
1072 hsync = intel_de_read(display, MIPI_HSYNC_PADDING_COUNT(display, port));
1073 hbp = intel_de_read(display, MIPI_HBP_COUNT(display, port));
1074
1075 /* horizontal values are in terms of high speed byte clock */
1076 hfp = pixels_from_txbyteclkhs(hfp, bpp, lane_count,
1077 intel_dsi->burst_mode_ratio);
1078 hsync = pixels_from_txbyteclkhs(hsync, bpp, lane_count,
1079 intel_dsi->burst_mode_ratio);
1080 hbp = pixels_from_txbyteclkhs(hbp, bpp, lane_count,
1081 intel_dsi->burst_mode_ratio);
1082
1083 if (intel_dsi->dual_link) {
1084 hfp *= 2;
1085 hsync *= 2;
1086 hbp *= 2;
1087 }
1088
1089 /* vertical values are in terms of lines */
1090 vfp = intel_de_read(display, MIPI_VFP_COUNT(display, port));
1091 vsync = intel_de_read(display, MIPI_VSYNC_PADDING_COUNT(display, port));
1092
1093 adjusted_mode->crtc_htotal = hactive + hfp + hsync + hbp;
1094 adjusted_mode->crtc_hsync_start = hfp + adjusted_mode->crtc_hdisplay;
1095 adjusted_mode->crtc_hsync_end = hsync + adjusted_mode->crtc_hsync_start;
1096 adjusted_mode->crtc_hblank_start = adjusted_mode->crtc_hdisplay;
1097 adjusted_mode->crtc_hblank_end = adjusted_mode->crtc_htotal;
1098
1099 adjusted_mode->crtc_vsync_start = vfp + adjusted_mode->crtc_vdisplay;
1100 adjusted_mode->crtc_vsync_end = vsync + adjusted_mode->crtc_vsync_start;
1101 adjusted_mode->crtc_vblank_start = adjusted_mode->crtc_vdisplay;
1102 adjusted_mode->crtc_vblank_end = adjusted_mode->crtc_vtotal;
1103
1104 /*
1105 * In BXT DSI there is no regs programmed with few horizontal timings
1106 * in Pixels but txbyteclkhs.. So retrieval process adds some
1107 * ROUND_UP ERRORS in the process of PIXELS<==>txbyteclkhs.
1108 * Actually here for the given adjusted_mode, we are calculating the
1109 * value programmed to the port and then back to the horizontal timing
1110 * param in pixels. This is the expected value, including roundup errors
1111 * And if that is same as retrieved value from port, then
1112 * (HW state) adjusted_mode's horizontal timings are corrected to
1113 * match with SW state to nullify the errors.
1114 */
1115 /* Calculating the value programmed to the Port register */
1116 hfp_sw = adjusted_mode_sw->crtc_hsync_start -
1117 adjusted_mode_sw->crtc_hdisplay;
1118 hsync_sw = adjusted_mode_sw->crtc_hsync_end -
1119 adjusted_mode_sw->crtc_hsync_start;
1120 hbp_sw = adjusted_mode_sw->crtc_htotal -
1121 adjusted_mode_sw->crtc_hsync_end;
1122
1123 if (intel_dsi->dual_link) {
1124 hfp_sw /= 2;
1125 hsync_sw /= 2;
1126 hbp_sw /= 2;
1127 }
1128
1129 hfp_sw = txbyteclkhs(hfp_sw, bpp, lane_count,
1130 intel_dsi->burst_mode_ratio);
1131 hsync_sw = txbyteclkhs(hsync_sw, bpp, lane_count,
1132 intel_dsi->burst_mode_ratio);
1133 hbp_sw = txbyteclkhs(hbp_sw, bpp, lane_count,
1134 intel_dsi->burst_mode_ratio);
1135
1136 /* Reverse calculating the adjusted mode parameters from port reg vals*/
1137 hfp_sw = pixels_from_txbyteclkhs(hfp_sw, bpp, lane_count,
1138 intel_dsi->burst_mode_ratio);
1139 hsync_sw = pixels_from_txbyteclkhs(hsync_sw, bpp, lane_count,
1140 intel_dsi->burst_mode_ratio);
1141 hbp_sw = pixels_from_txbyteclkhs(hbp_sw, bpp, lane_count,
1142 intel_dsi->burst_mode_ratio);
1143
1144 if (intel_dsi->dual_link) {
1145 hfp_sw *= 2;
1146 hsync_sw *= 2;
1147 hbp_sw *= 2;
1148 }
1149
1150 crtc_htotal_sw = adjusted_mode_sw->crtc_hdisplay + hfp_sw +
1151 hsync_sw + hbp_sw;
1152 crtc_hsync_start_sw = hfp_sw + adjusted_mode_sw->crtc_hdisplay;
1153 crtc_hsync_end_sw = hsync_sw + crtc_hsync_start_sw;
1154 crtc_hblank_start_sw = adjusted_mode_sw->crtc_hdisplay;
1155 crtc_hblank_end_sw = crtc_htotal_sw;
1156
1157 if (adjusted_mode->crtc_htotal == crtc_htotal_sw)
1158 adjusted_mode->crtc_htotal = adjusted_mode_sw->crtc_htotal;
1159
1160 if (adjusted_mode->crtc_hsync_start == crtc_hsync_start_sw)
1161 adjusted_mode->crtc_hsync_start =
1162 adjusted_mode_sw->crtc_hsync_start;
1163
1164 if (adjusted_mode->crtc_hsync_end == crtc_hsync_end_sw)
1165 adjusted_mode->crtc_hsync_end =
1166 adjusted_mode_sw->crtc_hsync_end;
1167
1168 if (adjusted_mode->crtc_hblank_start == crtc_hblank_start_sw)
1169 adjusted_mode->crtc_hblank_start =
1170 adjusted_mode_sw->crtc_hblank_start;
1171
1172 if (adjusted_mode->crtc_hblank_end == crtc_hblank_end_sw)
1173 adjusted_mode->crtc_hblank_end =
1174 adjusted_mode_sw->crtc_hblank_end;
1175 }
1176
intel_dsi_get_config(struct intel_encoder * encoder,struct intel_crtc_state * pipe_config)1177 static void intel_dsi_get_config(struct intel_encoder *encoder,
1178 struct intel_crtc_state *pipe_config)
1179 {
1180 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1181 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1182 u32 pclk;
1183
1184 drm_dbg_kms(&dev_priv->drm, "\n");
1185
1186 pipe_config->output_types |= BIT(INTEL_OUTPUT_DSI);
1187
1188 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
1189 bxt_dsi_get_pipe_config(encoder, pipe_config);
1190 pclk = bxt_dsi_get_pclk(encoder, pipe_config);
1191 } else {
1192 pclk = vlv_dsi_get_pclk(encoder, pipe_config);
1193 }
1194
1195 pipe_config->port_clock = pclk;
1196
1197 /* FIXME definitely not right for burst/cmd mode/pixel overlap */
1198 pipe_config->hw.adjusted_mode.crtc_clock = pclk;
1199 if (intel_dsi->dual_link)
1200 pipe_config->hw.adjusted_mode.crtc_clock *= 2;
1201 }
1202
1203 /* return txclkesc cycles in terms of divider and duration in us */
txclkesc(u32 divider,unsigned int us)1204 static u16 txclkesc(u32 divider, unsigned int us)
1205 {
1206 switch (divider) {
1207 case ESCAPE_CLOCK_DIVIDER_1:
1208 default:
1209 return 20 * us;
1210 case ESCAPE_CLOCK_DIVIDER_2:
1211 return 10 * us;
1212 case ESCAPE_CLOCK_DIVIDER_4:
1213 return 5 * us;
1214 }
1215 }
1216
set_dsi_timings(struct intel_encoder * encoder,const struct drm_display_mode * adjusted_mode)1217 static void set_dsi_timings(struct intel_encoder *encoder,
1218 const struct drm_display_mode *adjusted_mode)
1219 {
1220 struct intel_display *display = to_intel_display(encoder);
1221 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1222 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1223 enum port port;
1224 unsigned int bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
1225 unsigned int lane_count = intel_dsi->lane_count;
1226
1227 u16 hactive, hfp, hsync, hbp, vfp, vsync, vbp;
1228
1229 hactive = adjusted_mode->crtc_hdisplay;
1230 hfp = adjusted_mode->crtc_hsync_start - adjusted_mode->crtc_hdisplay;
1231 hsync = adjusted_mode->crtc_hsync_end - adjusted_mode->crtc_hsync_start;
1232 hbp = adjusted_mode->crtc_htotal - adjusted_mode->crtc_hsync_end;
1233
1234 if (intel_dsi->dual_link) {
1235 hactive /= 2;
1236 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK)
1237 hactive += intel_dsi->pixel_overlap;
1238 hfp /= 2;
1239 hsync /= 2;
1240 hbp /= 2;
1241 }
1242
1243 vfp = adjusted_mode->crtc_vsync_start - adjusted_mode->crtc_vdisplay;
1244 vsync = adjusted_mode->crtc_vsync_end - adjusted_mode->crtc_vsync_start;
1245 vbp = adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vsync_end;
1246
1247 /* horizontal values are in terms of high speed byte clock */
1248 hactive = txbyteclkhs(hactive, bpp, lane_count,
1249 intel_dsi->burst_mode_ratio);
1250 hfp = txbyteclkhs(hfp, bpp, lane_count, intel_dsi->burst_mode_ratio);
1251 hsync = txbyteclkhs(hsync, bpp, lane_count,
1252 intel_dsi->burst_mode_ratio);
1253 hbp = txbyteclkhs(hbp, bpp, lane_count, intel_dsi->burst_mode_ratio);
1254
1255 for_each_dsi_port(port, intel_dsi->ports) {
1256 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
1257 /*
1258 * Program hdisplay and vdisplay on MIPI transcoder.
1259 * This is different from calculated hactive and
1260 * vactive, as they are calculated per channel basis,
1261 * whereas these values should be based on resolution.
1262 */
1263 intel_de_write(display, BXT_MIPI_TRANS_HACTIVE(port),
1264 adjusted_mode->crtc_hdisplay);
1265 intel_de_write(display, BXT_MIPI_TRANS_VACTIVE(port),
1266 adjusted_mode->crtc_vdisplay);
1267 intel_de_write(display, BXT_MIPI_TRANS_VTOTAL(port),
1268 adjusted_mode->crtc_vtotal);
1269 }
1270
1271 intel_de_write(display, MIPI_HACTIVE_AREA_COUNT(display, port),
1272 hactive);
1273 intel_de_write(display, MIPI_HFP_COUNT(display, port), hfp);
1274
1275 /* meaningful for video mode non-burst sync pulse mode only,
1276 * can be zero for non-burst sync events and burst modes */
1277 intel_de_write(display, MIPI_HSYNC_PADDING_COUNT(display, port),
1278 hsync);
1279 intel_de_write(display, MIPI_HBP_COUNT(display, port), hbp);
1280
1281 /* vertical values are in terms of lines */
1282 intel_de_write(display, MIPI_VFP_COUNT(display, port), vfp);
1283 intel_de_write(display, MIPI_VSYNC_PADDING_COUNT(display, port),
1284 vsync);
1285 intel_de_write(display, MIPI_VBP_COUNT(display, port), vbp);
1286 }
1287 }
1288
pixel_format_to_reg(enum mipi_dsi_pixel_format fmt)1289 static u32 pixel_format_to_reg(enum mipi_dsi_pixel_format fmt)
1290 {
1291 switch (fmt) {
1292 case MIPI_DSI_FMT_RGB888:
1293 return VID_MODE_FORMAT_RGB888;
1294 case MIPI_DSI_FMT_RGB666:
1295 return VID_MODE_FORMAT_RGB666;
1296 case MIPI_DSI_FMT_RGB666_PACKED:
1297 return VID_MODE_FORMAT_RGB666_PACKED;
1298 case MIPI_DSI_FMT_RGB565:
1299 return VID_MODE_FORMAT_RGB565;
1300 default:
1301 MISSING_CASE(fmt);
1302 return VID_MODE_FORMAT_RGB666;
1303 }
1304 }
1305
intel_dsi_prepare(struct intel_encoder * encoder,const struct intel_crtc_state * pipe_config)1306 static void intel_dsi_prepare(struct intel_encoder *encoder,
1307 const struct intel_crtc_state *pipe_config)
1308 {
1309 struct intel_display *display = to_intel_display(encoder);
1310 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1311 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
1312 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1313 const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
1314 enum port port;
1315 unsigned int bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
1316 u32 val, tmp;
1317 u16 mode_hdisplay;
1318
1319 drm_dbg_kms(display->drm, "pipe %c\n", pipe_name(crtc->pipe));
1320
1321 mode_hdisplay = adjusted_mode->crtc_hdisplay;
1322
1323 if (intel_dsi->dual_link) {
1324 mode_hdisplay /= 2;
1325 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK)
1326 mode_hdisplay += intel_dsi->pixel_overlap;
1327 }
1328
1329 for_each_dsi_port(port, intel_dsi->ports) {
1330 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1331 /*
1332 * escape clock divider, 20MHz, shared for A and C.
1333 * device ready must be off when doing this! txclkesc?
1334 */
1335 tmp = intel_de_read(display, MIPI_CTRL(display, PORT_A));
1336 tmp &= ~ESCAPE_CLOCK_DIVIDER_MASK;
1337 intel_de_write(display, MIPI_CTRL(display, PORT_A),
1338 tmp | ESCAPE_CLOCK_DIVIDER_1);
1339
1340 /* read request priority is per pipe */
1341 tmp = intel_de_read(display, MIPI_CTRL(display, port));
1342 tmp &= ~READ_REQUEST_PRIORITY_MASK;
1343 intel_de_write(display, MIPI_CTRL(display, port),
1344 tmp | READ_REQUEST_PRIORITY_HIGH);
1345 } else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
1346 enum pipe pipe = crtc->pipe;
1347
1348 intel_de_rmw(display, MIPI_CTRL(display, port),
1349 BXT_PIPE_SELECT_MASK, BXT_PIPE_SELECT(pipe));
1350 }
1351
1352 /* XXX: why here, why like this? handling in irq handler?! */
1353 intel_de_write(display, MIPI_INTR_STAT(display, port), 0xffffffff);
1354 intel_de_write(display, MIPI_INTR_EN(display, port), 0xffffffff);
1355
1356 intel_de_write(display, MIPI_DPHY_PARAM(display, port),
1357 intel_dsi->dphy_reg);
1358
1359 intel_de_write(display, MIPI_DPI_RESOLUTION(display, port),
1360 adjusted_mode->crtc_vdisplay << VERTICAL_ADDRESS_SHIFT | mode_hdisplay << HORIZONTAL_ADDRESS_SHIFT);
1361 }
1362
1363 set_dsi_timings(encoder, adjusted_mode);
1364
1365 val = intel_dsi->lane_count << DATA_LANES_PRG_REG_SHIFT;
1366 if (is_cmd_mode(intel_dsi)) {
1367 val |= intel_dsi->channel << CMD_MODE_CHANNEL_NUMBER_SHIFT;
1368 val |= CMD_MODE_DATA_WIDTH_8_BIT; /* XXX */
1369 } else {
1370 val |= intel_dsi->channel << VID_MODE_CHANNEL_NUMBER_SHIFT;
1371 val |= pixel_format_to_reg(intel_dsi->pixel_format);
1372 }
1373
1374 tmp = 0;
1375 if (intel_dsi->eotp_pkt == 0)
1376 tmp |= EOT_DISABLE;
1377 if (intel_dsi->clock_stop)
1378 tmp |= CLOCKSTOP;
1379
1380 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
1381 tmp |= BXT_DPHY_DEFEATURE_EN;
1382 if (!is_cmd_mode(intel_dsi))
1383 tmp |= BXT_DEFEATURE_DPI_FIFO_CTR;
1384 }
1385
1386 for_each_dsi_port(port, intel_dsi->ports) {
1387 intel_de_write(display, MIPI_DSI_FUNC_PRG(display, port), val);
1388
1389 /* timeouts for recovery. one frame IIUC. if counter expires,
1390 * EOT and stop state. */
1391
1392 /*
1393 * In burst mode, value greater than one DPI line Time in byte
1394 * clock (txbyteclkhs) To timeout this timer 1+ of the above
1395 * said value is recommended.
1396 *
1397 * In non-burst mode, Value greater than one DPI frame time in
1398 * byte clock(txbyteclkhs) To timeout this timer 1+ of the above
1399 * said value is recommended.
1400 *
1401 * In DBI only mode, value greater than one DBI frame time in
1402 * byte clock(txbyteclkhs) To timeout this timer 1+ of the above
1403 * said value is recommended.
1404 */
1405
1406 if (is_vid_mode(intel_dsi) &&
1407 intel_dsi->video_mode == BURST_MODE) {
1408 intel_de_write(display, MIPI_HS_TX_TIMEOUT(display, port),
1409 txbyteclkhs(adjusted_mode->crtc_htotal, bpp, intel_dsi->lane_count, intel_dsi->burst_mode_ratio) + 1);
1410 } else {
1411 intel_de_write(display, MIPI_HS_TX_TIMEOUT(display, port),
1412 txbyteclkhs(adjusted_mode->crtc_vtotal * adjusted_mode->crtc_htotal, bpp, intel_dsi->lane_count, intel_dsi->burst_mode_ratio) + 1);
1413 }
1414 intel_de_write(display, MIPI_LP_RX_TIMEOUT(display, port),
1415 intel_dsi->lp_rx_timeout);
1416 intel_de_write(display, MIPI_TURN_AROUND_TIMEOUT(display, port),
1417 intel_dsi->turn_arnd_val);
1418 intel_de_write(display, MIPI_DEVICE_RESET_TIMER(display, port),
1419 intel_dsi->rst_timer_val);
1420
1421 /* dphy stuff */
1422
1423 /* in terms of low power clock */
1424 intel_de_write(display, MIPI_INIT_COUNT(display, port),
1425 txclkesc(intel_dsi->escape_clk_div, 100));
1426
1427 if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) &&
1428 !intel_dsi->dual_link) {
1429 /*
1430 * BXT spec says write MIPI_INIT_COUNT for
1431 * both the ports, even if only one is
1432 * getting used. So write the other port
1433 * if not in dual link mode.
1434 */
1435 intel_de_write(display,
1436 MIPI_INIT_COUNT(display, port == PORT_A ? PORT_C : PORT_A),
1437 intel_dsi->init_count);
1438 }
1439
1440 /* recovery disables */
1441 intel_de_write(display, MIPI_EOT_DISABLE(display, port), tmp);
1442
1443 /* in terms of low power clock */
1444 intel_de_write(display, MIPI_INIT_COUNT(display, port),
1445 intel_dsi->init_count);
1446
1447 /* in terms of txbyteclkhs. actual high to low switch +
1448 * MIPI_STOP_STATE_STALL * MIPI_LP_BYTECLK.
1449 *
1450 * XXX: write MIPI_STOP_STATE_STALL?
1451 */
1452 intel_de_write(display, MIPI_HIGH_LOW_SWITCH_COUNT(display, port),
1453 intel_dsi->hs_to_lp_count);
1454
1455 /* XXX: low power clock equivalence in terms of byte clock.
1456 * the number of byte clocks occupied in one low power clock.
1457 * based on txbyteclkhs and txclkesc.
1458 * txclkesc time / txbyteclk time * (105 + MIPI_STOP_STATE_STALL
1459 * ) / 105.???
1460 */
1461 intel_de_write(display, MIPI_LP_BYTECLK(display, port),
1462 intel_dsi->lp_byte_clk);
1463
1464 if (IS_GEMINILAKE(dev_priv)) {
1465 intel_de_write(display, MIPI_TLPX_TIME_COUNT(display, port),
1466 intel_dsi->lp_byte_clk);
1467 /* Shadow of DPHY reg */
1468 intel_de_write(display, MIPI_CLK_LANE_TIMING(display, port),
1469 intel_dsi->dphy_reg);
1470 }
1471
1472 /* the bw essential for transmitting 16 long packets containing
1473 * 252 bytes meant for dcs write memory command is programmed in
1474 * this register in terms of byte clocks. based on dsi transfer
1475 * rate and the number of lanes configured the time taken to
1476 * transmit 16 long packets in a dsi stream varies. */
1477 intel_de_write(display, MIPI_DBI_BW_CTRL(display, port),
1478 intel_dsi->bw_timer);
1479
1480 intel_de_write(display, MIPI_CLK_LANE_SWITCH_TIME_CNT(display, port),
1481 intel_dsi->clk_lp_to_hs_count << LP_HS_SSW_CNT_SHIFT | intel_dsi->clk_hs_to_lp_count << HS_LP_PWR_SW_CNT_SHIFT);
1482
1483 if (is_vid_mode(intel_dsi)) {
1484 u32 fmt = intel_dsi->video_frmt_cfg_bits | IP_TG_CONFIG;
1485
1486 /*
1487 * Some panels might have resolution which is not a
1488 * multiple of 64 like 1366 x 768. Enable RANDOM
1489 * resolution support for such panels by default.
1490 */
1491 fmt |= RANDOM_DPI_DISPLAY_RESOLUTION;
1492
1493 switch (intel_dsi->video_mode) {
1494 default:
1495 MISSING_CASE(intel_dsi->video_mode);
1496 fallthrough;
1497 case NON_BURST_SYNC_EVENTS:
1498 fmt |= VIDEO_MODE_NON_BURST_WITH_SYNC_EVENTS;
1499 break;
1500 case NON_BURST_SYNC_PULSE:
1501 fmt |= VIDEO_MODE_NON_BURST_WITH_SYNC_PULSE;
1502 break;
1503 case BURST_MODE:
1504 fmt |= VIDEO_MODE_BURST;
1505 break;
1506 }
1507
1508 intel_de_write(display, MIPI_VIDEO_MODE_FORMAT(display, port), fmt);
1509 }
1510 }
1511 }
1512
intel_dsi_unprepare(struct intel_encoder * encoder)1513 static void intel_dsi_unprepare(struct intel_encoder *encoder)
1514 {
1515 struct intel_display *display = to_intel_display(encoder);
1516 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1517 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1518 enum port port;
1519
1520 if (IS_GEMINILAKE(dev_priv))
1521 return;
1522
1523 for_each_dsi_port(port, intel_dsi->ports) {
1524 /* Panel commands can be sent when clock is in LP11 */
1525 intel_de_write(display, MIPI_DEVICE_READY(display, port), 0x0);
1526
1527 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
1528 bxt_dsi_reset_clocks(encoder, port);
1529 else
1530 vlv_dsi_reset_clocks(encoder, port);
1531 intel_de_write(display, MIPI_EOT_DISABLE(display, port), CLOCKSTOP);
1532
1533 intel_de_rmw(display, MIPI_DSI_FUNC_PRG(display, port), VID_MODE_FORMAT_MASK, 0);
1534
1535 intel_de_write(display, MIPI_DEVICE_READY(display, port), 0x1);
1536 }
1537 }
1538
1539 static const struct drm_encoder_funcs intel_dsi_funcs = {
1540 .destroy = intel_encoder_destroy,
1541 };
1542
vlv_dsi_mode_valid(struct drm_connector * connector,struct drm_display_mode * mode)1543 static enum drm_mode_status vlv_dsi_mode_valid(struct drm_connector *connector,
1544 struct drm_display_mode *mode)
1545 {
1546 struct drm_i915_private *i915 = to_i915(connector->dev);
1547
1548 if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) {
1549 enum drm_mode_status status;
1550
1551 status = intel_cpu_transcoder_mode_valid(i915, mode);
1552 if (status != MODE_OK)
1553 return status;
1554 }
1555
1556 return intel_dsi_mode_valid(connector, mode);
1557 }
1558
1559 static const struct drm_connector_helper_funcs intel_dsi_connector_helper_funcs = {
1560 .get_modes = intel_dsi_get_modes,
1561 .mode_valid = vlv_dsi_mode_valid,
1562 .atomic_check = intel_digital_connector_atomic_check,
1563 };
1564
1565 static const struct drm_connector_funcs intel_dsi_connector_funcs = {
1566 .detect = intel_panel_detect,
1567 .late_register = intel_connector_register,
1568 .early_unregister = intel_connector_unregister,
1569 .destroy = intel_connector_destroy,
1570 .fill_modes = drm_helper_probe_single_connector_modes,
1571 .atomic_get_property = intel_digital_connector_atomic_get_property,
1572 .atomic_set_property = intel_digital_connector_atomic_set_property,
1573 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1574 .atomic_duplicate_state = intel_digital_connector_duplicate_state,
1575 };
1576
vlv_dsi_add_properties(struct intel_connector * connector)1577 static void vlv_dsi_add_properties(struct intel_connector *connector)
1578 {
1579 const struct drm_display_mode *fixed_mode =
1580 intel_panel_preferred_fixed_mode(connector);
1581
1582 intel_attach_scaling_mode_property(&connector->base);
1583
1584 drm_connector_set_panel_orientation_with_quirk(&connector->base,
1585 intel_dsi_get_panel_orientation(connector),
1586 fixed_mode->hdisplay,
1587 fixed_mode->vdisplay);
1588 }
1589
1590 #define NS_KHZ_RATIO 1000000
1591
1592 #define PREPARE_CNT_MAX 0x3F
1593 #define EXIT_ZERO_CNT_MAX 0x3F
1594 #define CLK_ZERO_CNT_MAX 0xFF
1595 #define TRAIL_CNT_MAX 0x1F
1596
vlv_dphy_param_init(struct intel_dsi * intel_dsi)1597 static void vlv_dphy_param_init(struct intel_dsi *intel_dsi)
1598 {
1599 struct drm_i915_private *dev_priv = to_i915(intel_dsi->base.base.dev);
1600 struct intel_connector *connector = intel_dsi->attached_connector;
1601 struct mipi_config *mipi_config = connector->panel.vbt.dsi.config;
1602 u32 tlpx_ns, extra_byte_count, tlpx_ui;
1603 u32 ui_num, ui_den;
1604 u32 prepare_cnt, exit_zero_cnt, clk_zero_cnt, trail_cnt;
1605 u32 ths_prepare_ns, tclk_trail_ns;
1606 u32 tclk_prepare_clkzero, ths_prepare_hszero;
1607 u32 lp_to_hs_switch, hs_to_lp_switch;
1608 u32 mul;
1609
1610 tlpx_ns = intel_dsi_tlpx_ns(intel_dsi);
1611
1612 switch (intel_dsi->lane_count) {
1613 case 1:
1614 case 2:
1615 extra_byte_count = 2;
1616 break;
1617 case 3:
1618 extra_byte_count = 4;
1619 break;
1620 case 4:
1621 default:
1622 extra_byte_count = 3;
1623 break;
1624 }
1625
1626 /* in Kbps */
1627 ui_num = NS_KHZ_RATIO;
1628 ui_den = intel_dsi_bitrate(intel_dsi);
1629
1630 tclk_prepare_clkzero = mipi_config->tclk_prepare_clkzero;
1631 ths_prepare_hszero = mipi_config->ths_prepare_hszero;
1632
1633 /*
1634 * B060
1635 * LP byte clock = TLPX/ (8UI)
1636 */
1637 intel_dsi->lp_byte_clk = DIV_ROUND_UP(tlpx_ns * ui_den, 8 * ui_num);
1638
1639 /* DDR clock period = 2 * UI
1640 * UI(sec) = 1/(bitrate * 10^3) (bitrate is in KHZ)
1641 * UI(nsec) = 10^6 / bitrate
1642 * DDR clock period (nsec) = 2 * UI = (2 * 10^6)/ bitrate
1643 * DDR clock count = ns_value / DDR clock period
1644 *
1645 * For GEMINILAKE dphy_param_reg will be programmed in terms of
1646 * HS byte clock count for other platform in HS ddr clock count
1647 */
1648 mul = IS_GEMINILAKE(dev_priv) ? 8 : 2;
1649 ths_prepare_ns = max(mipi_config->ths_prepare,
1650 mipi_config->tclk_prepare);
1651
1652 /* prepare count */
1653 prepare_cnt = DIV_ROUND_UP(ths_prepare_ns * ui_den, ui_num * mul);
1654
1655 if (prepare_cnt > PREPARE_CNT_MAX) {
1656 drm_dbg_kms(&dev_priv->drm, "prepare count too high %u\n",
1657 prepare_cnt);
1658 prepare_cnt = PREPARE_CNT_MAX;
1659 }
1660
1661 /* exit zero count */
1662 exit_zero_cnt = DIV_ROUND_UP(
1663 (ths_prepare_hszero - ths_prepare_ns) * ui_den,
1664 ui_num * mul
1665 );
1666
1667 /*
1668 * Exit zero is unified val ths_zero and ths_exit
1669 * minimum value for ths_exit = 110ns
1670 * min (exit_zero_cnt * 2) = 110/UI
1671 * exit_zero_cnt = 55/UI
1672 */
1673 if (exit_zero_cnt < (55 * ui_den / ui_num) && (55 * ui_den) % ui_num)
1674 exit_zero_cnt += 1;
1675
1676 if (exit_zero_cnt > EXIT_ZERO_CNT_MAX) {
1677 drm_dbg_kms(&dev_priv->drm, "exit zero count too high %u\n",
1678 exit_zero_cnt);
1679 exit_zero_cnt = EXIT_ZERO_CNT_MAX;
1680 }
1681
1682 /* clk zero count */
1683 clk_zero_cnt = DIV_ROUND_UP(
1684 (tclk_prepare_clkzero - ths_prepare_ns)
1685 * ui_den, ui_num * mul);
1686
1687 if (clk_zero_cnt > CLK_ZERO_CNT_MAX) {
1688 drm_dbg_kms(&dev_priv->drm, "clock zero count too high %u\n",
1689 clk_zero_cnt);
1690 clk_zero_cnt = CLK_ZERO_CNT_MAX;
1691 }
1692
1693 /* trail count */
1694 tclk_trail_ns = max(mipi_config->tclk_trail, mipi_config->ths_trail);
1695 trail_cnt = DIV_ROUND_UP(tclk_trail_ns * ui_den, ui_num * mul);
1696
1697 if (trail_cnt > TRAIL_CNT_MAX) {
1698 drm_dbg_kms(&dev_priv->drm, "trail count too high %u\n",
1699 trail_cnt);
1700 trail_cnt = TRAIL_CNT_MAX;
1701 }
1702
1703 /* B080 */
1704 intel_dsi->dphy_reg = exit_zero_cnt << 24 | trail_cnt << 16 |
1705 clk_zero_cnt << 8 | prepare_cnt;
1706
1707 /*
1708 * LP to HS switch count = 4TLPX + PREP_COUNT * mul + EXIT_ZERO_COUNT *
1709 * mul + 10UI + Extra Byte Count
1710 *
1711 * HS to LP switch count = THS-TRAIL + 2TLPX + Extra Byte Count
1712 * Extra Byte Count is calculated according to number of lanes.
1713 * High Low Switch Count is the Max of LP to HS and
1714 * HS to LP switch count
1715 *
1716 */
1717 tlpx_ui = DIV_ROUND_UP(tlpx_ns * ui_den, ui_num);
1718
1719 /* B044 */
1720 /* FIXME:
1721 * The comment above does not match with the code */
1722 lp_to_hs_switch = DIV_ROUND_UP(4 * tlpx_ui + prepare_cnt * mul +
1723 exit_zero_cnt * mul + 10, 8);
1724
1725 hs_to_lp_switch = DIV_ROUND_UP(mipi_config->ths_trail + 2 * tlpx_ui, 8);
1726
1727 intel_dsi->hs_to_lp_count = max(lp_to_hs_switch, hs_to_lp_switch);
1728 intel_dsi->hs_to_lp_count += extra_byte_count;
1729
1730 /* B088 */
1731 /* LP -> HS for clock lanes
1732 * LP clk sync + LP11 + LP01 + tclk_prepare + tclk_zero +
1733 * extra byte count
1734 * 2TPLX + 1TLPX + 1 TPLX(in ns) + prepare_cnt * 2 + clk_zero_cnt *
1735 * 2(in UI) + extra byte count
1736 * In byteclks = (4TLPX + prepare_cnt * 2 + clk_zero_cnt *2 (in UI)) /
1737 * 8 + extra byte count
1738 */
1739 intel_dsi->clk_lp_to_hs_count =
1740 DIV_ROUND_UP(
1741 4 * tlpx_ui + prepare_cnt * 2 +
1742 clk_zero_cnt * 2,
1743 8);
1744
1745 intel_dsi->clk_lp_to_hs_count += extra_byte_count;
1746
1747 /* HS->LP for Clock Lanes
1748 * Low Power clock synchronisations + 1Tx byteclk + tclk_trail +
1749 * Extra byte count
1750 * 2TLPX + 8UI + (trail_count*2)(in UI) + Extra byte count
1751 * In byteclks = (2*TLpx(in UI) + trail_count*2 +8)(in UI)/8 +
1752 * Extra byte count
1753 */
1754 intel_dsi->clk_hs_to_lp_count =
1755 DIV_ROUND_UP(2 * tlpx_ui + trail_cnt * 2 + 8,
1756 8);
1757 intel_dsi->clk_hs_to_lp_count += extra_byte_count;
1758
1759 intel_dsi_log_params(intel_dsi);
1760 }
1761
vlv_dsi_min_cdclk(const struct intel_crtc_state * crtc_state)1762 int vlv_dsi_min_cdclk(const struct intel_crtc_state *crtc_state)
1763 {
1764 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
1765
1766 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI))
1767 return 0;
1768
1769 /*
1770 * On Valleyview some DSI panels lose (v|h)sync when the clock is lower
1771 * than 320000KHz.
1772 */
1773 if (IS_VALLEYVIEW(dev_priv))
1774 return 320000;
1775
1776 /*
1777 * On Geminilake once the CDCLK gets as low as 79200
1778 * picture gets unstable, despite that values are
1779 * correct for DSI PLL and DE PLL.
1780 */
1781 if (IS_GEMINILAKE(dev_priv))
1782 return 158400;
1783
1784 return 0;
1785 }
1786
1787 typedef void (*vlv_dsi_dmi_quirk_func)(struct intel_dsi *intel_dsi);
1788
1789 /*
1790 * Vtotal is wrong on the Asus TF103C leading to the last line of the display
1791 * being shown as the first line. The factory installed Android has a hardcoded
1792 * modeline, causing it to not suffer from this BIOS bug.
1793 *
1794 * Original mode: "1280x800": 60 67700 1280 1312 1328 1376 800 808 812 820 0x8 0xa
1795 * Fixed mode: "1280x800": 60 67700 1280 1312 1328 1376 800 808 812 816 0x8 0xa
1796 *
1797 * https://gitlab.freedesktop.org/drm/intel/-/issues/9381
1798 */
vlv_dsi_asus_tf103c_mode_fixup(struct intel_dsi * intel_dsi)1799 static void vlv_dsi_asus_tf103c_mode_fixup(struct intel_dsi *intel_dsi)
1800 {
1801 /* Cast away the const as we want to fixup the mode */
1802 struct drm_display_mode *fixed_mode = (struct drm_display_mode *)
1803 intel_panel_preferred_fixed_mode(intel_dsi->attached_connector);
1804
1805 if (fixed_mode->vtotal == 820)
1806 fixed_mode->vtotal -= 4;
1807 }
1808
1809 /*
1810 * On the Lenovo Yoga Tablet 2 830 / 1050 there are 2 problems:
1811 * 1. The I2C MIPI sequence elements reference bus 3. ACPI has I2C1 - I2C7
1812 * which under Linux become bus 0 - 6. And the MIPI sequence reference
1813 * to bus 3 is indented for I2C3 which is bus 2 under Linux.
1814 *
1815 * Note mipi_exec_i2c() cannot just subtract 1 from the bus
1816 * given in the I2C MIPI sequence element. Since on other
1817 * devices the I2C bus-numbers used in the MIPI sequences do
1818 * actually start at 0.
1819 *
1820 * 2. width_/height_mm contain a bogus 192mm x 120mm size. This is
1821 * especially a problem on the 8" 830 version which uses a 10:16
1822 * portrait screen where as the bogus size is 16:10.
1823 *
1824 * https://gitlab.freedesktop.org/drm/intel/-/issues/9379
1825 */
vlv_dsi_lenovo_yoga_tab2_size_fixup(struct intel_dsi * intel_dsi)1826 static void vlv_dsi_lenovo_yoga_tab2_size_fixup(struct intel_dsi *intel_dsi)
1827 {
1828 const struct drm_display_mode *fixed_mode =
1829 intel_panel_preferred_fixed_mode(intel_dsi->attached_connector);
1830 struct drm_display_info *info = &intel_dsi->attached_connector->base.display_info;
1831
1832 intel_dsi->i2c_bus_num = 2;
1833
1834 /*
1835 * The 10" 1050 uses a 1920x1200 landscape screen, where as the 8" 830
1836 * uses a 1200x1920 portrait screen.
1837 */
1838 if (fixed_mode->hdisplay == 1920) {
1839 info->width_mm = 216;
1840 info->height_mm = 135;
1841 } else {
1842 info->width_mm = 107;
1843 info->height_mm = 171;
1844 }
1845 }
1846
1847 /*
1848 * On the Lenovo Yoga Tab 3 Pro YT3-X90F there are 2 problems:
1849 * 1. i2c_acpi_find_adapter() picks the wrong adapter causing mipi_exec_i2c()
1850 * to not work. Fix this by setting i2c_bus_num.
1851 * 2. There is no backlight off MIPI sequence, causing the backlight to stay on.
1852 * Add a backlight off sequence mirroring the existing backlight on sequence.
1853 *
1854 * https://gitlab.freedesktop.org/drm/intel/-/issues/9380
1855 */
vlv_dsi_lenovo_yoga_tab3_backlight_fixup(struct intel_dsi * intel_dsi)1856 static void vlv_dsi_lenovo_yoga_tab3_backlight_fixup(struct intel_dsi *intel_dsi)
1857 {
1858 static const u8 backlight_off_sequence[16] = {
1859 /* Header Seq-id 7, length after header 11 bytes */
1860 0x07, 0x0b, 0x00, 0x00, 0x00,
1861 /* MIPI_SEQ_ELEM_I2C bus 0 addr 0x2c reg 0x00 data-len 1 data 0x00 */
1862 0x04, 0x08, 0x00, 0x00, 0x00, 0x2c, 0x00, 0x00, 0x01, 0x00,
1863 /* MIPI_SEQ_ELEM_END */
1864 0x00
1865 };
1866 struct intel_connector *connector = intel_dsi->attached_connector;
1867
1868 intel_dsi->i2c_bus_num = 0;
1869 connector->panel.vbt.dsi.sequence[MIPI_SEQ_BACKLIGHT_OFF] = backlight_off_sequence;
1870 }
1871
1872 static const struct dmi_system_id vlv_dsi_dmi_quirk_table[] = {
1873 {
1874 /* Asus Transformer Pad TF103C */
1875 .matches = {
1876 DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK COMPUTER INC."),
1877 DMI_MATCH(DMI_PRODUCT_NAME, "TF103C"),
1878 },
1879 .driver_data = (void *)vlv_dsi_asus_tf103c_mode_fixup,
1880 },
1881 {
1882 /*
1883 * Lenovo Yoga Tablet 2 830F/L or 1050F/L (The 8" and 10"
1884 * Lenovo Yoga Tablet 2 use the same mainboard)
1885 */
1886 .matches = {
1887 DMI_MATCH(DMI_SYS_VENDOR, "Intel Corp."),
1888 DMI_MATCH(DMI_PRODUCT_NAME, "VALLEYVIEW C0 PLATFORM"),
1889 DMI_MATCH(DMI_BOARD_NAME, "BYT-T FFD8"),
1890 /* Partial match on beginning of BIOS version */
1891 DMI_MATCH(DMI_BIOS_VERSION, "BLADE_21"),
1892 },
1893 .driver_data = (void *)vlv_dsi_lenovo_yoga_tab2_size_fixup,
1894 },
1895 {
1896 /* Lenovo Yoga Tab 3 Pro YT3-X90F */
1897 .matches = {
1898 DMI_MATCH(DMI_SYS_VENDOR, "Intel Corporation"),
1899 DMI_MATCH(DMI_PRODUCT_VERSION, "Blade3-10A-001"),
1900 },
1901 .driver_data = (void *)vlv_dsi_lenovo_yoga_tab3_backlight_fixup,
1902 },
1903 { }
1904 };
1905
vlv_dsi_init(struct drm_i915_private * dev_priv)1906 void vlv_dsi_init(struct drm_i915_private *dev_priv)
1907 {
1908 struct intel_display *display = &dev_priv->display;
1909 struct intel_dsi *intel_dsi;
1910 struct intel_encoder *encoder;
1911 struct intel_connector *connector;
1912 struct drm_display_mode *current_mode;
1913 const struct dmi_system_id *dmi_id;
1914 enum port port;
1915 enum pipe pipe;
1916
1917 drm_dbg_kms(&dev_priv->drm, "\n");
1918
1919 /* There is no detection method for MIPI so rely on VBT */
1920 if (!intel_bios_is_dsi_present(display, &port))
1921 return;
1922
1923 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
1924 dev_priv->display.dsi.mmio_base = BXT_MIPI_BASE;
1925 else
1926 dev_priv->display.dsi.mmio_base = VLV_MIPI_BASE;
1927
1928 intel_dsi = kzalloc(sizeof(*intel_dsi), GFP_KERNEL);
1929 if (!intel_dsi)
1930 return;
1931
1932 connector = intel_connector_alloc();
1933 if (!connector) {
1934 kfree(intel_dsi);
1935 return;
1936 }
1937
1938 encoder = &intel_dsi->base;
1939 intel_dsi->attached_connector = connector;
1940
1941 drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_dsi_funcs,
1942 DRM_MODE_ENCODER_DSI, "DSI %c", port_name(port));
1943
1944 encoder->compute_config = intel_dsi_compute_config;
1945 encoder->pre_enable = intel_dsi_pre_enable;
1946 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
1947 encoder->enable = bxt_dsi_enable;
1948 encoder->disable = intel_dsi_disable;
1949 encoder->post_disable = intel_dsi_post_disable;
1950 encoder->get_hw_state = intel_dsi_get_hw_state;
1951 encoder->get_config = intel_dsi_get_config;
1952 encoder->update_pipe = intel_backlight_update;
1953 encoder->shutdown = intel_dsi_shutdown;
1954
1955 connector->get_hw_state = intel_connector_get_hw_state;
1956
1957 encoder->port = port;
1958 encoder->type = INTEL_OUTPUT_DSI;
1959 encoder->power_domain = POWER_DOMAIN_PORT_DSI;
1960 encoder->cloneable = 0;
1961
1962 /*
1963 * On BYT/CHV, pipe A maps to MIPI DSI port A, pipe B maps to MIPI DSI
1964 * port C. BXT isn't limited like this.
1965 */
1966 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
1967 encoder->pipe_mask = ~0;
1968 else if (port == PORT_A)
1969 encoder->pipe_mask = BIT(PIPE_A);
1970 else
1971 encoder->pipe_mask = BIT(PIPE_B);
1972
1973 intel_dsi->panel_power_off_time = ktime_get_boottime();
1974
1975 intel_bios_init_panel_late(display, &connector->panel, NULL, NULL);
1976
1977 if (connector->panel.vbt.dsi.config->dual_link)
1978 intel_dsi->ports = BIT(PORT_A) | BIT(PORT_C);
1979 else
1980 intel_dsi->ports = BIT(port);
1981
1982 if (drm_WARN_ON(&dev_priv->drm, connector->panel.vbt.dsi.bl_ports & ~intel_dsi->ports))
1983 connector->panel.vbt.dsi.bl_ports &= intel_dsi->ports;
1984
1985 if (drm_WARN_ON(&dev_priv->drm, connector->panel.vbt.dsi.cabc_ports & ~intel_dsi->ports))
1986 connector->panel.vbt.dsi.cabc_ports &= intel_dsi->ports;
1987
1988 /* Create a DSI host (and a device) for each port. */
1989 for_each_dsi_port(port, intel_dsi->ports) {
1990 struct intel_dsi_host *host;
1991
1992 host = intel_dsi_host_init(intel_dsi, &intel_dsi_host_ops,
1993 port);
1994 if (!host)
1995 goto err;
1996
1997 intel_dsi->dsi_hosts[port] = host;
1998 }
1999
2000 if (!intel_dsi_vbt_init(intel_dsi, MIPI_DSI_GENERIC_PANEL_ID)) {
2001 drm_dbg_kms(&dev_priv->drm, "no device found\n");
2002 goto err;
2003 }
2004
2005 /* Use clock read-back from current hw-state for fastboot */
2006 current_mode = intel_encoder_current_mode(encoder);
2007 if (current_mode) {
2008 drm_dbg_kms(&dev_priv->drm, "Calculated pclk %d GOP %d\n",
2009 intel_dsi->pclk, current_mode->clock);
2010 if (intel_fuzzy_clock_check(intel_dsi->pclk,
2011 current_mode->clock)) {
2012 drm_dbg_kms(&dev_priv->drm, "Using GOP pclk\n");
2013 intel_dsi->pclk = current_mode->clock;
2014 }
2015
2016 kfree(current_mode);
2017 }
2018
2019 vlv_dphy_param_init(intel_dsi);
2020
2021 intel_dsi_vbt_gpio_init(intel_dsi,
2022 intel_dsi_get_hw_state(encoder, &pipe));
2023
2024 drm_connector_init(&dev_priv->drm, &connector->base, &intel_dsi_connector_funcs,
2025 DRM_MODE_CONNECTOR_DSI);
2026
2027 drm_connector_helper_add(&connector->base, &intel_dsi_connector_helper_funcs);
2028
2029 connector->base.display_info.subpixel_order = SubPixelHorizontalRGB; /*XXX*/
2030
2031 intel_connector_attach_encoder(connector, encoder);
2032
2033 mutex_lock(&dev_priv->drm.mode_config.mutex);
2034 intel_panel_add_vbt_lfp_fixed_mode(connector);
2035 mutex_unlock(&dev_priv->drm.mode_config.mutex);
2036
2037 if (!intel_panel_preferred_fixed_mode(connector)) {
2038 drm_dbg_kms(&dev_priv->drm, "no fixed mode\n");
2039 goto err_cleanup_connector;
2040 }
2041
2042 dmi_id = dmi_first_match(vlv_dsi_dmi_quirk_table);
2043 if (dmi_id) {
2044 vlv_dsi_dmi_quirk_func quirk_func =
2045 (vlv_dsi_dmi_quirk_func)dmi_id->driver_data;
2046
2047 quirk_func(intel_dsi);
2048 }
2049
2050 intel_panel_init(connector, NULL);
2051
2052 intel_backlight_setup(connector, INVALID_PIPE);
2053
2054 vlv_dsi_add_properties(connector);
2055
2056 return;
2057
2058 err_cleanup_connector:
2059 drm_connector_cleanup(&connector->base);
2060 err:
2061 drm_encoder_cleanup(&encoder->base);
2062 kfree(intel_dsi);
2063 kfree(connector);
2064 }
2065