1 /*
2 * \file trc_pkt_elem_etmv4i.cpp
3 * \brief OpenCSD :
4 *
5 * \copyright Copyright (c) 2015, ARM Limited. All Rights Reserved.
6 */
7
8 /*
9 * Redistribution and use in source and binary forms, with or without modification,
10 * are permitted provided that the following conditions are met:
11 *
12 * 1. Redistributions of source code must retain the above copyright notice,
13 * this list of conditions and the following disclaimer.
14 *
15 * 2. Redistributions in binary form must reproduce the above copyright notice,
16 * this list of conditions and the following disclaimer in the documentation
17 * and/or other materials provided with the distribution.
18 *
19 * 3. Neither the name of the copyright holder nor the names of its contributors
20 * may be used to endorse or promote products derived from this software without
21 * specific prior written permission.
22 *
23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 'AS IS' AND
24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
26 * IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
27 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34 #include <sstream>
35 #include <iomanip>
36
37 #include "opencsd/etmv4/trc_pkt_elem_etmv4i.h"
38
EtmV4ITrcPacket()39 EtmV4ITrcPacket::EtmV4ITrcPacket()
40 {
41 protocol_version = 0x42; // min protocol version.
42 }
43
~EtmV4ITrcPacket()44 EtmV4ITrcPacket::~EtmV4ITrcPacket()
45 {
46 }
47
initStartState()48 void EtmV4ITrcPacket::initStartState()
49 {
50 // clear packet state to start of trace (first sync or post discontinuity)
51
52 // clear all valid bits
53 pkt_valid.val = 0;
54
55 // virtual address
56 v_addr.pkt_bits = 0;
57 v_addr.valid_bits = 0;
58 v_addr_ISA = 0;
59
60 // timestamp
61 ts.bits_changed = 0;
62 ts.timestamp = 0;
63
64 // per packet init
65 initNextPacket();
66 }
67
initNextPacket()68 void EtmV4ITrcPacket::initNextPacket()
69 {
70 // clear valid bits for elements that are only valid over a single packet.
71 pkt_valid.bits.cc_valid = 0;
72 pkt_valid.bits.commit_elem_valid = 0;
73 atom.num = 0;
74 context.updated = 0;
75 context.updated_v = 0;
76 context.updated_c = 0;
77 err_type = ETM4_PKT_I_NO_ERR_TYPE;
78 }
79
80 // printing
toString(std::string & str) const81 void EtmV4ITrcPacket::toString(std::string &str) const
82 {
83 const char *name;
84 const char *desc;
85 std::string valStr, ctxtStr = "";
86
87 name = packetTypeName(type, &desc);
88 str = name + (std::string)" : " + desc;
89
90 // extended descriptions
91 switch (type)
92 {
93 case ETM4_PKT_I_BAD_SEQUENCE:
94 case ETM4_PKT_I_INCOMPLETE_EOT:
95 case ETM4_PKT_I_RESERVED_CFG:
96 name = packetTypeName(err_type, 0);
97 str += "[" + (std::string)name + "]";
98 break;
99
100 case ETM4_PKT_I_ADDR_CTXT_L_32IS0:
101 case ETM4_PKT_I_ADDR_CTXT_L_32IS1:
102 contextStr(ctxtStr);
103 case ETM4_PKT_I_ADDR_L_32IS0:
104 case ETM4_PKT_I_ADDR_L_32IS1:
105 case ETE_PKT_I_SRC_ADDR_L_32IS0:
106 case ETE_PKT_I_SRC_ADDR_L_32IS1:
107 trcPrintableElem::getValStr(valStr, (v_addr.size == VA_64BIT) ? 64 : 32, v_addr.valid_bits, v_addr.val, true, (v_addr.pkt_bits < 32) ? v_addr.pkt_bits : 0);
108 str += "; Addr=" + valStr + "; " + ctxtStr;
109 break;
110
111 case ETM4_PKT_I_ADDR_CTXT_L_64IS0:
112 case ETM4_PKT_I_ADDR_CTXT_L_64IS1:
113 contextStr(ctxtStr);
114 case ETM4_PKT_I_ADDR_L_64IS0:
115 case ETM4_PKT_I_ADDR_L_64IS1:
116 case ETE_PKT_I_SRC_ADDR_L_64IS0:
117 case ETE_PKT_I_SRC_ADDR_L_64IS1:
118 trcPrintableElem::getValStr(valStr, (v_addr.size == VA_64BIT) ? 64 : 32, v_addr.valid_bits, v_addr.val, true, (v_addr.pkt_bits < 64) ? v_addr.pkt_bits : 0);
119 str += "; Addr=" + valStr + "; " + ctxtStr;
120 break;
121
122 case ETM4_PKT_I_CTXT:
123 contextStr(ctxtStr);
124 str += "; " + ctxtStr;
125 break;
126
127 case ETM4_PKT_I_ADDR_S_IS0:
128 case ETM4_PKT_I_ADDR_S_IS1:
129 case ETE_PKT_I_SRC_ADDR_S_IS0:
130 case ETE_PKT_I_SRC_ADDR_S_IS1:
131 trcPrintableElem::getValStr(valStr, (v_addr.size == VA_64BIT) ? 64 : 32, v_addr.valid_bits, v_addr.val, true, v_addr.pkt_bits);
132 str += "; Addr=" + valStr;
133 break;
134
135 case ETM4_PKT_I_ADDR_MATCH:
136 case ETE_PKT_I_SRC_ADDR_MATCH:
137 addrMatchIdx(valStr);
138 str += ", " + valStr;
139 trcPrintableElem::getValStr(valStr, (v_addr.size == VA_64BIT) ? 64 : 32, v_addr.valid_bits, v_addr.val, true);
140 str += "; Addr=" + valStr + "; " + ctxtStr;
141 break;
142
143 case ETM4_PKT_I_ATOM_F1:
144 case ETM4_PKT_I_ATOM_F2:
145 case ETM4_PKT_I_ATOM_F3:
146 case ETM4_PKT_I_ATOM_F4:
147 case ETM4_PKT_I_ATOM_F5:
148 case ETM4_PKT_I_ATOM_F6:
149 atomSeq(valStr);
150 str += "; " + valStr;
151 break;
152
153 case ETM4_PKT_I_EXCEPT:
154 exceptionInfo(valStr);
155 str += "; " + valStr;
156 break;
157
158 case ETM4_PKT_I_TIMESTAMP:
159 {
160 std::ostringstream oss;
161 oss << "; Updated val = " << std::hex << "0x" << ts.timestamp;
162 if (pkt_valid.bits.cc_valid)
163 oss << "; CC=" << std::hex << "0x" << cycle_count;
164 str += oss.str();
165 }
166 break;
167
168 case ETM4_PKT_I_TRACE_INFO:
169 {
170 std::ostringstream oss;
171 oss << "; INFO=" << std::hex << "0x" << trace_info.val;
172 oss << " { CC." << std::dec << trace_info.bits.cc_enabled;
173 if (isETE())
174 oss << ", TSTATE." << std::dec << trace_info.bits.in_trans_state;
175 oss << " }";
176 if (trace_info.bits.cc_enabled)
177 oss << "; CC_THRESHOLD=" << std::hex << "0x" << cc_threshold;
178 str += oss.str();
179 }
180 break;
181
182 case ETM4_PKT_I_CCNT_F1:
183 case ETM4_PKT_I_CCNT_F2:
184 case ETM4_PKT_I_CCNT_F3:
185 {
186 std::ostringstream oss;
187 oss << "; Count=" << std::hex << "0x" << cycle_count;
188 str += oss.str();
189 }
190 break;
191
192 case ETM4_PKT_I_CANCEL_F1:
193 {
194 std::ostringstream oss;
195 oss << "; Cancel(" << std::dec << cancel_elements << ")";
196 str += oss.str();
197 }
198 break;
199
200 case ETM4_PKT_I_CANCEL_F1_MISPRED:
201 {
202 std::ostringstream oss;
203 oss << "; Cancel(" << std::dec << cancel_elements << "), Mispredict";
204 str += oss.str();
205 }
206 break;
207
208 case ETM4_PKT_I_MISPREDICT:
209 {
210 std::ostringstream oss;
211 oss << "; ";
212 if (atom.num) {
213 atomSeq(valStr);
214 oss << "Atom: " << valStr << ", ";
215 }
216 oss << "Mispredict";
217 str += oss.str();
218 }
219 break;
220
221 case ETM4_PKT_I_CANCEL_F2:
222 {
223 std::ostringstream oss;
224 oss << "; ";
225 if (atom.num) {
226 atomSeq(valStr);
227 oss << "Atom: " << valStr << ", ";
228 }
229 oss << "Cancel(1), Mispredict";
230 str += oss.str();
231 }
232 break;
233
234 case ETM4_PKT_I_CANCEL_F3:
235 {
236 std::ostringstream oss;
237 oss << "; ";
238 if (atom.num) {
239 oss << "Atom: E, ";
240 }
241 oss << "Cancel(" << std::dec << cancel_elements << "), Mispredict";
242 str += oss.str();
243 }
244 break;
245
246 case ETM4_PKT_I_COMMIT:
247 {
248 std::ostringstream oss;
249 oss << "; Commit(" << std::dec << commit_elements << ")";
250 str += oss.str();
251 }
252 break;
253
254 case ETM4_PKT_I_Q:
255 {
256 std::ostringstream oss;
257 if (Q_pkt.count_present)
258 {
259 oss << "; Count(" << std::dec << Q_pkt.q_count << ")";
260 str += oss.str();
261 }
262 else
263 str += "; Count(Unknown)";
264
265 if (Q_pkt.addr_match)
266 {
267 addrMatchIdx(valStr);
268 str += "; " + valStr;
269 }
270
271 if (Q_pkt.addr_present || Q_pkt.addr_match)
272 {
273 trcPrintableElem::getValStr(valStr, (v_addr.size == VA_64BIT) ? 64 : 32, v_addr.valid_bits, v_addr.val, true, (v_addr.pkt_bits < 64) ? v_addr.pkt_bits : 0);
274 str += "; Addr=" + valStr;
275 }
276 }
277 break;
278
279 case ETE_PKT_I_ITE:
280 {
281 std::ostringstream oss;
282 oss << "; EL" << std::dec << (int)ite_pkt.el << "; Payload=0x" << std::hex << ite_pkt.value;
283 str += oss.str();
284 }
285 break;
286 }
287
288 }
289
toStringFmt(const uint32_t fmtFlags,std::string & str) const290 void EtmV4ITrcPacket::toStringFmt(const uint32_t fmtFlags, std::string &str) const
291 {
292 toString(str); // TBD add in formatted response.
293 }
294
packetTypeName(const ocsd_etmv4_i_pkt_type type,const char ** ppDesc) const295 const char *EtmV4ITrcPacket::packetTypeName(const ocsd_etmv4_i_pkt_type type, const char **ppDesc) const
296 {
297 const char *pName = "I_UNKNOWN";
298 const char *pDesc = "Unknown Packet Header";
299
300 switch(type)
301 {
302 case ETM4_PKT_I_NOTSYNC:
303 pName = "I_NOT_SYNC";
304 pDesc = "I Stream not synchronised";
305 break;
306
307 case ETM4_PKT_I_INCOMPLETE_EOT:
308 pName = "I_INCOMPLETE_EOT";
309 pDesc = "Incomplete packet at end of trace.";
310 break;
311
312 case ETM4_PKT_I_NO_ERR_TYPE:
313 pName = "I_NO_ERR_TYPE";
314 pDesc = "No Error Type.";
315 break;
316
317 case ETM4_PKT_I_BAD_SEQUENCE:
318 pName = "I_BAD_SEQUENCE";
319 pDesc = "Invalid Sequence in packet.";
320 break;
321
322 case ETM4_PKT_I_BAD_TRACEMODE:
323 pName = "I_BAD_TRACEMODE";
324 pDesc = "Invalid Packet for trace mode.";
325 break;
326
327 case ETM4_PKT_I_RESERVED:
328 pName = "I_RESERVED";
329 pDesc = "Reserved Packet Header";
330 break;
331
332 case ETM4_PKT_I_RESERVED_CFG:
333 pName = "I_RESERVED_CFG";
334 pDesc = "Reserved header for current configuration.";
335 break;
336
337 case ETM4_PKT_I_EXTENSION:
338 pName = "I_EXTENSION";
339 pDesc = "Extension packet header.";
340 break;
341
342 case ETM4_PKT_I_TRACE_INFO:
343 pName = "I_TRACE_INFO";
344 pDesc = "Trace Info.";
345 break;
346
347 case ETM4_PKT_I_TIMESTAMP:
348 pName = "I_TIMESTAMP";
349 pDesc = "Timestamp.";
350 break;
351
352 case ETM4_PKT_I_TRACE_ON:
353 pName = "I_TRACE_ON";
354 pDesc = "Trace On.";
355 break;
356
357 case ETM4_PKT_I_FUNC_RET:
358 pName = "I_FUNC_RET";
359 pDesc = "V8M - function return.";
360 break;
361
362 case ETM4_PKT_I_EXCEPT:
363 pName = "I_EXCEPT";
364 pDesc = "Exception.";
365 break;
366
367 case ETM4_PKT_I_EXCEPT_RTN:
368 pName = "I_EXCEPT_RTN";
369 pDesc = "Exception Return.";
370 break;
371
372 case ETE_PKT_I_TRANS_ST:
373 pName = "I_TRANS_ST";
374 pDesc = "Transaction Start.";
375 break;
376
377 case ETE_PKT_I_TRANS_COMMIT:
378 pName = "I_TRANS_COMMIT";
379 pDesc = "Transaction Commit.";
380 break;
381
382 case ETM4_PKT_I_CCNT_F1:
383 pName = "I_CCNT_F1";
384 pDesc = "Cycle Count format 1.";
385 break;
386
387 case ETM4_PKT_I_CCNT_F2:
388 pName = "I_CCNT_F2";
389 pDesc = "Cycle Count format 2.";
390 break;
391
392 case ETM4_PKT_I_CCNT_F3:
393 pName = "I_CCNT_F3";
394 pDesc = "Cycle Count format 3.";
395 break;
396
397 case ETM4_PKT_I_NUM_DS_MKR:
398 pName = "I_NUM_DS_MKR";
399 pDesc = "Data Synchronisation Marker - Numbered.";
400 break;
401
402 case ETM4_PKT_I_UNNUM_DS_MKR:
403 pName = "I_UNNUM_DS_MKR";
404 pDesc = "Data Synchronisation Marker - Unnumbered.";
405 break;
406
407 case ETM4_PKT_I_COMMIT:
408 pName = "I_COMMIT";
409 pDesc = "Commit";
410 break;
411
412 case ETM4_PKT_I_CANCEL_F1:
413 pName = "I_CANCEL_F1";
414 pDesc = "Cancel Format 1.";
415 break;
416
417 case ETM4_PKT_I_CANCEL_F1_MISPRED:
418 pName = "I_CANCEL_F1_MISPRED";
419 pDesc = "Cancel Format 1 + Mispredict.";
420 break;
421
422
423 case ETM4_PKT_I_MISPREDICT:
424 pName = "I_MISPREDICT";
425 pDesc = "Mispredict.";
426 break;
427
428 case ETM4_PKT_I_CANCEL_F2:
429 pName = "I_CANCEL_F2";
430 pDesc = "Cancel Format 2.";
431 break;
432
433 case ETM4_PKT_I_CANCEL_F3:
434 pName = "I_CANCEL_F3";
435 pDesc = "Cancel Format 3.";
436 break;
437
438 case ETM4_PKT_I_COND_I_F2:
439 pName = "I_COND_I_F2";
440 pDesc = "Conditional Instruction, format 2.";
441 break;
442
443 case ETM4_PKT_I_COND_FLUSH:
444 pName = "I_COND_FLUSH";
445 pDesc = "Conditional Flush.";
446 break;
447
448 case ETM4_PKT_I_COND_RES_F4:
449 pName = "I_COND_RES_F4";
450 pDesc = "Conditional Result, format 4.";
451 break;
452
453 case ETM4_PKT_I_COND_RES_F2:
454 pName = "I_COND_RES_F2";
455 pDesc = "Conditional Result, format 2.";
456 break;
457
458 case ETM4_PKT_I_COND_RES_F3:
459 pName = "I_COND_RES_F3";
460 pDesc = "Conditional Result, format 3.";
461 break;
462
463 case ETM4_PKT_I_COND_RES_F1:
464 pName = "I_COND_RES_F1";
465 pDesc = "Conditional Result, format 1.";
466 break;
467
468 case ETM4_PKT_I_COND_I_F1:
469 pName = "I_COND_I_F1";
470 pDesc = "Conditional Instruction, format 1.";
471 break;
472
473 case ETM4_PKT_I_COND_I_F3:
474 pName = "I_COND_I_F3";
475 pDesc = "Conditional Instruction, format 3.";
476 break;
477
478 case ETM4_PKT_I_IGNORE:
479 pName = "I_IGNORE";
480 pDesc = "Ignore.";
481 break;
482
483 case ETM4_PKT_I_EVENT:
484 pName = "I_EVENT";
485 pDesc = "Trace Event.";
486 break;
487
488 case ETM4_PKT_I_CTXT:
489 pName = "I_CTXT";
490 pDesc = "Context Packet.";
491 break;
492
493 case ETM4_PKT_I_ADDR_CTXT_L_32IS0:
494 pName = "I_ADDR_CTXT_L_32IS0";
495 pDesc = "Address & Context, Long, 32 bit, IS0.";
496 break;
497
498 case ETM4_PKT_I_ADDR_CTXT_L_32IS1:
499 pName = "I_ADDR_CTXT_L_32IS1";
500 pDesc = "Address & Context, Long, 32 bit, IS0.";
501 break;
502
503 case ETM4_PKT_I_ADDR_CTXT_L_64IS0:
504 pName = "I_ADDR_CTXT_L_64IS0";
505 pDesc = "Address & Context, Long, 64 bit, IS0.";
506 break;
507
508 case ETM4_PKT_I_ADDR_CTXT_L_64IS1:
509 pName = "I_ADDR_CTXT_L_64IS1";
510 pDesc = "Address & Context, Long, 64 bit, IS1.";
511 break;
512
513 case ETE_PKT_I_TS_MARKER:
514 pName = "I_TS_MARKER";
515 pDesc = "Timestamp Marker";
516 break;
517
518 case ETM4_PKT_I_ADDR_MATCH:
519 pName = "I_ADDR_MATCH";
520 pDesc = "Exact Address Match.";
521 break;
522
523 case ETM4_PKT_I_ADDR_S_IS0:
524 pName = "I_ADDR_S_IS0";
525 pDesc = "Address, Short, IS0.";
526 break;
527
528 case ETM4_PKT_I_ADDR_S_IS1:
529 pName = "I_ADDR_S_IS1";
530 pDesc = "Address, Short, IS1.";
531 break;
532
533 case ETM4_PKT_I_ADDR_L_32IS0:
534 pName = "I_ADDR_L_32IS0";
535 pDesc = "Address, Long, 32 bit, IS0.";
536 break;
537
538 case ETM4_PKT_I_ADDR_L_32IS1:
539 pName = "I_ADDR_L_32IS1";
540 pDesc = "Address, Long, 32 bit, IS1.";
541 break;
542
543 case ETM4_PKT_I_ADDR_L_64IS0:
544 pName = "I_ADDR_L_64IS0";
545 pDesc = "Address, Long, 64 bit, IS0.";
546 break;
547
548 case ETM4_PKT_I_ADDR_L_64IS1:
549 pName = "I_ADDR_L_64IS1";
550 pDesc = "Address, Long, 64 bit, IS1.";
551 break;
552
553 case ETM4_PKT_I_Q:
554 pName = "I_Q";
555 pDesc = "Q Packet.";
556 break;
557
558 case ETE_PKT_I_SRC_ADDR_MATCH:
559 pName = "I_SRC_ADDR_MATCH";
560 pDesc = "Exact Source Address Match.";
561 break;
562
563 case ETE_PKT_I_SRC_ADDR_S_IS0:
564 pName = "I_SRC_ADDR_S_IS0";
565 pDesc = "Source Address, Short, IS0.";
566 break;
567
568 case ETE_PKT_I_SRC_ADDR_S_IS1:
569 pName = "I_SRC_ADDR_S_IS1";
570 pDesc = "Source Address, Short, IS1.";
571 break;
572
573 case ETE_PKT_I_SRC_ADDR_L_32IS0:
574 pName = "I_SCR_ADDR_L_32IS0";
575 pDesc = "Source Address, Long, 32 bit, IS0.";
576 break;
577
578 case ETE_PKT_I_SRC_ADDR_L_32IS1:
579 pName = "I_SRC_ADDR_L_32IS1";
580 pDesc = "Source Address, Long, 32 bit, IS1.";
581 break;
582
583 case ETE_PKT_I_SRC_ADDR_L_64IS0:
584 pName = "I_SRC_ADDR_L_64IS0";
585 pDesc = "Source Address, Long, 64 bit, IS0.";
586 break;
587
588 case ETE_PKT_I_SRC_ADDR_L_64IS1:
589 pName = "I_SRC_ADDR_L_64IS1";
590 pDesc = "Source Address, Long, 64 bit, IS1.";
591 break;
592
593 case ETM4_PKT_I_ATOM_F6:
594 pName = "I_ATOM_F6";
595 pDesc = "Atom format 6.";
596 break;
597
598 case ETM4_PKT_I_ATOM_F5:
599 pName = "I_ATOM_F5";
600 pDesc = "Atom format 5.";
601 break;
602
603 case ETM4_PKT_I_ATOM_F2:
604 pName = "I_ATOM_F2";
605 pDesc = "Atom format 2.";
606 break;
607
608 case ETM4_PKT_I_ATOM_F4:
609 pName = "I_ATOM_F4";
610 pDesc = "Atom format 4.";
611 break;
612
613 case ETM4_PKT_I_ATOM_F1:
614 pName = "I_ATOM_F1";
615 pDesc = "Atom format 1.";
616 break;
617
618 case ETM4_PKT_I_ATOM_F3:
619 pName = "I_ATOM_F3";
620 pDesc = "Atom format 3.";
621 break;
622
623 case ETM4_PKT_I_ASYNC:
624 pName = "I_ASYNC";
625 pDesc = "Alignment Synchronisation.";
626 break;
627
628 case ETM4_PKT_I_DISCARD:
629 pName = "I_DISCARD";
630 pDesc = "Discard.";
631 break;
632
633 case ETM4_PKT_I_OVERFLOW:
634 pName = "I_OVERFLOW";
635 pDesc = "Overflow.";
636 break;
637
638 case ETE_PKT_I_PE_RESET:
639 pName = "I_PE_RESET";
640 pDesc = "PE Reset.";
641 break;
642
643 case ETE_PKT_I_TRANS_FAIL:
644 pName = "I_TRANS_FAIL";
645 pDesc = "Transaction Fail.";
646 break;
647
648 case ETE_PKT_I_ITE:
649 pName = "I_ITE";
650 pDesc = "Instrumentation";
651 break;
652
653 default:
654 break;
655 }
656
657 if(ppDesc) *ppDesc = pDesc;
658 return pName;
659 }
660
contextStr(std::string & ctxtStr) const661 void EtmV4ITrcPacket::contextStr(std::string &ctxtStr) const
662 {
663 ctxtStr = "";
664 if(pkt_valid.bits.context_valid)
665 {
666 std::ostringstream oss;
667 if(context.updated)
668 {
669 oss << "Ctxt: " << (context.SF ? "AArch64," : "AArch32, ") << "EL" << context.EL << ", " << (context.NS ? "NS; " : "S; ");
670 if(context.updated_c)
671 {
672 oss << "CID=0x" << std::hex << std::setfill('0') << std::setw(8) << context.ctxtID << "; ";
673 }
674 if(context.updated_v)
675 {
676 oss << "VMID=0x" << std::hex << std::setfill('0') << std::setw(4) << context.VMID << "; ";
677 }
678 }
679 else
680 {
681 oss << "Ctxt: Same";
682 }
683 ctxtStr = oss.str();
684 }
685 }
686
atomSeq(std::string & valStr) const687 void EtmV4ITrcPacket::atomSeq(std::string &valStr) const
688 {
689 std::ostringstream oss;
690 uint32_t bitpattern = atom.En_bits;
691 for(int i = 0; i < atom.num; i++)
692 {
693 oss << ((bitpattern & 0x1) ? "E" : "N");
694 bitpattern >>= 1;
695 }
696 valStr = oss.str();
697 }
698
addrMatchIdx(std::string & valStr) const699 void EtmV4ITrcPacket::addrMatchIdx(std::string &valStr) const
700 {
701 std::ostringstream oss;
702 oss << "[" << (uint16_t)addr_exact_match_idx << "]";
703 valStr = oss.str();
704 }
705
exceptionInfo(std::string & valStr) const706 void EtmV4ITrcPacket::exceptionInfo(std::string &valStr) const
707 {
708 std::ostringstream oss;
709
710 static const char *ARv8Excep[] = {
711 "PE Reset", "Debug Halt", "Call", "Trap",
712 "System Error", "Reserved", "Inst Debug", "Data Debug",
713 "Reserved", "Reserved", "Alignment", "Inst Fault",
714 "Data Fault", "Reserved", "IRQ", "FIQ"
715 };
716
717 static const char *MExcep[] = {
718 "Reserved", "PE Reset", "NMI", "HardFault",
719 "MemManage", "BusFault", "UsageFault", "Reserved",
720 "Reserved","Reserved","Reserved","SVC",
721 "DebugMonitor", "Reserved","PendSV","SysTick",
722 "IRQ0","IRQ1","IRQ2","IRQ3",
723 "IRQ4","IRQ5","IRQ6","IRQ7",
724 "DebugHalt", "LazyFP Push", "Lockup", "Reserved",
725 "Reserved","Reserved","Reserved","Reserved"
726 };
727
728 if(exception_info.m_type == 0)
729 {
730 if(exception_info.exceptionType < 0x10)
731 oss << " " << ARv8Excep[exception_info.exceptionType] << ";";
732 else
733 oss << " Reserved;";
734
735 }
736 else
737 {
738 if(exception_info.exceptionType < 0x20)
739 oss << " " << MExcep[exception_info.exceptionType] << ";";
740 else if((exception_info.exceptionType >= 0x208) && (exception_info.exceptionType <= 0x3EF))
741 oss << " IRQ" << (int)(exception_info.exceptionType - 0x200) << ";";
742 else
743 oss << " Reserved;";
744 if(exception_info.m_fault_pending)
745 oss << " Fault Pending;";
746 }
747
748 if(exception_info.addr_interp == 0x1)
749 oss << " Ret Addr Follows;";
750 else if(exception_info.addr_interp == 0x2)
751 oss << " Ret Addr Follows, Match Prev;";
752
753 valStr = oss.str();
754 }
755
operator =(const ocsd_etmv4_i_pkt * p_pkt)756 EtmV4ITrcPacket &EtmV4ITrcPacket::operator =(const ocsd_etmv4_i_pkt* p_pkt)
757 {
758 *dynamic_cast<ocsd_etmv4_i_pkt *>(this) = *p_pkt;
759 return *this;
760 }
761
762 /* End of File trc_pkt_elem_etmv4i.cpp */
763