xref: /illumos-gate/usr/src/uts/common/io/cxgbe/common/t4_regs_values.h (revision 7e6ad4690aa1d3cbf260ef54d5e9632ae40a782e)
1 /*
2  * This file and its contents are supplied under the terms of the
3  * Common Development and Distribution License ("CDDL"), version 1.0.
4  * You may only use this file in accordance with the terms of version
5  * 1.0 of the CDDL.
6  *
7  * A full copy of the text of the CDDL should have accompanied this
8  * source. A copy of the CDDL is also available via the Internet at
9  * http://www.illumos.org/license/CDDL.
10  */
11 
12 /*
13  * This file is part of the Chelsio T4/T5/T6 support code.
14  *
15  * Copyright (C) 2003-2019 Chelsio Communications.  All rights reserved.
16  *
17  * This program is distributed in the hope that it will be useful, but WITHOUT
18  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
19  * FITNESS FOR A PARTICULAR PURPOSE.  See the LICENSE file included in this
20  * release for licensing terms and conditions.
21  */
22 
23 #ifndef __T4_REGS_VALUES_H__
24 #define __T4_REGS_VALUES_H__
25 
26 /*
27  * This file contains definitions for various T4 register value hardware
28  * constants.  The types of values encoded here are predominantly those for
29  * register fields which control "modal" behavior.  For the most part, we do
30  * not include definitions for register fields which are simple numeric
31  * metrics, etc.
32  *
33  * These new "modal values" use a naming convention which matches the
34  * currently existing macros in t4_reg.h.  For register field FOO which would
35  * have S_FOO, M_FOO, V_FOO() and G_FOO() macros, we introduce X_FOO_{MODE}
36  * definitions.  These can be used as V_FOO(X_FOO_MODE) or as (G_FOO(x) ==
37  * X_FOO_MODE).
38  *
39  * Note that this should all be part of t4_regs.h but the toolset used to
40  * generate that file doesn't [yet] have the capability of collecting these
41  * constants.
42  */
43 
44 /*
45  * SGE definitions.
46  * ================
47  */
48 
49 /*
50  * SGE register field values.
51  */
52 
53 /* CONTROL register */
54 #define X_FLSPLITMODE_FLSPLITMIN	0
55 #define X_FLSPLITMODE_ETHHDR		1
56 #define X_FLSPLITMODE_IPHDR		2
57 #define X_FLSPLITMODE_TCPHDR		3
58 
59 #define X_DCASYSTYPE_FSB		0
60 #define X_DCASYSTYPE_CSI		1
61 
62 #define X_EGSTATPAGESIZE_64B		0
63 #define X_EGSTATPAGESIZE_128B		1
64 
65 #define X_RXPKTCPLMODE_DATA		0
66 #define X_RXPKTCPLMODE_SPLIT		1
67 
68 #define X_INGPCIEBOUNDARY_SHIFT		5
69 #define X_INGPCIEBOUNDARY_32B		0
70 #define X_INGPCIEBOUNDARY_64B		1
71 #define X_INGPCIEBOUNDARY_128B		2
72 #define X_INGPCIEBOUNDARY_256B		3
73 #define X_INGPCIEBOUNDARY_512B		4
74 #define X_INGPCIEBOUNDARY_1024B		5
75 #define X_INGPCIEBOUNDARY_2048B		6
76 #define X_INGPCIEBOUNDARY_4096B		7
77 
78 #define X_T6_INGPADBOUNDARY_SHIFT	3
79 #define X_T6_INGPADBOUNDARY_8B		0
80 #define X_T6_INGPADBOUNDARY_16B		1
81 #define X_T6_INGPADBOUNDARY_32B		2
82 #define X_T6_INGPADBOUNDARY_64B		3
83 #define X_T6_INGPADBOUNDARY_128B	4
84 #define X_T6_INGPADBOUNDARY_256B	5
85 #define X_T6_INGPADBOUNDARY_512B	6
86 #define X_T6_INGPADBOUNDARY_1024B	7
87 
88 #define X_INGPADBOUNDARY_SHIFT		5
89 #define X_INGPADBOUNDARY_32B		0
90 #define X_INGPADBOUNDARY_64B		1
91 #define X_INGPADBOUNDARY_128B		2
92 #define X_INGPADBOUNDARY_256B		3
93 #define X_INGPADBOUNDARY_512B		4
94 #define X_INGPADBOUNDARY_1024B		5
95 #define X_INGPADBOUNDARY_2048B		6
96 #define X_INGPADBOUNDARY_4096B		7
97 
98 #define X_EGRPCIEBOUNDARY_SHIFT		5
99 #define X_EGRPCIEBOUNDARY_32B		0
100 #define X_EGRPCIEBOUNDARY_64B		1
101 #define X_EGRPCIEBOUNDARY_128B		2
102 #define X_EGRPCIEBOUNDARY_256B		3
103 #define X_EGRPCIEBOUNDARY_512B		4
104 #define X_EGRPCIEBOUNDARY_1024B		5
105 #define X_EGRPCIEBOUNDARY_2048B		6
106 #define X_EGRPCIEBOUNDARY_4096B		7
107 
108 /* CONTROL2 register */
109 #define X_INGPACKBOUNDARY_SHIFT		5	// *most* of the values ...
110 #define X_INGPACKBOUNDARY_16B		0	// Note weird value!
111 #define X_INGPACKBOUNDARY_64B		1
112 #define X_INGPACKBOUNDARY_128B		2
113 #define X_INGPACKBOUNDARY_256B		3
114 #define X_INGPACKBOUNDARY_512B		4
115 #define X_INGPACKBOUNDARY_1024B		5
116 #define X_INGPACKBOUNDARY_2048B		6
117 #define X_INGPACKBOUNDARY_4096B		7
118 
119 /* GTS register */
120 #define SGE_TIMERREGS			6
121 #define X_TIMERREG_COUNTER0		0
122 #define X_TIMERREG_COUNTER1		1
123 #define X_TIMERREG_COUNTER2		2
124 #define X_TIMERREG_COUNTER3		3
125 #define X_TIMERREG_COUNTER4		4
126 #define X_TIMERREG_COUNTER5		5
127 #define X_TIMERREG_RESTART_COUNTER	6
128 #define X_TIMERREG_UPDATE_CIDX		7
129 
130 /*
131  * Egress Context field values
132  */
133 #define EC_WR_UNITS			16
134 
135 #define X_FETCHBURSTMIN_SHIFT		4
136 #define X_FETCHBURSTMIN_16B		0
137 #define X_FETCHBURSTMIN_32B		1
138 #define X_FETCHBURSTMIN_64B		2
139 #define X_FETCHBURSTMIN_128B		3
140 
141 /* T6 and later use a single-bit encoding for FetchBurstMin */
142 #define X_FETCHBURSTMIN_SHIFT_T6	6
143 #define X_FETCHBURSTMIN_64B_T6		0
144 #define X_FETCHBURSTMIN_128B_T6		1
145 
146 #define X_FETCHBURSTMAX_SHIFT		6
147 #define X_FETCHBURSTMAX_64B		0
148 #define X_FETCHBURSTMAX_128B		1
149 #define X_FETCHBURSTMAX_256B		2
150 #define X_FETCHBURSTMAX_512B		3
151 
152 #define X_HOSTFCMODE_NONE		0
153 #define X_HOSTFCMODE_INGRESS_QUEUE	1
154 #define X_HOSTFCMODE_STATUS_PAGE	2
155 #define X_HOSTFCMODE_BOTH		3
156 
157 #define X_HOSTFCOWNER_UP		0
158 #define X_HOSTFCOWNER_SGE		1
159 
160 #define X_CIDXFLUSHTHRESH_1		0
161 #define X_CIDXFLUSHTHRESH_2		1
162 #define X_CIDXFLUSHTHRESH_4		2
163 #define X_CIDXFLUSHTHRESH_8		3
164 #define X_CIDXFLUSHTHRESH_16		4
165 #define X_CIDXFLUSHTHRESH_32		5
166 #define X_CIDXFLUSHTHRESH_64		6
167 #define X_CIDXFLUSHTHRESH_128		7
168 
169 #define X_IDXSIZE_UNIT			64
170 
171 #define X_BASEADDRESS_ALIGN		512
172 
173 /*
174  * Ingress Context field values
175  */
176 #define X_UPDATESCHEDULING_TIMER	0
177 #define X_UPDATESCHEDULING_COUNTER_OPTTIMER	1
178 
179 #define X_UPDATEDELIVERY_NONE		0
180 #define X_UPDATEDELIVERY_INTERRUPT	1
181 #define X_UPDATEDELIVERY_STATUS_PAGE	2
182 #define X_UPDATEDELIVERY_BOTH		3
183 
184 #define X_INTERRUPTDESTINATION_PCIE	0
185 #define X_INTERRUPTDESTINATION_IQ	1
186 
187 #define X_QUEUEENTRYSIZE_16B		0
188 #define X_QUEUEENTRYSIZE_32B		1
189 #define X_QUEUEENTRYSIZE_64B		2
190 #define X_QUEUEENTRYSIZE_128B		3
191 
192 #define IC_SIZE_UNIT			16
193 #define IC_BASEADDRESS_ALIGN		512
194 
195 #define X_RSPD_TYPE_FLBUF		0
196 #define X_RSPD_TYPE_CPL			1
197 #define X_RSPD_TYPE_INTR		2
198 
199 /*
200  * Context field definitions.  This is by no means a complete list of SGE
201  * Context fields.  In the vast majority of cases the firmware initializes
202  * things the way they need to be set up.  But in a few small cases, we need
203  * to compute new values and ship them off to the firmware to be applied to
204  * the SGE Conexts ...
205  */
206 
207 /*
208  * Congestion Manager Definitions.
209  */
210 #define S_CONMCTXT_CNGTPMODE		19
211 #define M_CONMCTXT_CNGTPMODE		0x3
212 #define V_CONMCTXT_CNGTPMODE(x)		((x) << S_CONMCTXT_CNGTPMODE)
213 #define G_CONMCTXT_CNGTPMODE(x)  \
214 	(((x) >> S_CONMCTXT_CNGTPMODE) & M_CONMCTXT_CNGTPMODE)
215 #define S_CONMCTXT_CNGCHMAP		0
216 #define M_CONMCTXT_CNGCHMAP		0xffff
217 #define V_CONMCTXT_CNGCHMAP(x)		((x) << S_CONMCTXT_CNGCHMAP)
218 #define G_CONMCTXT_CNGCHMAP(x)   \
219 	(((x) >> S_CONMCTXT_CNGCHMAP) & M_CONMCTXT_CNGCHMAP)
220 
221 #define X_CONMCTXT_CNGTPMODE_DISABLE	0
222 #define X_CONMCTXT_CNGTPMODE_QUEUE	1
223 #define X_CONMCTXT_CNGTPMODE_CHANNEL	2
224 #define X_CONMCTXT_CNGTPMODE_BOTH	3
225 
226 /*
227  * T5 and later support a new BAR2-based doorbell mechanism for Egress Queues.
228  * The User Doorbells are each 128 bytes in length with a Simple Doorbell at
229  * offsets 8x and a Write Combining single 64-byte Egress Queue Unit
230  * (X_IDXSIZE_UNIT) Gather Buffer interface at offset 64.  For Ingress Queues,
231  * we have a Going To Sleep register at offsets 8x+4.
232  *
233  * As noted above, we have many instances of the Simple Doorbell and Going To
234  * Sleep registers at offsets 8x and 8x+4, respectively.  We want to use a
235  * non-64-byte aligned offset for the Simple Doorbell in order to attempt to
236  * avoid buffering of the writes to the Simple Doorbell and we want to use a
237  * non-contiguous offset for the Going To Sleep writes in order to avoid
238  * possible combining between them.
239  */
240 #define SGE_UDB_SIZE		128
241 #define SGE_UDB_KDOORBELL	8
242 #define SGE_UDB_GTS		20
243 #define SGE_UDB_WCDOORBELL	64
244 
245 /*
246  * CIM definitions.
247  * ================
248  */
249 
250 /*
251  * CIM register field values.
252  */
253 #define X_MBOWNER_NONE			0
254 #define X_MBOWNER_FW			1
255 #define X_MBOWNER_PL			2
256 #define X_MBOWNER_FW_DEFERRED		3
257 
258 /*
259  * PCI-E definitions.
260  * ==================
261  */
262 
263 #define X_WINDOW_SHIFT			10
264 #define X_PCIEOFST_SHIFT		10
265 
266 /*
267  * TP definitions.
268  * ===============
269  */
270 
271 /*
272  * TP_VLAN_PRI_MAP controls which subset of fields will be present in the
273  * Compressed Filter Tuple for LE filters.  Each bit set in TP_VLAN_PRI_MAP
274  * selects for a particular field being present.  These fields, when present
275  * in the Compressed Filter Tuple, have the following widths in bits.
276  */
277 #define S_FT_FIRST			S_FCOE
278 #define S_FT_LAST			S_FRAGMENTATION
279 
280 #define W_FT_FCOE			1
281 #define W_FT_PORT			3
282 #define W_FT_VNIC_ID			17
283 #define W_FT_VLAN			17
284 #define W_FT_TOS			8
285 #define W_FT_PROTOCOL			8
286 #define W_FT_ETHERTYPE			16
287 #define W_FT_MACMATCH			9
288 #define W_FT_MPSHITTYPE			3
289 #define W_FT_FRAGMENTATION		1
290 
291 /*
292  * Some of the Compressed Filter Tuple fields have internal structure.  These
293  * bit shifts/masks describe those structures.  All shifts are relative to the
294  * base position of the fields within the Compressed Filter Tuple
295  */
296 #define S_FT_VLAN_VLD			16
297 #define V_FT_VLAN_VLD(x)		((x) << S_FT_VLAN_VLD)
298 #define F_FT_VLAN_VLD			V_FT_VLAN_VLD(1U)
299 
300 #define S_FT_VNID_ID_VF			0
301 #define M_FT_VNID_ID_VF			0x7fU
302 #define V_FT_VNID_ID_VF(x)		((x) << S_FT_VNID_ID_VF)
303 #define G_FT_VNID_ID_VF(x)		(((x) >> S_FT_VNID_ID_VF) & M_FT_VNID_ID_VF)
304 
305 #define S_FT_VNID_ID_PF			7
306 #define M_FT_VNID_ID_PF			0x7U
307 #define V_FT_VNID_ID_PF(x)		((x) << S_FT_VNID_ID_PF)
308 #define G_FT_VNID_ID_PF(x)		(((x) >> S_FT_VNID_ID_PF) & M_FT_VNID_ID_PF)
309 
310 #define S_FT_VNID_ID_VLD		16
311 #define V_FT_VNID_ID_VLD(x)		((x) << S_FT_VNID_ID_VLD)
312 #define F_FT_VNID_ID_VLD(x)		V_FT_VNID_ID_VLD(1U)
313 
314 #endif /* __T4_REGS_VALUES_H__ */
315