1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2011 Chelsio Communications, Inc. 5 * All rights reserved. 6 * Written by: Navdeep Parhar <np@FreeBSD.org> 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 * 29 */ 30 31 #ifndef __T4_IOCTL_H__ 32 #define __T4_IOCTL_H__ 33 34 #include <sys/types.h> 35 #include <net/ethernet.h> 36 #include <net/bpf.h> 37 38 /* 39 * Ioctl commands specific to this driver. 40 */ 41 enum { 42 T4_GETREG = 0x40, /* read register */ 43 T4_SETREG, /* write register */ 44 T4_REGDUMP, /* dump of all registers */ 45 T4_GET_FILTER_MODE, /* get global filter mode */ 46 T4_SET_FILTER_MODE, /* set global filter mode */ 47 T4_GET_FILTER, /* get information about a filter */ 48 T4_SET_FILTER, /* program a filter */ 49 T4_DEL_FILTER, /* delete a filter */ 50 T4_GET_SGE_CONTEXT, /* get SGE context for a queue */ 51 T4_LOAD_FW, /* flash firmware */ 52 T4_GET_MEM, /* read memory */ 53 T4_GET_I2C, /* read from i2c addressible device */ 54 T4_CLEAR_STATS, /* clear a port's MAC statistics */ 55 T4_SET_OFLD_POLICY, /* Set offload policy */ 56 T4_SET_SCHED_CLASS, /* set sched class */ 57 T4_SET_SCHED_QUEUE, /* set queue class */ 58 T4_GET_TRACER, /* get information about a tracer */ 59 T4_SET_TRACER, /* program a tracer */ 60 T4_LOAD_CFG, /* copy a config file to card's flash */ 61 T4_LOAD_BOOT, /* flash boot rom */ 62 T4_LOAD_BOOTCFG, /* flash bootcfg */ 63 T4_CUDBG_DUMP, /* debug dump of chip state */ 64 T4_SET_FILTER_MASK, /* set filter mask (hashfilter mode) */ 65 T4_HOLD_CLIP_ADDR, /* add ref on an IP in the CLIP */ 66 T4_RELEASE_CLIP_ADDR, /* remove ref from an IP in the CLIP */ 67 T4_GET_SGE_CTXT, /* get SGE context for a queue */ 68 }; 69 70 struct t4_reg { 71 uint32_t addr; 72 uint32_t size; 73 uint64_t val; 74 }; 75 76 #define T4_REGDUMP_SIZE (160 * 1024) 77 #define T5_REGDUMP_SIZE (332 * 1024) 78 struct t4_regdump { 79 uint32_t version; 80 uint32_t len; /* bytes */ 81 uint32_t *data; 82 }; 83 84 struct t4_data { 85 uint32_t len; 86 uint8_t *data; 87 }; 88 89 struct t4_bootrom { 90 uint32_t pf_offset; 91 uint32_t pfidx_addr; 92 uint32_t len; 93 uint8_t *data; 94 }; 95 96 struct t4_i2c_data { 97 uint8_t port_id; 98 uint8_t dev_addr; 99 uint8_t offset; 100 uint8_t len; 101 uint8_t data[8]; 102 }; 103 104 /* 105 * A hardware filter is some valid combination of these. 106 */ 107 #define T4_FILTER_IPv4 0x1 /* IPv4 packet */ 108 #define T4_FILTER_IPv6 0x2 /* IPv6 packet */ 109 #define T4_FILTER_IP_SADDR 0x4 /* Source IP address or network */ 110 #define T4_FILTER_IP_DADDR 0x8 /* Destination IP address or network */ 111 #define T4_FILTER_IP_SPORT 0x10 /* Source IP port */ 112 #define T4_FILTER_IP_DPORT 0x20 /* Destination IP port */ 113 #define T4_FILTER_FCoE 0x40 /* Fibre Channel over Ethernet packet */ 114 #define T4_FILTER_PORT 0x80 /* Physical ingress port */ 115 #define T4_FILTER_VNIC 0x100 /* See the IC_* bits towards the end */ 116 #define T4_FILTER_VLAN 0x200 /* VLAN ID */ 117 #define T4_FILTER_IP_TOS 0x400 /* IPv4 TOS/IPv6 Traffic Class */ 118 #define T4_FILTER_IP_PROTO 0x800 /* IP protocol */ 119 #define T4_FILTER_ETH_TYPE 0x1000 /* Ethernet Type */ 120 #define T4_FILTER_MAC_IDX 0x2000 /* MPS MAC address match index */ 121 #define T4_FILTER_MPS_HIT_TYPE 0x4000 /* MPS match type */ 122 #define T4_FILTER_IP_FRAGMENT 0x8000 /* IP fragment */ 123 #define T4_FILTER_IPSECIDX 0x10000 124 #define T4_FILTER_ROCE 0x20000 125 #define T4_FILTER_SYNONLY 0x40000 126 #define T4_FILTER_TCPFLAGS 0x80000 127 /* 128 * T4_FILTER_VNIC's real meaning depends on the ingress config. 129 */ 130 #define T4_FILTER_IC_OVLAN 0 /* outer VLAN */ 131 #define T4_FILTER_IC_VNIC 0x80000000 /* VNIC id (PF/VF) */ 132 #define T4_FILTER_IC_ENCAP 0x40000000 133 134 /* Filter action */ 135 enum { 136 FILTER_PASS = 0, /* default */ 137 FILTER_DROP, 138 FILTER_SWITCH 139 }; 140 141 /* 802.1q manipulation on FILTER_SWITCH */ 142 enum { 143 VLAN_NOCHANGE = 0, /* default */ 144 VLAN_REMOVE, 145 VLAN_INSERT, 146 VLAN_REWRITE 147 }; 148 149 /* MPS match type */ 150 enum { 151 UCAST_EXACT = 0, /* exact unicast match */ 152 UCAST_HASH = 1, /* inexact (hashed) unicast match */ 153 MCAST_EXACT = 2, /* exact multicast match */ 154 MCAST_HASH = 3, /* inexact (hashed) multicast match */ 155 PROMISC = 4, /* no match but port is promiscuous */ 156 HYPPROMISC = 5, /* port is hypervisor-promisuous + not bcast */ 157 BCAST = 6, /* broadcast packet */ 158 }; 159 160 /* Rx steering */ 161 enum { 162 DST_MODE_QUEUE, /* queue is directly specified by filter */ 163 DST_MODE_RSS_QUEUE, /* filter specifies RSS entry containing queue */ 164 DST_MODE_RSS, /* queue selected by default RSS hash lookup */ 165 DST_MODE_FILT_RSS /* queue selected by hashing in filter-specified 166 RSS subtable */ 167 }; 168 169 enum { 170 NAT_MODE_NONE = 0, /* No NAT performed */ 171 NAT_MODE_DIP, /* NAT on Dst IP */ 172 NAT_MODE_DIP_DP, /* NAT on Dst IP, Dst Port */ 173 NAT_MODE_DIP_DP_SIP, /* NAT on Dst IP, Dst Port and Src IP */ 174 NAT_MODE_DIP_DP_SP, /* NAT on Dst IP, Dst Port and Src Port */ 175 NAT_MODE_SIP_SP, /* NAT on Src IP and Src Port */ 176 NAT_MODE_DIP_SIP_SP, /* NAT on Dst IP, Src IP and Src Port */ 177 NAT_MODE_ALL /* NAT on entire 4-tuple */ 178 }; 179 180 struct t4_filter_tuple { 181 /* 182 * These are always available. 183 */ 184 uint8_t sip[16]; /* source IP address (IPv4 in [3:0]) */ 185 uint8_t dip[16]; /* destination IP address (IPv4 in [3:0]) */ 186 uint16_t sport; /* source port */ 187 uint16_t dport; /* destination port */ 188 189 /* 190 * A combination of these (up to 36 bits) is available. TP_VLAN_PRI_MAP 191 * is used to select the global mode and all filters are limited to the 192 * set of fields allowed by the global mode. 193 */ 194 uint16_t vnic; /* VNIC id (PF/VF) or outer VLAN tag */ 195 uint16_t vlan; /* VLAN tag */ 196 uint16_t ethtype; /* Ethernet type */ 197 uint8_t tos; /* TOS/Traffic Type */ 198 uint8_t proto; /* protocol type */ 199 uint32_t fcoe:1; /* FCoE packet */ 200 uint32_t iport:3; /* ingress port */ 201 uint32_t matchtype:3; /* MPS match type */ 202 uint32_t frag:1; /* fragmentation extension header */ 203 uint32_t macidx:9; /* exact match MAC index */ 204 uint32_t vlan_vld:1; /* VLAN valid */ 205 uint32_t ovlan_vld:1; /* outer VLAN tag valid, value in "vnic" */ 206 uint32_t pfvf_vld:1; /* VNIC id (PF/VF) valid, value in "vnic" */ 207 uint32_t roce:1; 208 uint32_t synonly:1; 209 uint32_t tcpflags:6; 210 uint32_t ipsecidx:12; 211 }; 212 213 struct t4_filter_specification { 214 uint32_t hitcnts:1; /* count filter hits in TCB */ 215 uint32_t prio:1; /* filter has priority over active/server */ 216 uint32_t type:1; /* 0 => IPv4, 1 => IPv6 */ 217 uint32_t hash:1; /* 0 => LE TCAM, 1 => Hash */ 218 uint32_t action:2; /* drop, pass, switch */ 219 uint32_t rpttid:1; /* report TID in RSS hash field */ 220 uint32_t dirsteer:1; /* 0 => RSS, 1 => steer to iq */ 221 uint32_t iq:10; /* ingress queue */ 222 uint32_t maskhash:1; /* dirsteer=0: steer to an RSS sub-region */ 223 uint32_t dirsteerhash:1;/* dirsteer=1: 0 => TCB contains RSS hash */ 224 /* 1 => TCB contains IQ ID */ 225 226 /* 227 * Switch proxy/rewrite fields. An ingress packet which matches a 228 * filter with "switch" set will be looped back out as an egress 229 * packet -- potentially with some Ethernet header rewriting. 230 */ 231 uint32_t eport:2; /* egress port to switch packet out */ 232 uint32_t newdmac:1; /* rewrite destination MAC address */ 233 uint32_t newsmac:1; /* rewrite source MAC address */ 234 uint32_t swapmac:1; /* swap SMAC/DMAC for loopback packet */ 235 uint32_t newvlan:2; /* rewrite VLAN Tag */ 236 uint32_t nat_mode:3; /* NAT operation mode */ 237 uint32_t nat_flag_chk:1;/* check TCP flags before NAT'ing */ 238 uint32_t nat_seq_chk; /* sequence value to use for NAT check*/ 239 uint8_t dmac[ETHER_ADDR_LEN]; /* new destination MAC address */ 240 uint8_t smac[ETHER_ADDR_LEN]; /* new source MAC address */ 241 uint16_t vlan; /* VLAN Tag to insert */ 242 243 uint8_t nat_dip[16]; /* destination IP to use after NAT'ing */ 244 uint8_t nat_sip[16]; /* source IP to use after NAT'ing */ 245 uint16_t nat_dport; /* destination port to use after NAT'ing */ 246 uint16_t nat_sport; /* source port to use after NAT'ing */ 247 248 /* 249 * Filter rule value/mask pairs. 250 */ 251 struct t4_filter_tuple val; 252 struct t4_filter_tuple mask; 253 }; 254 255 struct t4_filter { 256 uint32_t idx; 257 uint16_t l2tidx; 258 uint16_t smtidx; 259 uint64_t hits; 260 struct t4_filter_specification fs; 261 }; 262 263 /* Tx Scheduling Class parameters */ 264 struct t4_sched_class_params { 265 int8_t level; /* scheduler hierarchy level */ 266 int8_t mode; /* per-class or per-flow */ 267 int8_t rateunit; /* bit or packet rate */ 268 int8_t ratemode; /* %port relative or kbps absolute */ 269 int8_t channel; /* scheduler channel [0..N] */ 270 int8_t cl; /* scheduler class [0..N] */ 271 int32_t minrate; /* minimum rate */ 272 int32_t maxrate; /* maximum rate */ 273 int16_t weight; /* percent weight */ 274 int16_t pktsize; /* average packet size */ 275 }; 276 277 /* 278 * Support for "sched-class" command to allow a TX Scheduling Class to be 279 * programmed with various parameters. 280 */ 281 struct t4_sched_params { 282 int8_t subcmd; /* sub-command */ 283 int8_t type; /* packet or flow */ 284 union { 285 struct { /* sub-command SCHED_CLASS_CONFIG */ 286 int8_t minmax; /* minmax enable */ 287 } config; 288 struct t4_sched_class_params params; 289 uint8_t reserved[6 + 8 * 8]; 290 } u; 291 }; 292 293 enum { 294 SCHED_CLASS_SUBCMD_CONFIG, /* config sub-command */ 295 SCHED_CLASS_SUBCMD_PARAMS, /* params sub-command */ 296 }; 297 298 enum { 299 SCHED_CLASS_TYPE_PACKET, 300 }; 301 302 enum { 303 SCHED_CLASS_LEVEL_CL_RL, /* class rate limiter */ 304 SCHED_CLASS_LEVEL_CL_WRR, /* class weighted round robin */ 305 SCHED_CLASS_LEVEL_CH_RL, /* channel rate limiter */ 306 }; 307 308 enum { 309 SCHED_CLASS_MODE_CLASS, /* per-class scheduling */ 310 SCHED_CLASS_MODE_FLOW, /* per-flow scheduling */ 311 }; 312 313 enum { 314 SCHED_CLASS_RATEUNIT_BITS, /* bit rate scheduling */ 315 SCHED_CLASS_RATEUNIT_PKTS, /* packet rate scheduling */ 316 }; 317 318 enum { 319 SCHED_CLASS_RATEMODE_REL, /* percent of port bandwidth */ 320 SCHED_CLASS_RATEMODE_ABS, /* Kb/s */ 321 }; 322 323 /* 324 * Support for "sched_queue" command to allow one or more NIC TX Queues to be 325 * bound to a TX Scheduling Class. 326 */ 327 struct t4_sched_queue { 328 uint8_t port; 329 int8_t queue; /* queue index; -1 => all queues */ 330 int8_t cl; /* class index; -1 => unbind */ 331 }; 332 333 #define T4_SGE_CONTEXT_SIZE 24 334 #define T7_SGE_CONTEXT_SIZE 28 335 enum { 336 SGE_CONTEXT_EGRESS, 337 SGE_CONTEXT_INGRESS, 338 SGE_CONTEXT_FLM, 339 SGE_CONTEXT_CNM 340 }; 341 342 struct t4_sge_context { 343 uint32_t mem_id; 344 uint32_t cid; 345 uint32_t data[T4_SGE_CONTEXT_SIZE / 4]; 346 }; 347 348 struct t4_sge_ctxt { 349 uint32_t mem_id; 350 uint32_t cid; 351 uint32_t data[T7_SGE_CONTEXT_SIZE / 4]; 352 }; 353 354 struct t4_mem_range { 355 uint32_t addr; 356 uint32_t len; 357 uint32_t *data; 358 }; 359 360 #define T4_TRACE_LEN 112 361 struct t4_trace_params { 362 uint32_t data[T4_TRACE_LEN / 4]; 363 uint32_t mask[T4_TRACE_LEN / 4]; 364 uint16_t snap_len; 365 uint16_t min_len; 366 uint8_t skip_ofst; 367 uint8_t skip_len; 368 uint8_t invert; 369 uint8_t port; 370 }; 371 372 struct t4_tracer { 373 uint8_t idx; 374 uint8_t enabled; 375 uint8_t valid; 376 struct t4_trace_params tp; 377 }; 378 379 struct t4_cudbg_dump { 380 uint8_t wr_flash; 381 uint8_t bitmap[16]; 382 uint32_t len; 383 uint8_t *data; 384 }; 385 386 enum { 387 OPEN_TYPE_LISTEN = 'L', 388 OPEN_TYPE_ACTIVE = 'A', 389 OPEN_TYPE_PASSIVE = 'P', 390 OPEN_TYPE_DONTCARE = 'D', 391 }; 392 393 enum { 394 QUEUE_RANDOM = -1, 395 QUEUE_ROUNDROBIN = -2, 396 }; 397 398 struct offload_settings { 399 int8_t offload; 400 int8_t rx_coalesce; 401 int8_t cong_algo; 402 int8_t sched_class; 403 int8_t tstamp; 404 int8_t sack; 405 int8_t nagle; 406 int8_t ecn; 407 int8_t ddp; 408 int8_t tls; 409 int16_t txq; 410 int16_t rxq; 411 int16_t mss; 412 }; 413 414 struct offload_rule { 415 char open_type; 416 struct offload_settings settings; 417 struct bpf_program bpf_prog; /* compiled program/filter */ 418 }; 419 420 /* 421 * An offload policy consists of a set of rules matched in sequence. The 422 * settings of the first rule that matches are applied to that connection. 423 */ 424 struct t4_offload_policy { 425 uint32_t nrules; 426 struct offload_rule *rule; 427 }; 428 429 /* Address/mask entry in the CLIP. FW_CLIP2_CMD is aware of the mask. */ 430 struct t4_clip_addr { 431 uint8_t addr[16]; 432 uint8_t mask[16]; 433 }; 434 435 #define CHELSIO_T4_GETREG _IOWR('f', T4_GETREG, struct t4_reg) 436 #define CHELSIO_T4_SETREG _IOW('f', T4_SETREG, struct t4_reg) 437 #define CHELSIO_T4_REGDUMP _IOWR('f', T4_REGDUMP, struct t4_regdump) 438 #define CHELSIO_T4_GET_FILTER_MODE _IOWR('f', T4_GET_FILTER_MODE, uint32_t) 439 #define CHELSIO_T4_SET_FILTER_MODE _IOW('f', T4_SET_FILTER_MODE, uint32_t) 440 #define CHELSIO_T4_GET_FILTER _IOWR('f', T4_GET_FILTER, struct t4_filter) 441 #define CHELSIO_T4_SET_FILTER _IOWR('f', T4_SET_FILTER, struct t4_filter) 442 #define CHELSIO_T4_DEL_FILTER _IOW('f', T4_DEL_FILTER, struct t4_filter) 443 #define CHELSIO_T4_GET_SGE_CONTEXT _IOWR('f', T4_GET_SGE_CONTEXT, \ 444 struct t4_sge_context) 445 #define CHELSIO_T4_LOAD_FW _IOW('f', T4_LOAD_FW, struct t4_data) 446 #define CHELSIO_T4_GET_MEM _IOW('f', T4_GET_MEM, struct t4_mem_range) 447 #define CHELSIO_T4_GET_I2C _IOWR('f', T4_GET_I2C, struct t4_i2c_data) 448 #define CHELSIO_T4_CLEAR_STATS _IOW('f', T4_CLEAR_STATS, uint32_t) 449 #define CHELSIO_T4_SCHED_CLASS _IOW('f', T4_SET_SCHED_CLASS, \ 450 struct t4_sched_params) 451 #define CHELSIO_T4_SCHED_QUEUE _IOW('f', T4_SET_SCHED_QUEUE, \ 452 struct t4_sched_queue) 453 #define CHELSIO_T4_GET_TRACER _IOWR('f', T4_GET_TRACER, struct t4_tracer) 454 #define CHELSIO_T4_SET_TRACER _IOW('f', T4_SET_TRACER, struct t4_tracer) 455 #define CHELSIO_T4_LOAD_CFG _IOW('f', T4_LOAD_CFG, struct t4_data) 456 #define CHELSIO_T4_LOAD_BOOT _IOW('f', T4_LOAD_BOOT, struct t4_bootrom) 457 #define CHELSIO_T4_LOAD_BOOTCFG _IOW('f', T4_LOAD_BOOTCFG, struct t4_data) 458 #define CHELSIO_T4_CUDBG_DUMP _IOWR('f', T4_CUDBG_DUMP, struct t4_cudbg_dump) 459 #define CHELSIO_T4_SET_OFLD_POLICY _IOW('f', T4_SET_OFLD_POLICY, struct t4_offload_policy) 460 #define CHELSIO_T4_SET_FILTER_MASK _IOW('f', T4_SET_FILTER_MASK, uint32_t) 461 #define CHELSIO_T4_HOLD_CLIP_ADDR _IOW('f', T4_HOLD_CLIP_ADDR, struct t4_clip_addr) 462 #define CHELSIO_T4_RELEASE_CLIP_ADDR _IOW('f', T4_RELEASE_CLIP_ADDR, struct t4_clip_addr) 463 #define CHELSIO_T4_GET_SGE_CTXT _IOWR('f', T4_GET_SGE_CTXT, struct t4_sge_ctxt) 464 #endif 465