xref: /illumos-gate/usr/src/uts/common/sys/sata/adapters/ahci/ahcireg.h (revision 33b27906b01ade9752c1935377f3fefdf49b8f95)
1 /*
2  * CDDL HEADER START
3  *
4  * The contents of this file are subject to the terms of the
5  * Common Development and Distribution License (the "License").
6  * You may not use this file except in compliance with the License.
7  *
8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9  * or http://www.opensolaris.org/os/licensing.
10  * See the License for the specific language governing permissions
11  * and limitations under the License.
12  *
13  * When distributing Covered Code, include this CDDL HEADER in each
14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15  * If applicable, add the following below this CDDL HEADER, with the
16  * fields enclosed by brackets "[]" replaced with your own identifying
17  * information: Portions Copyright [yyyy] [name of copyright owner]
18  *
19  * CDDL HEADER END
20  */
21 
22 /*
23  * Copyright 2009 Sun Microsystems, Inc.  All rights reserved.
24  * Use is subject to license terms.
25  */
26 /*
27  * Copyright 2013 Nexenta Systems, Inc.  All rights reserved.
28  * Copyright 2021 RackTop Systems, Inc.
29  */
30 
31 #ifndef _AHCIREG_H
32 #define	_AHCIREG_H
33 
34 #ifdef	__cplusplus
35 extern "C" {
36 #endif
37 
38 #define	AHCI_MAX_PORTS		32
39 #define	AHCI_PORT_MAX_CMD_SLOTS	32
40 
41 #define	VIA_VENID		0x1106
42 
43 /*
44  * In AHCI spec, command table contains a list of 0 (no data transfer)
45  * to up to 65,535 scatter/gather entries for the data transfer.
46  */
47 #define	AHCI_MAX_PRDT_NUMBER	65535
48 #define	AHCI_MIN_PRDT_NUMBER	1
49 
50 /*
51  * The default value of s/g entrie is 257, at least 1MB (4KB/pg * 256) + 1
52  * if misaligned, and it's tuable by setting ahci_dma_prdt_number in
53  * /etc/system file.
54  */
55 #define	AHCI_PRDT_NUMBER	257
56 
57 /* PCI header offset for AHCI Base Address */
58 #define	AHCI_PCI_RNUM		0x24
59 
60 /* various global HBA capability bits */
61 #define	AHCI_HBA_CAP_NP		(0x1f << 0) /* number of ports */
62 #define	AHCI_HBA_CAP_SXS	(0x1 << 5) /* external SATA */
63 #define	AHCI_HBA_CAP_EMS	(0x1 << 6) /* enclosure management */
64 #define	AHCI_HBA_CAP_CCCS	(0x1 << 7) /* command completed coalescing */
65 #define	AHCI_HBA_CAP_NCS	(0x1f << 8) /* number of command slots */
66 #define	AHCI_HBA_CAP_PSC	(0x1 << 13) /* partial state capable */
67 #define	AHCI_HBA_CAP_SSC	(0x1 << 14) /* slumber state capable */
68 #define	AHCI_HBA_CAP_PMD	(0x1 << 15) /* PIO multiple DRQ block */
69 #define	AHCI_HBA_CAP_FBSS	(0x1 << 16) /* FIS-based switching */
70 #define	AHCI_HBA_CAP_SPM	(0x1 << 17) /* port multiplier */
71 #define	AHCI_HBA_CAP_SAM	(0x1 << 18) /* AHCI mode only */
72 #define	AHCI_HBA_CAP_ISS	(0xf << 20) /* interface speed support */
73 #define	AHCI_HBA_CAP_SCLO	(0x1 << 24) /* command list override */
74 #define	AHCI_HBA_CAP_SAL	(0x1 << 25) /* activity LED */
75 #define	AHCI_HBA_CAP_SALP	(0x1 << 26) /* aggressive link power mgmt */
76 #define	AHCI_HBA_CAP_SSS	(0x1 << 27) /* staggered  spin-up */
77 #define	AHCI_HBA_CAP_SMPS	(0x1 << 28) /* mechanical presence switch */
78 #define	AHCI_HBA_CAP_SSNTF	(0x1 << 29) /* Snotification register */
79 #define	AHCI_HBA_CAP_SNCQ	(0x1 << 30) /* Native Command Queuing */
80 #define	AHCI_HBA_CAP_S64A	((uint32_t)0x1 << 31) /* 64-bit addressing */
81 #define	AHCI_HBA_CAP_NCS_SHIFT	8  /* Number of command slots */
82 #define	AHCI_HBA_CAP_ISS_SHIFT	20 /* Interface speed support */
83 
84 /* various global HBA control bits */
85 #define	AHCI_HBA_GHC_HR		(0x1 << 0) /* HBA Reset */
86 #define	AHCI_HBA_GHC_IE		(0x1 << 1) /* Interrupt Enable */
87 #define	AHCI_HBA_GHC_MRSM	(0x1 << 2) /* MSI Revert to Single Message */
88 #define	AHCI_HBA_GHC_AE		((uint32_t)0x1 << 31) /* AHCI Enable */
89 
90 /* various global HBA Command Completion Coalescing (CCC) control bits */
91 #define	AHCI_HBA_CCC_CTL_EN		0x00000001  /* Enable */
92 #define	AHCI_HBA_CCC_CTL_INT_MASK	(0x1f << 3) /* Interrupt */
93 #define	AHCI_HBA_CCC_CTL_CC_MASK	0x0000ff00  /* Command Completions */
94 #define	AHCI_HBA_CCC_CTL_TV_MASK	0xffff0000  /* Timeout Value */
95 #define	AHCI_HBA_CCC_CTL_INT_SHIFT	3
96 #define	AHCI_HBA_CCC_CTL_CC_SHIFT	8
97 #define	AHCI_HBA_CCC_CTL_TV_SHIFT	16
98 
99 /* global HBA Enclosure Management Location (EM_LOC) */
100 #define	AHCI_HBA_EM_LOC_SZ_MASK		0x0000ffff /* Buffer Size */
101 #define	AHCI_HBA_EM_LOC_OFST_MASK	0xffff0000 /* Offset */
102 #define	AHCI_HBA_EM_LOC_OFST_SHIFT	16
103 
104 /* global HBA Enclosure Management Control (EM_CTL) bits */
105 #define	AHCI_HBA_EM_CTL_STS_MR		(0x1 << 0) /* Message Received */
106 #define	AHCI_HBA_EM_CTL_CTL_TM		(0x1 << 8) /* Transmit Message */
107 #define	AHCI_HBA_EM_CTL_CTL_RST		(0x1 << 9) /* Reset */
108 #define	AHCI_HBA_EM_CTL_SUPP_LED	(0x1 << 16) /* LED Message Types */
109 #define	AHCI_HBA_EM_CTL_SUPP_SAFTE	(0x1 << 17) /* SAF-TE EM Messages */
110 #define	AHCI_HBA_EM_CTL_SUPP_SES2	(0x1 << 18) /* SES-2 EM Messages */
111 #define	AHCI_HBA_EM_CTL_SUPP_SGPIO	(0x1 << 19) /* SGPIO EM Messages */
112 #define	AHCI_HBA_EM_CTL_ATTR_SMB	(0x1 << 24) /* Single Message Buffer */
113 #define	AHCI_HBA_EM_CTL_ATTR_XMT	(0x1 << 25) /* Transmit Only */
114 #define	AHCI_HBA_EM_CTL_ATTR_ALHD	(0x1 << 26) /* Activity LED HW Driven */
115 #define	AHCI_HBA_EM_CTL_ATTR_PM		(0x1 << 27) /* PM Support */
116 
117 #define	AHCI_HBA_CAP2_BOH	(0x1 << 0) /* BIOS/OS Handoff */
118 #define	AHCI_HBA_CAP2_NVMP	(0x1 << 1) /* NVMHCI present */
119 #define	AHCI_HBA_CAP2_APST	(0x1 << 2) /* Auto Partial to Slumber */
120 #define	AHCI_HBA_CAP2_SDS	(0x1 << 3) /* Device Sleep */
121 #define	AHCI_HBA_CAP2_SADM	(0x1 << 4) /* Aggressive Dev Sleep Mgmt */
122 #define	AHCI_HBA_CAP2_DESO	(0x1 << 5) /* DevSleep from Slumber Only */
123 
124 /* global HBA registers definitions */
125 #define	AHCI_GLOBAL_OFFSET(ahci_ctlp)	(ahci_ctlp->ahcictl_ahci_addr)
126 	/* HBA Capabilities */
127 #define	AHCI_GLOBAL_CAP(ahci_ctlp)	(AHCI_GLOBAL_OFFSET(ahci_ctlp) + 0x00)
128 	/* Global HBA Control */
129 #define	AHCI_GLOBAL_GHC(ahci_ctlp)	(AHCI_GLOBAL_OFFSET(ahci_ctlp) + 0x04)
130 	/* Interrupt Status Register */
131 #define	AHCI_GLOBAL_IS(ahci_ctlp)	(AHCI_GLOBAL_OFFSET(ahci_ctlp) + 0x08)
132 	/* Ports Implemented */
133 #define	AHCI_GLOBAL_PI(ahci_ctlp)	(AHCI_GLOBAL_OFFSET(ahci_ctlp) + 0x0c)
134 	/* AHCI Version */
135 #define	AHCI_GLOBAL_VS(ahci_ctlp)	(AHCI_GLOBAL_OFFSET(ahci_ctlp) + 0x10)
136 	/* Command Completion Coalescing Control */
137 #define	AHCI_GLOBAL_CCC_CTL(ahci_ctlp)	(AHCI_GLOBAL_OFFSET(ahci_ctlp) + 0x14)
138 	/* Command Completion Coalescing Ports */
139 #define	AHCI_GLOBAL_CCC_PORTS(ahci_ctlp)	\
140 					(AHCI_GLOBAL_OFFSET(ahci_ctlp) + 0x18)
141 	/* Enclosure Management Location */
142 #define	AHCI_GLOBAL_EM_LOC(ahci_ctlp)	(AHCI_GLOBAL_OFFSET(ahci_ctlp) + 0x1c)
143 	/* Enclosure Management Control */
144 #define	AHCI_GLOBAL_EM_CTL(ahci_ctlp)	(AHCI_GLOBAL_OFFSET(ahci_ctlp) + 0x20)
145 	/* HBA Capabilities Extended (AHCI spec 1.2) */
146 #define	AHCI_GLOBAL_CAP2(ahci_ctlp)	(AHCI_GLOBAL_OFFSET(ahci_ctlp) + 0x24)
147 	/* BIOS/OS Handoff Control and Status (AHCI spec 1.2) */
148 #define	AHCI_GLOBAL_BOHC(ahci_ctlp)	(AHCI_GLOBAL_OFFSET(ahci_ctlp) + 0x28)
149 
150 #define	AHCI_PORT_IMPLEMENTED(ahci_ctlp, port)	\
151 	((0x1 << port) & ahci_ctlp->ahcictl_ports_implemented)
152 
153 /* various port interrupt bits */
154 	/* Device to Host Register FIS Interrupt */
155 #define	AHCI_INTR_STATUS_DHRS (0x1 << 0)
156 	/* PIO Setup FIS Interrupt */
157 #define	AHCI_INTR_STATUS_PSS			(0x1 << 1)
158 	/* DMA Setup FIS Interrupt */
159 #define	AHCI_INTR_STATUS_DSS			(0x1 << 2)
160 	/* Set Device Bits Interrupt */
161 #define	AHCI_INTR_STATUS_SDBS			(0x1 << 3)
162 	/* Unknown FIS Interrupt */
163 #define	AHCI_INTR_STATUS_UFS			(0x1 << 4)
164 	/* Descriptor Processed */
165 #define	AHCI_INTR_STATUS_DPS			(0x1 << 5)
166 	/* Port Connect Change Status */
167 #define	AHCI_INTR_STATUS_PCS			(0x1 << 6)
168 	/* Device Mechanical Presence Status */
169 #define	AHCI_INTR_STATUS_DMPS			(0x1 << 7)
170 	/* PhyRdy Change Status */
171 #define	AHCI_INTR_STATUS_PRCS			(0x1 << 22)
172 	/* Incorrect Port Multiplier Status */
173 #define	AHCI_INTR_STATUS_IPMS			(0x1 << 23)
174 	/* Overflow Status */
175 #define	AHCI_INTR_STATUS_OFS			(0x1 << 24)
176 	/* Interface Non-fatal Error Status */
177 #define	AHCI_INTR_STATUS_INFS			(0x1 << 26)
178 	/* Interface Fatal Error Status */
179 #define	AHCI_INTR_STATUS_IFS			(0x1 << 27)
180 	/* Host Bus Data Error Status */
181 #define	AHCI_INTR_STATUS_HBDS			(0x1 << 28)
182 	/* Host Bus Fatal Error Status */
183 #define	AHCI_INTR_STATUS_HBFS			(0x1 << 29)
184 	/* Task File Error Status */
185 #define	AHCI_INTR_STATUS_TFES			(0x1 << 30)
186 	/* Cold Port Detect Status */
187 #define	AHCI_INTR_STATUS_CPDS			((uint32_t)0x1 << 31)
188 #define	AHCI_PORT_INTR_MASK			0xfec000ff
189 
190 /* port command and status bits */
191 #define	AHCI_CMD_STATUS_ST	(0x1 << 0) /* Start */
192 #define	AHCI_CMD_STATUS_SUD	(0x1 << 1) /* Spin-up device */
193 #define	AHCI_CMD_STATUS_POD	(0x1 << 2) /* Power on device */
194 #define	AHCI_CMD_STATUS_CLO	(0x1 << 3) /* Command list override */
195 #define	AHCI_CMD_STATUS_FRE	(0x1 << 4) /* FIS receive enable */
196 #define	AHCI_CMD_STATUS_CCS	(0x1f << 8) /* Current command slot */
197 			/* Mechanical presence switch state */
198 #define	AHCI_CMD_STATUS_MPSS	(0x1 << 13)
199 #define	AHCI_CMD_STATUS_FR	(0x1 << 14) /* FIS receiving running */
200 #define	AHCI_CMD_STATUS_CR	(0x1 << 15) /* Command list running */
201 #define	AHCI_CMD_STATUS_CPS	(0x1 << 16) /* Cold presence state */
202 #define	AHCI_CMD_STATUS_PMA	(0x1 << 17) /* Port multiplier attached */
203 #define	AHCI_CMD_STATUS_HPCP	(0x1 << 18) /* Hot plug capable port */
204 			/* Mechanical presence switch attached to port */
205 #define	AHCI_CMD_STATUS_MPSP	(0x1 << 19)
206 #define	AHCI_CMD_STATUS_CPD	(0x1 << 20) /* Cold presence detection */
207 #define	AHCI_CMD_STATUS_ESP	(0x1 << 21) /* External SATA port */
208 #define	AHCI_CMD_STATUS_ATAPI	(0x1 << 24) /* Device is ATAPI */
209 #define	AHCI_CMD_STATUS_DLAE	(0x1 << 25) /* Drive LED on ATAPI enable */
210 			/* Aggressive link power magament enable */
211 #define	AHCI_CMD_STATUS_ALPE	(0x1 << 26)
212 #define	AHCI_CMD_STATUS_ASP	(0x1 << 27) /* Aggressive slumber/partial */
213 			/* Interface communication control */
214 #define	AHCI_CMD_STATUS_ICC	(0xf << 28)
215 #define	AHCI_CMD_STATUS_CCS_SHIFT	8
216 #define	AHCI_CMD_STATUS_ICC_SHIFT	28
217 
218 /* port task file data bits */
219 #define	AHCI_TFD_STS_MASK	0x000000ff
220 #define	AHCI_TFD_ERR_MASK	0x0000ff00
221 #define	AHCI_TFD_STS_BSY	(0x1 << 7)
222 #define	AHCI_TFD_STS_DRQ	(0x1 << 3)
223 #define	AHCI_TFD_STS_ERR	(0x1 << 0)
224 #define	AHCI_TFD_ERR_SHIFT	8
225 #define	AHCI_TFD_ERR_SGS	(0x1 << 0) /* DDR1: Send_good_status */
226 
227 /* FIS-Based Switching Control Register */
228 #define	AHCI_FBS_SWE_MASK	(0xf << 16)	/* Device With Error */
229 #define	AHCI_FBS_ADO_MASK	(0xf << 12)	/* Active Device Optimization */
230 #define	AHCI_FBS_DEV_MASK	(0xf << 8)	/* Device To Issue */
231 #define	AHCI_FBS_SDE		(0x1 << 2)	/* Single Device Error */
232 #define	AHCI_FBS_DEC		(0x1 << 1)	/* Device Error Clear */
233 #define	AHCI_FBS_EN		(0x1 << 0)	/* Enable */
234 
235 /* Sxxx Registers */
236 #define	AHCI_SERROR_CLEAR_ALL			0xffffffff
237 #define	AHCI_SNOTIF_CLEAR_ALL			0xffffffff
238 
239 /* per port registers offset */
240 #define	AHCI_PORT_OFFSET(ahci_ctlp, port)			\
241 		(ahci_ctlp->ahcictl_ahci_addr + (0x100 + (port * 0x80)))
242 	/* Command List Base Address */
243 #define	AHCI_PORT_PxCLB(ahci_ctlp, port)			\
244 			(AHCI_PORT_OFFSET(ahci_ctlp, port) + 0x00)
245 	/* Command List Base Address Upper 32-Bits */
246 #define	AHCI_PORT_PxCLBU(ahci_ctlp, port)			\
247 			(AHCI_PORT_OFFSET(ahci_ctlp, port) + 0x04)
248 	/* FIS Base Address */
249 #define	AHCI_PORT_PxFB(ahci_ctlp, port)				\
250 			(AHCI_PORT_OFFSET(ahci_ctlp, port) + 0x08)
251 	/* FIS Base Address Upper 32-Bits */
252 #define	AHCI_PORT_PxFBU(ahci_ctlp, port)			\
253 			(AHCI_PORT_OFFSET(ahci_ctlp, port) + 0x0c)
254 	/* Interrupt Status */
255 #define	AHCI_PORT_PxIS(ahci_ctlp, port)				\
256 			(AHCI_PORT_OFFSET(ahci_ctlp, port) + 0x10)
257 	/* Interrupt Enable */
258 #define	AHCI_PORT_PxIE(ahci_ctlp, port)				\
259 			(AHCI_PORT_OFFSET(ahci_ctlp, port) + 0x14)
260 	/* Command and Status */
261 #define	AHCI_PORT_PxCMD(ahci_ctlp, port)			\
262 			(AHCI_PORT_OFFSET(ahci_ctlp, port) + 0x18)
263 	/* Task File Data */
264 #define	AHCI_PORT_PxTFD(ahci_ctlp, port)			\
265 			(AHCI_PORT_OFFSET(ahci_ctlp, port) + 0x20)
266 	/* Signature */
267 #define	AHCI_PORT_PxSIG(ahci_ctlp, port)			\
268 			(AHCI_PORT_OFFSET(ahci_ctlp, port) + 0x24)
269 	/* Serial ATA Status (SCR0:SStatus) */
270 #define	AHCI_PORT_PxSSTS(ahci_ctlp, port)			\
271 			(AHCI_PORT_OFFSET(ahci_ctlp, port) + 0x28)
272 	/* Serial ATA Control (SCR2:SControl) */
273 #define	AHCI_PORT_PxSCTL(ahci_ctlp, port)			\
274 			(AHCI_PORT_OFFSET(ahci_ctlp, port) + 0x2c)
275 	/* Serial ATA Error (SCR1:SError) */
276 #define	AHCI_PORT_PxSERR(ahci_ctlp, port)			\
277 			(AHCI_PORT_OFFSET(ahci_ctlp, port) + 0x30)
278 	/* Serial ATA Active (SCR3:SActive) */
279 #define	AHCI_PORT_PxSACT(ahci_ctlp, port)			\
280 			(AHCI_PORT_OFFSET(ahci_ctlp, port) + 0x34)
281 	/* Command Issue */
282 #define	AHCI_PORT_PxCI(ahci_ctlp, port)				\
283 			(AHCI_PORT_OFFSET(ahci_ctlp, port) + 0x38)
284 	/* SNotification */
285 #define	AHCI_PORT_PxSNTF(ahci_ctlp, port)			\
286 			(AHCI_PORT_OFFSET(ahci_ctlp, port) + 0x3c)
287 	/* FIS-Based Switching Control */
288 #define	AHCI_PORT_PxFBS(ahci_ctlp, port)			\
289 			(AHCI_PORT_OFFSET(ahci_ctlp, port) + 0x40)
290 
291 #define	AHCI_SLOT_MASK(ahci_ctlp)				\
292 	((ahci_ctlp->ahcictl_num_cmd_slots == AHCI_PORT_MAX_CMD_SLOTS) ? \
293 	0xffffffff : ((0x1 << ahci_ctlp->ahcictl_num_cmd_slots) - 1))
294 #define	AHCI_NCQ_SLOT_MASK(ahci_portp)				\
295 	((ahci_portp->ahciport_max_ncq_tags == AHCI_PORT_MAX_CMD_SLOTS) ? \
296 	0xffffffff : ((0x1 << ahci_portp->ahciport_max_ncq_tags) - 1))
297 #define	AHCI_PMPORT_MASK(ahci_portp)				\
298 	((0x1 << ahci_portp->ahciport_pmult_info->ahcipmi_num_dev_ports) - 1)
299 
300 /* Device signatures */
301 #define	AHCI_SIGNATURE_PORT_MULTIPLIER	0x96690101
302 #define	AHCI_SIGNATURE_ATAPI		0xeb140101
303 #define	AHCI_SIGNATURE_DISK		0x00000101
304 
305 #define	AHCI_H2D_REGISTER_FIS_TYPE	0x27
306 #define	AHCI_H2D_REGISTER_FIS_LENGTH	5
307 
308 #define	AHCI_CMDHEAD_ATAPI	0x1 /* set to 1 for ATAPI command */
309 #define	AHCI_CMDHEAD_DATA_WRITE	0x1 /* From system memory to device */
310 #define	AHCI_CMDHEAD_DATA_READ	0x0 /* From device to system memory */
311 #define	AHCI_CMDHEAD_PREFETCHABLE	0x1 /* if set, HBA prefetch PRDs */
312 
313 /* Register - Host to Device FIS (from SATA spec) */
314 typedef struct ahci_fis_h2d_register {
315 	/* offset 0x00 */
316 	uint32_t	ahcifhr_type_pmp_rsvd_cmddevctl_cmd_features;
317 
318 #define	SET_FIS_TYPE(fis, type)					\
319 	(fis->ahcifhr_type_pmp_rsvd_cmddevctl_cmd_features |= (type & 0xff))
320 
321 #define	SET_FIS_PMP(fis, pmp)					\
322 	(fis->ahcifhr_type_pmp_rsvd_cmddevctl_cmd_features |=	\
323 		((pmp & 0xf) << 8))
324 
325 #define	SET_FIS_CDMDEVCTL(fis, cmddevctl)			\
326 	(fis->ahcifhr_type_pmp_rsvd_cmddevctl_cmd_features |=	\
327 		((cmddevctl & 0x1) << 15))
328 
329 #define	GET_FIS_COMMAND(fis)					\
330 	((fis->ahcifhr_type_pmp_rsvd_cmddevctl_cmd_features >> 16) & 0xff)
331 
332 #define	SET_FIS_COMMAND(fis, command)				\
333 	(fis->ahcifhr_type_pmp_rsvd_cmddevctl_cmd_features |=	\
334 		((command & 0xff) << 16))
335 
336 #define	GET_FIS_FEATURES(fis)					\
337 	((fis->ahcifhr_type_pmp_rsvd_cmddevctl_cmd_features >> 24) & 0xff)
338 
339 #define	SET_FIS_FEATURES(fis, features)				\
340 	(fis->ahcifhr_type_pmp_rsvd_cmddevctl_cmd_features |=	\
341 		((features & 0xff) << 24))
342 
343 	/* offset 0x04 */
344 	uint32_t	ahcifhr_sector_cyllow_cylhi_devhead;
345 
346 #define	GET_FIS_SECTOR(fis)					\
347 	(fis->ahcifhr_sector_cyllow_cylhi_devhead & 0xff)
348 
349 #define	SET_FIS_SECTOR(fis, sector)				\
350 	(fis->ahcifhr_sector_cyllow_cylhi_devhead |= ((sector & 0xff)))
351 
352 #define	GET_FIS_CYL_LOW(fis)					\
353 	((fis->ahcifhr_sector_cyllow_cylhi_devhead >> 8) & 0xff)
354 
355 #define	SET_FIS_CYL_LOW(fis, cyl_low)				\
356 	(fis->ahcifhr_sector_cyllow_cylhi_devhead |= ((cyl_low & 0xff) << 8))
357 
358 #define	GET_FIS_CYL_HI(fis)					\
359 	((fis->ahcifhr_sector_cyllow_cylhi_devhead >> 16) & 0xff)
360 
361 #define	SET_FIS_CYL_HI(fis, cyl_hi)				\
362 	(fis->ahcifhr_sector_cyllow_cylhi_devhead |= ((cyl_hi & 0xff) << 16))
363 
364 #define	GET_FIS_DEV_HEAD(fis)					\
365 	((fis->ahcifhr_sector_cyllow_cylhi_devhead >> 24) & 0xff)
366 
367 #define	SET_FIS_DEV_HEAD(fis, dev_head)				\
368 	(fis->ahcifhr_sector_cyllow_cylhi_devhead |= ((dev_head & 0xff) << 24))
369 
370 	/* offset 0x08 */
371 	uint32_t	ahcifhr_sectexp_cyllowexp_cylhiexp_featuresexp;
372 
373 #define	GET_FIS_SECTOR_EXP(fis)					\
374 	(fis->ahcifhr_sectexp_cyllowexp_cylhiexp_featuresexp  & 0xff)
375 
376 #define	SET_FIS_SECTOR_EXP(fis, sectorexp)			\
377 	(fis->ahcifhr_sectexp_cyllowexp_cylhiexp_featuresexp |=	\
378 		((sectorexp & 0xff)))
379 
380 #define	GET_FIS_CYL_LOW_EXP(fis)				\
381 	((fis->ahcifhr_sectexp_cyllowexp_cylhiexp_featuresexp >> 8) & 0xff)
382 
383 #define	SET_FIS_CYL_LOW_EXP(fis, cyllowexp)			\
384 	(fis->ahcifhr_sectexp_cyllowexp_cylhiexp_featuresexp |=	\
385 		((cyllowexp & 0xff) << 8))
386 
387 #define	GET_FIS_CYL_HI_EXP(fis)					\
388 	((fis->ahcifhr_sectexp_cyllowexp_cylhiexp_featuresexp >> 16) & 0xff)
389 
390 #define	SET_FIS_CYL_HI_EXP(fis, cylhiexp)			\
391 	(fis->ahcifhr_sectexp_cyllowexp_cylhiexp_featuresexp |=	\
392 		((cylhiexp & 0xff) << 16))
393 
394 #define	SET_FIS_FEATURES_EXP(fis, features_exp)			\
395 	(fis->ahcifhr_sectexp_cyllowexp_cylhiexp_featuresexp |=	\
396 		((features_exp & 0xff) << 24))
397 
398 	/* offset 0x0c */
399 	uint32_t	ahcifhr_sectcount_sectcountexp_rsvd_devctl;
400 
401 #define	GET_FIS_SECTOR_COUNT(fis)				\
402 	(fis->ahcifhr_sectcount_sectcountexp_rsvd_devctl & 0xff)
403 
404 #define	SET_FIS_SECTOR_COUNT(fis, sector_count)			\
405 	(fis->ahcifhr_sectcount_sectcountexp_rsvd_devctl |=	\
406 		((sector_count & 0xff)))
407 
408 #define	GET_FIS_SECTOR_COUNT_EXP(fis)				\
409 	((fis->ahcifhr_sectcount_sectcountexp_rsvd_devctl >> 8) & 0xff)
410 
411 #define	SET_FIS_SECTOR_COUNT_EXP(fis, sector_count_exp)		\
412 	(fis->ahcifhr_sectcount_sectcountexp_rsvd_devctl |=	\
413 		((sector_count_exp & 0xff) << 8))
414 
415 #define	SET_FIS_DEVCTL(fis, devctl)				\
416 	(fis->ahcifhr_sectcount_sectcountexp_rsvd_devctl |=	\
417 		((devctl & 0xff) << 24))
418 
419 	/* offset 0x10 */
420 	uint32_t	ahcifhr_rsvd3[1]; /* should be zero */
421 } ahci_fis_h2d_register_t;
422 
423 /* Register - Device to Host FIS (from SATA spec) */
424 typedef struct ahci_fis_d2h_register {
425 	/* offset 0x00 */
426 	uint32_t	ahcifdr_type_intr_rsvd_status_error;
427 
428 #define	GET_RFIS_STATUS(fis)					\
429 	((fis->ahcifdr_type_intr_rsvd_status_error >> 16) & 0xff)
430 
431 #define	GET_RFIS_ERROR(fis)					\
432 	((fis->ahcifdr_type_intr_rsvd_status_error >> 24) & 0xff)
433 
434 	/* offset 0x04 */
435 	uint32_t	ahcifdr_sector_cyllow_cylhi_devhead;
436 
437 #define	GET_RFIS_CYL_LOW(fis)					\
438 	(fis->ahcifdr_sector_cyllow_cylhi_devhead & 0xff)
439 
440 #define	GET_RFIS_CYL_MID(fis)					\
441 	((fis->ahcifdr_sector_cyllow_cylhi_devhead >> 8) & 0xff)
442 
443 #define	GET_RFIS_CYL_HI(fis)					\
444 	((fis->ahcifdr_sector_cyllow_cylhi_devhead >> 16) & 0xff)
445 
446 #define	GET_RFIS_DEV_HEAD(fis)					\
447 	((fis->ahcifdr_sector_cyllow_cylhi_devhead >> 24) & 0xff)
448 
449 	/* offset 0x08 */
450 	uint32_t	ahcifdr_sectexp_cyllowexp_cylhiexp_rsvd;
451 
452 #define	GET_RFIS_CYL_LOW_EXP(fis)					\
453 	(fis->ahcifdr_sectexp_cyllowexp_cylhiexp_rsvd  & 0xff)
454 
455 #define	GET_RFIS_CYL_MID_EXP(fis)				\
456 	((fis->ahcifdr_sectexp_cyllowexp_cylhiexp_rsvd >> 8) & 0xff)
457 
458 #define	GET_RFIS_CYL_HI_EXP(fis)					\
459 	((fis->ahcifdr_sectexp_cyllowexp_cylhiexp_rsvd >> 16) & 0xff)
460 
461 	/* offset 0x0c */
462 	uint32_t	ahcifdr_sectcount_sectcountexp_rsvd;
463 
464 #define	GET_RFIS_SECTOR_COUNT(fis)				\
465 	(fis->ahcifdr_sectcount_sectcountexp_rsvd & 0xff)
466 
467 #define	GET_RFIS_SECTOR_COUNT_EXP(fis)				\
468 	((fis->ahcifdr_sectcount_sectcountexp_rsvd >> 8) & 0xff)
469 
470 	/* offset 0x10 */
471 	uint32_t	ahcifdr_rsvd;
472 } ahci_fis_d2h_register_t;
473 
474 /* Set Device Bits - Device to Host FIS (from SATA spec) */
475 typedef struct ahci_fis_set_device_bits {
476 	/* offset 0x00 */
477 	uint32_t	ahcifsdb_type_rsvd_intr_status_error;
478 
479 #define	GET_N_BIT_OF_SET_DEV_BITS(fis)				\
480 	((fis->ahcifsdb_type_rsvd_intr_status_error >> 15) & 0x1)
481 
482 	/* offset 0x04 */
483 	uint32_t	ahcifsdb_rsvd;
484 } ahci_fis_set_device_bits_t;
485 
486 /* DMA Setup - Device to Host or Host to Device (from SATA spec) */
487 typedef struct ahci_fis_dma_setup {
488 	/* offset 0x00 */
489 	uint32_t	ahcifds_type_rsvd_direction_intr_rsvd;
490 
491 	/* offset 0x04 */
492 	uint32_t	ahcifds_dma_buffer_identifier_low;
493 
494 	/* offset 0x08 */
495 	uint32_t	ahcifds_dma_buffer_identifier_high;
496 
497 	/* offset 0x0c */
498 	uint32_t	ahcifds_rsvd1;
499 
500 	/* offset 0x10 */
501 	uint32_t	ahcifds_dma_buffer_offset;
502 
503 	/* offset 0x14 */
504 	uint32_t	ahcifds_dma_transfer_count;
505 
506 	/* offset 0x18 */
507 	uint32_t	ahcifds_rsvd2;
508 } ahci_fis_dma_setup_t;
509 
510 /* PIO Setup - Device to Host FIS (from SATA spec) */
511 typedef struct ahci_fis_pio_setup {
512 	/* offset 0x00 */
513 	uint32_t	ahcifps_type_rsvd_direction_intr_status_error;
514 
515 	/* offset 0x04 */
516 	uint32_t	ahcifps_sector_cyllow_cylhi_devhead;
517 
518 	/* offset 0x08 */
519 	uint32_t	ahcifps_sectexp_cyllowexp_cylhiexp_rsvd;
520 
521 	/* offset 0x0c */
522 	uint32_t	ahcifps_sectcount_sectcountexp_rsvd_e_status;
523 
524 	/* offset 0x10 */
525 	uint32_t	ahcifps_transfer_count_rsvd;
526 } ahci_fis_pio_setup_t;
527 
528 /* BIST Active - Host to Device or Device to Host (from SATA spec) */
529 typedef struct ahci_fis_bist_active {
530 	/* offset 0x00 */
531 	uint32_t	ahcifba_type_rsvd_pattern_rsvd;
532 
533 	/* offset 0x04 */
534 	uint32_t	ahcifba_data1;
535 
536 	/* offset 0x08 */
537 	uint32_t	ahcifba_data2;
538 } ahci_fis_bist_active_t;
539 
540 /* Up to 64 bytes */
541 typedef struct ahci_fis_unknown {
542 	uint32_t	ahcifu_first_dword;
543 	uint32_t	ahcifu_dword[15];
544 } ahci_fis_unknown_t;
545 
546 /*
547  * This is a software constructed FIS. For data transfer,
548  * this is the H2D Register FIS format as specified in
549  * the Serial ATA 1.0a specification. Valid Command FIS
550  * length are 2 to 16 Dwords.
551  */
552 typedef struct ahci_fis_command {
553 	union {
554 		ahci_fis_h2d_register_t	ahcifc_h2d_register;
555 		ahci_fis_bist_active_t	ahcifc_bist_active;
556 	} ahcifc_fis;
557 	uint32_t	ahcifc_rsvd3[11]; /* should be zero */
558 } ahci_fis_command_t;
559 
560 /* Received FISes structure - size 100h */
561 typedef struct ahci_rcvd_fis {
562 	/* offset 0x00 - DMA Setup FIS */
563 	ahci_fis_dma_setup_t		ahcirf_dma_setup_fis;
564 	uint32_t			ahcirf_fis_rsvd1;
565 
566 	/* offset 0x20 - PIO Setup FIS */
567 	ahci_fis_pio_setup_t		ahcirf_pio_setup_fis;
568 	uint32_t			ahcirf_fis_rsvd2[3];
569 
570 	/* offset 0x40 - D2H Register FIS */
571 	ahci_fis_d2h_register_t		ahcirf_d2h_register_fis;
572 	uint32_t			ahcirf_fis_rsvd3;
573 
574 	/* offset 0x58 - Set Device Bits FIS */
575 	ahci_fis_set_device_bits_t	ahcirf_set_device_bits_fis;
576 
577 	/* offset 0x60 - Unknown FIS */
578 	ahci_fis_unknown_t		ahcirf_unknown_fis;
579 
580 	/* offset 0xa0h - Reserved */
581 	uint32_t			ahcirf_fis_rsvd4[24];
582 } ahci_rcvd_fis_t;
583 
584 /* physical region description table (PRDT) item structure */
585 typedef struct ahci_prdt_item {
586 	/* DW 0 - Data Base Address */
587 	uint32_t	ahcipi_data_base_addr;
588 
589 	/* DW 1 - Data Base Address Upper */
590 	uint32_t	ahcipi_data_base_addr_upper;
591 
592 	/* DW 2 - Reserved */
593 	uint32_t	ahcipi_rsvd;
594 
595 	/* DW 3 - Description Information */
596 	uint32_t	ahcipi_descr_info;
597 
598 #define	GET_PRDT_ITEM_INTR_ON_COMPLETION(prdt_item)	\
599 		((prdt_item.ahcipi_descr_info >> 31) & 0x01)
600 
601 #define	GET_PRDT_ITEM_DATA_BYTE_COUNT(prdt_item)	\
602 		(prdt_item.ahcipi_descr_info & 0x3fffff)
603 
604 } ahci_prdt_item_t;
605 
606 /* command table structure */
607 typedef struct ahci_cmd_table {
608 	/* offset 0x00 - Command FIS */
609 	ahci_fis_command_t	ahcict_command_fis;
610 
611 	/* offset 0x40 - ATAPI Command */
612 	uint8_t			ahcict_atapi_cmd[SATA_ATAPI_MAX_CDB_LEN];
613 
614 	/* offset 0x50 - Reserved */
615 	uint32_t		ahcict_rsvd[12];
616 
617 	/* offset 0x80 - Physical Region Description Table */
618 	ahci_prdt_item_t	ahcict_prdt[AHCI_PRDT_NUMBER];
619 } ahci_cmd_table_t;
620 
621 /* command head structure - size 20h */
622 typedef struct ahci_cmd_header {
623 	/* DW 0 - Description Information */
624 	uint32_t	ahcich_descr_info;
625 
626 #define	BZERO_DESCR_INFO(cmd_header)				\
627 	(cmd_header->ahcich_descr_info = 0)
628 
629 #define	GET_PRD_TABLE_LENGTH(cmd_header)			\
630 		((cmd_header->ahcich_descr_info >> 16) & 0xffff)
631 
632 #define	SET_PRD_TABLE_LENGTH(cmd_header, length)		\
633 	(cmd_header->ahcich_descr_info |= ((length & 0xffff) << 16))
634 
635 #define	GET_PORT_MULTI_PORT(cmd_header)				\
636 		((cmd_header->ahcich_descr_info >> 12) & 0x0f)
637 
638 #define	SET_PORT_MULTI_PORT(cmd_header, flags)			\
639 	(cmd_header->ahcich_descr_info |= ((flags & 0x0f) << 12))
640 
641 #define	GET_CLEAR_BUSY_UPON_R_OK(cmd_header)			\
642 		((cmd_header->ahcich_descr_info >> 10) & 0x01)
643 
644 #define	SET_CLEAR_BUSY_UPON_R_OK(cmd_header, flags)		\
645 	(cmd_header->ahcich_descr_info |= ((flags & 0x01) << 10))
646 
647 #define	GET_BIST(cmd_header)					\
648 		((cmd_header->ahcich_descr_info >> 9) & 0x01)
649 
650 #define	GET_RESET(cmd_header)					\
651 		((cmd_header->ahcich_descr_info >> 8) & 0x01)
652 
653 #define	SET_RESET(cmd_header, features_exp)			\
654 	(cmd_header->ahcich_descr_info |= ((features_exp & 0x01) << 8))
655 
656 #define	GET_PREFETCHABLE(cmd_header)				\
657 		((cmd_header->ahcich_descr_info >> 7) & 0x01)
658 
659 #define	SET_PREFETCHABLE(cmd_header, flags)			\
660 	(cmd_header->ahcich_descr_info |= ((flags & 0x01) << 7))
661 
662 #define	GET_WRITE(cmd_header)					\
663 		((cmd_header->ahcich_descr_info >> 6) & 0x01)
664 
665 #define	SET_WRITE(cmd_header, flags)				\
666 	(cmd_header->ahcich_descr_info |= ((flags & 0x01) << 6))
667 
668 #define	GET_ATAPI(cmd_header)					\
669 		((cmd_header->ahcich_descr_info >> 5) & 0x01)
670 
671 #define	SET_ATAPI(cmd_header, flags)				\
672 	(cmd_header->ahcich_descr_info |= ((flags & 0x01) << 5))
673 
674 #define	GET_COMMAND_FIS_LENGTH(cmd_header)			\
675 		(cmd_header->ahcich_descr_info && 0x1f)
676 
677 #define	SET_COMMAND_FIS_LENGTH(cmd_header, length)		\
678 	(cmd_header->ahcich_descr_info |= (length & 0x1f))
679 
680 	/* DW 1 - Physical Region Descriptor Byte Count */
681 	uint32_t	ahcich_prd_byte_count;
682 
683 #define	BZERO_PRD_BYTE_COUNT(cmd_header)			\
684 	(cmd_header->ahcich_prd_byte_count = 0)
685 
686 	/* DW 2 - Command Table Base Address */
687 	uint32_t	ahcich_cmd_tab_base_addr;
688 
689 #define	SET_COMMAND_TABLE_BASE_ADDR(cmd_header, base_address)	\
690 	(cmd_header->ahcich_cmd_tab_base_addr = base_address)
691 
692 	/* DW 3 - Command Table Base Address Upper */
693 	uint32_t	ahcich_cmd_tab_base_addr_upper;
694 
695 #define	SET_COMMAND_TABLE_BASE_ADDR_UPPER(cmd_header, base_address) \
696 	(cmd_header->ahcich_cmd_tab_base_addr_upper = base_address)
697 
698 	/* DW 4-7 - Reserved */
699 	uint32_t	ahcich_rsvd[4];
700 } ahci_cmd_header_t;
701 
702 
703 #ifdef	__cplusplus
704 }
705 #endif
706 
707 #endif /* _AHCIREG_H */
708