1// SPDX-License-Identifier: (GPL-2.0-only OR MIT) 2// Copyright (C) 2023-2024 Arm Ltd. 3 4#include <dt-bindings/interrupt-controller/arm-gic.h> 5#include <dt-bindings/clock/sun6i-rtc.h> 6#include <dt-bindings/clock/sun55i-a523-ccu.h> 7#include <dt-bindings/clock/sun55i-a523-mcu-ccu.h> 8#include <dt-bindings/clock/sun55i-a523-r-ccu.h> 9#include <dt-bindings/reset/sun55i-a523-ccu.h> 10#include <dt-bindings/reset/sun55i-a523-mcu-ccu.h> 11#include <dt-bindings/reset/sun55i-a523-r-ccu.h> 12#include <dt-bindings/power/allwinner,sun55i-a523-ppu.h> 13#include <dt-bindings/power/allwinner,sun55i-a523-pck-600.h> 14 15/ { 16 interrupt-parent = <&gic>; 17 #address-cells = <2>; 18 #size-cells = <2>; 19 20 cpus { 21 #address-cells = <1>; 22 #size-cells = <0>; 23 24 cpu0: cpu@0 { 25 compatible = "arm,cortex-a55"; 26 device_type = "cpu"; 27 reg = <0x000>; 28 enable-method = "psci"; 29 }; 30 31 cpu1: cpu@100 { 32 compatible = "arm,cortex-a55"; 33 device_type = "cpu"; 34 reg = <0x100>; 35 enable-method = "psci"; 36 }; 37 38 cpu2: cpu@200 { 39 compatible = "arm,cortex-a55"; 40 device_type = "cpu"; 41 reg = <0x200>; 42 enable-method = "psci"; 43 }; 44 45 cpu3: cpu@300 { 46 compatible = "arm,cortex-a55"; 47 device_type = "cpu"; 48 reg = <0x300>; 49 enable-method = "psci"; 50 }; 51 52 cpu4: cpu@400 { 53 compatible = "arm,cortex-a55"; 54 device_type = "cpu"; 55 reg = <0x400>; 56 enable-method = "psci"; 57 }; 58 59 cpu5: cpu@500 { 60 compatible = "arm,cortex-a55"; 61 device_type = "cpu"; 62 reg = <0x500>; 63 enable-method = "psci"; 64 }; 65 66 cpu6: cpu@600 { 67 compatible = "arm,cortex-a55"; 68 device_type = "cpu"; 69 reg = <0x600>; 70 enable-method = "psci"; 71 }; 72 73 cpu7: cpu@700 { 74 compatible = "arm,cortex-a55"; 75 device_type = "cpu"; 76 reg = <0x700>; 77 enable-method = "psci"; 78 }; 79 }; 80 81 osc24M: osc24M-clk { 82 #clock-cells = <0>; 83 compatible = "fixed-clock"; 84 clock-frequency = <24000000>; 85 clock-output-names = "osc24M"; 86 }; 87 88 pmu { 89 compatible = "arm,cortex-a55-pmu"; 90 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; 91 }; 92 93 psci { 94 compatible = "arm,psci-0.2"; 95 method = "smc"; 96 }; 97 98 timer { 99 compatible = "arm,armv8-timer"; 100 arm,no-tick-in-suspend; 101 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>, 102 <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>, 103 <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>, 104 <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>; 105 }; 106 107 soc { 108 compatible = "simple-bus"; 109 #address-cells = <1>; 110 #size-cells = <1>; 111 ranges = <0x0 0x0 0x0 0x40000000>; 112 113 gpu: gpu@1800000 { 114 compatible = "allwinner,sun55i-a523-mali", 115 "arm,mali-valhall-jm"; 116 reg = <0x1800000 0x10000>; 117 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 118 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 119 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; 120 interrupt-names = "job", "mmu", "gpu"; 121 clocks = <&ccu CLK_GPU>, <&ccu CLK_BUS_GPU>; 122 clock-names = "core", "bus"; 123 power-domains = <&pck600 PD_GPU>; 124 resets = <&ccu RST_BUS_GPU>; 125 status = "disabled"; 126 }; 127 128 pio: pinctrl@2000000 { 129 compatible = "allwinner,sun55i-a523-pinctrl"; 130 reg = <0x2000000 0x800>; 131 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>, 132 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>, 133 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, 134 <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>, 135 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, 136 <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>, 137 <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>, 138 <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>, 139 <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, 140 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 141 clocks = <&ccu CLK_APB1>, <&osc24M>, <&rtc CLK_OSC32K>; 142 clock-names = "apb", "hosc", "losc"; 143 gpio-controller; 144 #gpio-cells = <3>; 145 interrupt-controller; 146 #interrupt-cells = <3>; 147 148 /omit-if-no-ref/ 149 i2s2_pi_pins: i2s2-pi-pins { 150 pins = "PI2", "PI3", "PI4", "PI5"; 151 allwinner,pinmux = <5>; 152 function = "i2s2"; 153 bias-disable; 154 }; 155 156 mmc0_pins: mmc0-pins { 157 pins = "PF0" ,"PF1", "PF2", "PF3", "PF4", "PF5"; 158 allwinner,pinmux = <2>; 159 function = "mmc0"; 160 drive-strength = <30>; 161 bias-pull-up; 162 }; 163 164 /omit-if-no-ref/ 165 mmc1_pins: mmc1-pins { 166 pins = "PG0" ,"PG1", "PG2", "PG3", "PG4", "PG5"; 167 allwinner,pinmux = <2>; 168 function = "mmc1"; 169 drive-strength = <30>; 170 bias-pull-up; 171 }; 172 173 mmc2_pins: mmc2-pins { 174 pins = "PC0", "PC1" ,"PC5", "PC6", "PC8", 175 "PC9", "PC10", "PC11", "PC13", "PC14", 176 "PC15", "PC16"; 177 allwinner,pinmux = <3>; 178 function = "mmc2"; 179 drive-strength = <30>; 180 bias-pull-up; 181 }; 182 183 rgmii0_pins: rgmii0-pins { 184 pins = "PH0", "PH1", "PH2", "PH3", "PH4", 185 "PH5", "PH6", "PH7", "PH9", "PH10", 186 "PH14", "PH15", "PH16", "PH17", "PH18"; 187 allwinner,pinmux = <5>; 188 function = "gmac0"; 189 drive-strength = <40>; 190 bias-disable; 191 }; 192 193 rgmii1_pins: rgmii1-pins { 194 pins = "PJ0", "PJ1", "PJ2", "PJ3", "PJ4", 195 "PJ5", "PJ6", "PJ7", "PJ8", "PJ9", 196 "PJ11", "PJ12", "PJ13", "PJ14", "PJ15"; 197 allwinner,pinmux = <5>; 198 function = "gmac1"; 199 drive-strength = <40>; 200 bias-disable; 201 }; 202 203 /omit-if-no-ref/ 204 spdif_out_pb_pin: spdif-pb-pin { 205 pins = "PB8"; 206 function = "spdif"; 207 allwinner,pinmux = <2>; 208 }; 209 210 /omit-if-no-ref/ 211 spdif_out_pi_pin: spdif-pi-pin { 212 pins = "PI10"; 213 function = "spdif"; 214 allwinner,pinmux = <2>; 215 }; 216 217 uart0_pb_pins: uart0-pb-pins { 218 pins = "PB9", "PB10"; 219 allwinner,pinmux = <2>; 220 function = "uart0"; 221 }; 222 223 /omit-if-no-ref/ 224 uart1_pins: uart1-pins { 225 pins = "PG6", "PG7"; 226 function = "uart1"; 227 allwinner,pinmux = <2>; 228 }; 229 230 /omit-if-no-ref/ 231 uart1_rts_cts_pins: uart1-rts-cts-pins { 232 pins = "PG8", "PG9"; 233 function = "uart1"; 234 allwinner,pinmux = <2>; 235 }; 236 }; 237 238 ccu: clock-controller@2001000 { 239 compatible = "allwinner,sun55i-a523-ccu"; 240 reg = <0x02001000 0x1000>; 241 clocks = <&osc24M>, <&rtc CLK_OSC32K>, 242 <&rtc CLK_IOSC>, <&rtc CLK_OSC32K_FANOUT>; 243 clock-names = "hosc", "losc", 244 "iosc", "losc-fanout"; 245 #clock-cells = <1>; 246 #reset-cells = <1>; 247 }; 248 249 wdt: watchdog@2050000 { 250 compatible = "allwinner,sun55i-a523-wdt"; 251 reg = <0x2050000 0x20>; 252 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 253 clocks = <&osc24M>, <&rtc CLK_OSC32K>; 254 clock-names = "hosc", "losc"; 255 status = "okay"; 256 }; 257 258 uart0: serial@2500000 { 259 compatible = "snps,dw-apb-uart"; 260 reg = <0x02500000 0x400>; 261 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 262 reg-shift = <2>; 263 reg-io-width = <4>; 264 clocks = <&ccu CLK_BUS_UART0>; 265 resets = <&ccu RST_BUS_UART0>; 266 dmas = <&dma 14>, <&dma 14>; 267 dma-names = "tx", "rx"; 268 status = "disabled"; 269 }; 270 271 uart1: serial@2500400 { 272 compatible = "snps,dw-apb-uart"; 273 reg = <0x02500400 0x400>; 274 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 275 reg-shift = <2>; 276 reg-io-width = <4>; 277 clocks = <&ccu CLK_BUS_UART1>; 278 resets = <&ccu RST_BUS_UART1>; 279 dmas = <&dma 15>, <&dma 15>; 280 dma-names = "tx", "rx"; 281 status = "disabled"; 282 }; 283 284 uart2: serial@2500800 { 285 compatible = "snps,dw-apb-uart"; 286 reg = <0x02500800 0x400>; 287 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 288 reg-shift = <2>; 289 reg-io-width = <4>; 290 clocks = <&ccu CLK_BUS_UART2>; 291 resets = <&ccu RST_BUS_UART2>; 292 dmas = <&dma 16>, <&dma 16>; 293 dma-names = "tx", "rx"; 294 status = "disabled"; 295 }; 296 297 uart3: serial@2500c00 { 298 compatible = "snps,dw-apb-uart"; 299 reg = <0x02500c00 0x400>; 300 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 301 reg-shift = <2>; 302 reg-io-width = <4>; 303 clocks = <&ccu CLK_BUS_UART3>; 304 resets = <&ccu RST_BUS_UART3>; 305 dmas = <&dma 17>, <&dma 17>; 306 dma-names = "tx", "rx"; 307 status = "disabled"; 308 }; 309 310 uart4: serial@2501000 { 311 compatible = "snps,dw-apb-uart"; 312 reg = <0x02501000 0x400>; 313 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 314 reg-shift = <2>; 315 reg-io-width = <4>; 316 clocks = <&ccu CLK_BUS_UART4>; 317 resets = <&ccu RST_BUS_UART4>; 318 dmas = <&dma 18>, <&dma 18>; 319 dma-names = "tx", "rx"; 320 status = "disabled"; 321 }; 322 323 uart5: serial@2501400 { 324 compatible = "snps,dw-apb-uart"; 325 reg = <0x02501400 0x400>; 326 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 327 reg-shift = <2>; 328 reg-io-width = <4>; 329 clocks = <&ccu CLK_BUS_UART5>; 330 resets = <&ccu RST_BUS_UART5>; 331 dmas = <&dma 19>, <&dma 19>; 332 dma-names = "tx", "rx"; 333 status = "disabled"; 334 }; 335 336 uart6: serial@2501800 { 337 compatible = "snps,dw-apb-uart"; 338 reg = <0x02501800 0x400>; 339 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 340 reg-shift = <2>; 341 reg-io-width = <4>; 342 clocks = <&ccu CLK_BUS_UART6>; 343 resets = <&ccu RST_BUS_UART6>; 344 dmas = <&dma 20>, <&dma 20>; 345 dma-names = "tx", "rx"; 346 status = "disabled"; 347 }; 348 349 uart7: serial@2501c00 { 350 compatible = "snps,dw-apb-uart"; 351 reg = <0x02501c00 0x400>; 352 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 353 reg-shift = <2>; 354 reg-io-width = <4>; 355 clocks = <&ccu CLK_BUS_UART7>; 356 resets = <&ccu RST_BUS_UART7>; 357 dmas = <&dma 21>, <&dma 21>; 358 dma-names = "tx", "rx"; 359 status = "disabled"; 360 }; 361 362 i2c0: i2c@2502000 { 363 compatible = "allwinner,sun55i-a523-i2c", 364 "allwinner,sun8i-v536-i2c", 365 "allwinner,sun6i-a31-i2c"; 366 reg = <0x2502000 0x400>; 367 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 368 clocks = <&ccu CLK_BUS_I2C0>; 369 resets = <&ccu RST_BUS_I2C0>; 370 dmas = <&dma 43>, <&dma 43>; 371 dma-names = "rx", "tx"; 372 status = "disabled"; 373 #address-cells = <1>; 374 #size-cells = <0>; 375 }; 376 377 i2c1: i2c@2502400 { 378 compatible = "allwinner,sun55i-a523-i2c", 379 "allwinner,sun8i-v536-i2c", 380 "allwinner,sun6i-a31-i2c"; 381 reg = <0x2502400 0x400>; 382 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 383 clocks = <&ccu CLK_BUS_I2C1>; 384 resets = <&ccu RST_BUS_I2C1>; 385 dmas = <&dma 44>, <&dma 44>; 386 dma-names = "rx", "tx"; 387 status = "disabled"; 388 #address-cells = <1>; 389 #size-cells = <0>; 390 }; 391 392 i2c2: i2c@2502800 { 393 compatible = "allwinner,sun55i-a523-i2c", 394 "allwinner,sun8i-v536-i2c", 395 "allwinner,sun6i-a31-i2c"; 396 reg = <0x2502800 0x400>; 397 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 398 clocks = <&ccu CLK_BUS_I2C2>; 399 resets = <&ccu RST_BUS_I2C2>; 400 dmas = <&dma 45>, <&dma 45>; 401 dma-names = "rx", "tx"; 402 status = "disabled"; 403 #address-cells = <1>; 404 #size-cells = <0>; 405 }; 406 407 i2c3: i2c@2502c00 { 408 compatible = "allwinner,sun55i-a523-i2c", 409 "allwinner,sun8i-v536-i2c", 410 "allwinner,sun6i-a31-i2c"; 411 reg = <0x2502c00 0x400>; 412 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 413 clocks = <&ccu CLK_BUS_I2C3>; 414 resets = <&ccu RST_BUS_I2C3>; 415 dmas = <&dma 46>, <&dma 46>; 416 dma-names = "rx", "tx"; 417 status = "disabled"; 418 #address-cells = <1>; 419 #size-cells = <0>; 420 }; 421 422 i2c4: i2c@2503000 { 423 compatible = "allwinner,sun55i-a523-i2c", 424 "allwinner,sun8i-v536-i2c", 425 "allwinner,sun6i-a31-i2c"; 426 reg = <0x2503000 0x400>; 427 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 428 clocks = <&ccu CLK_BUS_I2C4>; 429 resets = <&ccu RST_BUS_I2C4>; 430 dmas = <&dma 47>, <&dma 47>; 431 dma-names = "rx", "tx"; 432 status = "disabled"; 433 #address-cells = <1>; 434 #size-cells = <0>; 435 }; 436 437 i2c5: i2c@2503400 { 438 compatible = "allwinner,sun55i-a523-i2c", 439 "allwinner,sun8i-v536-i2c", 440 "allwinner,sun6i-a31-i2c"; 441 reg = <0x2503400 0x400>; 442 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 443 clocks = <&ccu CLK_BUS_I2C5>; 444 resets = <&ccu RST_BUS_I2C5>; 445 dmas = <&dma 48>, <&dma 48>; 446 dma-names = "rx", "tx"; 447 status = "disabled"; 448 #address-cells = <1>; 449 #size-cells = <0>; 450 }; 451 452 syscon: syscon@3000000 { 453 compatible = "allwinner,sun55i-a523-system-control", 454 "allwinner,sun50i-a64-system-control"; 455 reg = <0x03000000 0x1000>; 456 #address-cells = <1>; 457 #size-cells = <1>; 458 ranges; 459 }; 460 461 dma: dma-controller@3002000 { 462 compatible = "allwinner,sun55i-a523-dma", 463 "allwinner,sun50i-a100-dma"; 464 reg = <0x03002000 0x1000>; 465 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 466 clocks = <&ccu CLK_BUS_DMA>, <&ccu CLK_MBUS_DMA>; 467 clock-names = "bus", "mbus"; 468 dma-channels = <16>; 469 dma-requests = <54>; 470 resets = <&ccu RST_BUS_DMA>; 471 #dma-cells = <1>; 472 }; 473 474 sid: efuse@3006000 { 475 compatible = "allwinner,sun55i-a523-sid", 476 "allwinner,sun50i-a64-sid"; 477 reg = <0x03006000 0x1000>; 478 #address-cells = <1>; 479 #size-cells = <1>; 480 }; 481 482 gic: interrupt-controller@3400000 { 483 compatible = "arm,gic-v3"; 484 #address-cells = <1>; 485 #interrupt-cells = <3>; 486 #size-cells = <1>; 487 ranges; 488 interrupt-controller; 489 reg = <0x3400000 0x10000>, 490 <0x3460000 0x100000>; 491 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 492 dma-noncoherent; 493 494 its: msi-controller@3440000 { 495 compatible = "arm,gic-v3-its"; 496 reg = <0x3440000 0x20000>; 497 msi-controller; 498 #msi-cells = <1>; 499 dma-noncoherent; 500 }; 501 }; 502 503 mmc0: mmc@4020000 { 504 compatible = "allwinner,sun55i-a523-mmc", 505 "allwinner,sun20i-d1-mmc"; 506 reg = <0x04020000 0x1000>; 507 clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>; 508 clock-names = "ahb", "mmc"; 509 resets = <&ccu RST_BUS_MMC0>; 510 reset-names = "ahb"; 511 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 512 pinctrl-names = "default"; 513 pinctrl-0 = <&mmc0_pins>; 514 status = "disabled"; 515 516 max-frequency = <150000000>; 517 cap-sd-highspeed; 518 cap-mmc-highspeed; 519 cap-sdio-irq; 520 #address-cells = <1>; 521 #size-cells = <0>; 522 }; 523 524 mmc1: mmc@4021000 { 525 compatible = "allwinner,sun55i-a523-mmc", 526 "allwinner,sun20i-d1-mmc"; 527 reg = <0x04021000 0x1000>; 528 clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>; 529 clock-names = "ahb", "mmc"; 530 resets = <&ccu RST_BUS_MMC1>; 531 reset-names = "ahb"; 532 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 533 pinctrl-names = "default"; 534 pinctrl-0 = <&mmc1_pins>; 535 status = "disabled"; 536 537 max-frequency = <150000000>; 538 cap-sd-highspeed; 539 cap-mmc-highspeed; 540 cap-sdio-irq; 541 #address-cells = <1>; 542 #size-cells = <0>; 543 }; 544 545 mmc2: mmc@4022000 { 546 compatible = "allwinner,sun55i-a523-mmc", 547 "allwinner,sun20i-d1-mmc"; 548 reg = <0x04022000 0x1000>; 549 clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>; 550 clock-names = "ahb", "mmc"; 551 resets = <&ccu RST_BUS_MMC2>; 552 reset-names = "ahb"; 553 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; 554 pinctrl-names = "default"; 555 pinctrl-0 = <&mmc2_pins>; 556 status = "disabled"; 557 558 max-frequency = <150000000>; 559 cap-sd-highspeed; 560 cap-mmc-highspeed; 561 cap-sdio-irq; 562 #address-cells = <1>; 563 #size-cells = <0>; 564 }; 565 566 usb_otg: usb@4100000 { 567 compatible = "allwinner,sun55i-a523-musb", 568 "allwinner,sun8i-a33-musb"; 569 reg = <0x4100000 0x400>; 570 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 571 interrupt-names = "mc"; 572 clocks = <&ccu CLK_BUS_OTG>; 573 resets = <&ccu RST_BUS_OTG>; 574 extcon = <&usbphy 0>; 575 phys = <&usbphy 0>; 576 phy-names = "usb"; 577 status = "disabled"; 578 }; 579 580 usbphy: phy@4100400 { 581 compatible = "allwinner,sun55i-a523-usb-phy", 582 "allwinner,sun20i-d1-usb-phy"; 583 reg = <0x4100400 0x100>, 584 <0x4101800 0x100>, 585 <0x4200800 0x100>; 586 reg-names = "phy_ctrl", 587 "pmu0", 588 "pmu1"; 589 clocks = <&osc24M>, 590 <&osc24M>; 591 clock-names = "usb0_phy", 592 "usb1_phy"; 593 resets = <&ccu RST_USB_PHY0>, 594 <&ccu RST_USB_PHY1>; 595 reset-names = "usb0_reset", 596 "usb1_reset"; 597 status = "disabled"; 598 #phy-cells = <1>; 599 }; 600 601 ehci0: usb@4101000 { 602 compatible = "allwinner,sun55i-a523-ehci", 603 "generic-ehci"; 604 reg = <0x4101000 0x100>; 605 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 606 clocks = <&ccu CLK_BUS_OHCI0>, 607 <&ccu CLK_BUS_EHCI0>, 608 <&ccu CLK_USB_OHCI0>; 609 resets = <&ccu RST_BUS_OHCI0>, 610 <&ccu RST_BUS_EHCI0>; 611 phys = <&usbphy 0>; 612 phy-names = "usb"; 613 status = "disabled"; 614 }; 615 616 ohci0: usb@4101400 { 617 compatible = "allwinner,sun55i-a523-ohci", 618 "generic-ohci"; 619 reg = <0x4101400 0x100>; 620 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 621 clocks = <&ccu CLK_BUS_OHCI0>, 622 <&ccu CLK_USB_OHCI0>; 623 resets = <&ccu RST_BUS_OHCI0>; 624 phys = <&usbphy 0>; 625 phy-names = "usb"; 626 status = "disabled"; 627 }; 628 629 ehci1: usb@4200000 { 630 compatible = "allwinner,sun55i-a523-ehci", 631 "generic-ehci"; 632 reg = <0x4200000 0x100>; 633 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 634 clocks = <&ccu CLK_BUS_OHCI1>, 635 <&ccu CLK_BUS_EHCI1>, 636 <&ccu CLK_USB_OHCI1>; 637 resets = <&ccu RST_BUS_OHCI1>, 638 <&ccu RST_BUS_EHCI1>; 639 phys = <&usbphy 1>; 640 phy-names = "usb"; 641 status = "disabled"; 642 }; 643 644 ohci1: usb@4200400 { 645 compatible = "allwinner,sun55i-a523-ohci", 646 "generic-ohci"; 647 reg = <0x4200400 0x100>; 648 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 649 clocks = <&ccu CLK_BUS_OHCI1>, 650 <&ccu CLK_USB_OHCI1>; 651 resets = <&ccu RST_BUS_OHCI1>; 652 phys = <&usbphy 1>; 653 phy-names = "usb"; 654 status = "disabled"; 655 }; 656 657 gmac0: ethernet@4500000 { 658 compatible = "allwinner,sun55i-a523-gmac0", 659 "allwinner,sun50i-a64-emac"; 660 reg = <0x04500000 0x10000>; 661 clocks = <&ccu CLK_BUS_EMAC0>; 662 clock-names = "stmmaceth"; 663 resets = <&ccu RST_BUS_EMAC0>; 664 reset-names = "stmmaceth"; 665 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 666 interrupt-names = "macirq"; 667 pinctrl-names = "default"; 668 pinctrl-0 = <&rgmii0_pins>; 669 syscon = <&syscon>; 670 status = "disabled"; 671 672 mdio0: mdio { 673 compatible = "snps,dwmac-mdio"; 674 #address-cells = <1>; 675 #size-cells = <0>; 676 }; 677 }; 678 679 gmac1: ethernet@4510000 { 680 compatible = "allwinner,sun55i-a523-gmac200", 681 "snps,dwmac-4.20a"; 682 reg = <0x04510000 0x10000>; 683 clocks = <&ccu CLK_BUS_EMAC1>, <&ccu CLK_MBUS_EMAC1>; 684 clock-names = "stmmaceth", "mbus"; 685 resets = <&ccu RST_BUS_EMAC1>; 686 reset-names = "stmmaceth"; 687 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 688 interrupt-names = "macirq"; 689 pinctrl-names = "default"; 690 pinctrl-0 = <&rgmii1_pins>; 691 power-domains = <&pck600 PD_VO1>; 692 syscon = <&syscon>; 693 snps,fixed-burst; 694 snps,axi-config = <&gmac1_stmmac_axi_setup>; 695 snps,mtl-rx-config = <&gmac1_mtl_rx_setup>; 696 snps,mtl-tx-config = <&gmac1_mtl_tx_setup>; 697 status = "disabled"; 698 699 mdio1: mdio { 700 compatible = "snps,dwmac-mdio"; 701 #address-cells = <1>; 702 #size-cells = <0>; 703 }; 704 705 gmac1_mtl_rx_setup: rx-queues-config { 706 snps,rx-queues-to-use = <1>; 707 708 queue0 {}; 709 }; 710 711 gmac1_stmmac_axi_setup: stmmac-axi-config { 712 snps,wr_osr_lmt = <0xf>; 713 snps,rd_osr_lmt = <0xf>; 714 snps,blen = <256 128 64 32 16 8 4>; 715 }; 716 717 gmac1_mtl_tx_setup: tx-queues-config { 718 snps,tx-queues-to-use = <1>; 719 720 queue0 {}; 721 }; 722 }; 723 724 ppu: power-controller@7001400 { 725 compatible = "allwinner,sun55i-a523-ppu"; 726 reg = <0x07001400 0x400>; 727 clocks = <&r_ccu CLK_BUS_R_PPU1>; 728 resets = <&r_ccu RST_BUS_R_PPU1>; 729 #power-domain-cells = <1>; 730 }; 731 732 r_ccu: clock-controller@7010000 { 733 compatible = "allwinner,sun55i-a523-r-ccu"; 734 reg = <0x7010000 0x250>; 735 clocks = <&osc24M>, 736 <&rtc CLK_OSC32K>, 737 <&rtc CLK_IOSC>, 738 <&ccu CLK_PLL_PERIPH0_200M>, 739 <&ccu CLK_PLL_AUDIO0_4X>; 740 clock-names = "hosc", 741 "losc", 742 "iosc", 743 "pll-periph", 744 "pll-audio"; 745 #clock-cells = <1>; 746 #reset-cells = <1>; 747 assigned-clocks = <&r_ccu CLK_R_AHB>, <&r_ccu CLK_R_APB0>; 748 assigned-clock-rates = <200000000>, <100000000>; 749 }; 750 751 nmi_intc: interrupt-controller@7010320 { 752 compatible = "allwinner,sun55i-a523-nmi"; 753 reg = <0x07010320 0xc>; 754 interrupt-controller; 755 #interrupt-cells = <2>; 756 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; 757 }; 758 759 r_pio: pinctrl@7022000 { 760 compatible = "allwinner,sun55i-a523-r-pinctrl"; 761 reg = <0x7022000 0x800>; 762 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>, 763 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 764 clocks = <&r_ccu CLK_R_APB0>, 765 <&osc24M>, 766 <&rtc CLK_OSC32K>; 767 clock-names = "apb", "hosc", "losc"; 768 gpio-controller; 769 #gpio-cells = <3>; 770 interrupt-controller; 771 #interrupt-cells = <3>; 772 773 r_i2c_pins: r-i2c-pins { 774 pins = "PL0" ,"PL1"; 775 allwinner,pinmux = <2>; 776 function = "r_i2c0"; 777 }; 778 }; 779 780 pck600: power-controller@7060000 { 781 compatible = "allwinner,sun55i-a523-pck-600"; 782 reg = <0x07060000 0x8000>; 783 clocks = <&r_ccu CLK_BUS_R_PPU0>; 784 resets = <&r_ccu RST_BUS_R_PPU0>; 785 #power-domain-cells = <1>; 786 }; 787 788 r_i2c0: i2c@7081400 { 789 compatible = "allwinner,sun55i-a523-i2c", 790 "allwinner,sun8i-v536-i2c", 791 "allwinner,sun6i-a31-i2c"; 792 reg = <0x07081400 0x400>; 793 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 794 clocks = <&r_ccu CLK_BUS_R_I2C0>; 795 dmas = <&dma 49>, <&dma 49>; 796 dma-names = "rx", "tx"; 797 resets = <&r_ccu RST_BUS_R_I2C0>; 798 pinctrl-names = "default"; 799 pinctrl-0 = <&r_i2c_pins>; 800 status = "disabled"; 801 802 #address-cells = <1>; 803 #size-cells = <0>; 804 }; 805 806 rtc: rtc@7090000 { 807 compatible = "allwinner,sun55i-a523-rtc", 808 "allwinner,sun50i-r329-rtc"; 809 reg = <0x7090000 0x400>; 810 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 811 clocks = <&r_ccu CLK_BUS_R_RTC>, 812 <&osc24M>, 813 <&r_ccu CLK_R_AHB>; 814 clock-names = "bus", "hosc", "ahb"; 815 #clock-cells = <1>; 816 }; 817 818 mcu_ccu: clock-controller@7102000 { 819 compatible = "allwinner,sun55i-a523-mcu-ccu"; 820 reg = <0x7102000 0x200>; 821 clocks = <&osc24M>, 822 <&rtc CLK_OSC32K>, 823 <&rtc CLK_IOSC>, 824 <&ccu CLK_PLL_AUDIO0_4X>, 825 <&ccu CLK_PLL_PERIPH0_300M>, 826 <&ccu CLK_DSP>, 827 <&ccu CLK_MBUS>, 828 <&r_ccu CLK_R_AHB>, 829 <&r_ccu CLK_R_APB0>; 830 clock-names = "hosc", 831 "losc", 832 "iosc", 833 "pll-audio0-4x", 834 "pll-periph0-300m", 835 "dsp", 836 "mbus", 837 "r-ahb", 838 "r-apb0"; 839 #clock-cells = <1>; 840 #reset-cells = <1>; 841 }; 842 843 i2s0: i2s@7112000 { 844 compatible = "allwinner,sun55i-a523-i2s", 845 "allwinner,sun50i-r329-i2s"; 846 reg = <0x07112000 0x1000>; 847 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; 848 clocks = <&mcu_ccu CLK_BUS_MCU_I2S0>, <&mcu_ccu CLK_MCU_I2S0>; 849 clock-names = "apb", "mod"; 850 resets = <&mcu_ccu RST_BUS_MCU_I2S0>; 851 dmas = <&mcu_dma 3>, <&mcu_dma 3>; 852 dma-names = "rx", "tx"; 853 #sound-dai-cells = <0>; 854 status = "disabled"; 855 }; 856 857 i2s1: i2s@7113000 { 858 compatible = "allwinner,sun55i-a523-i2s", 859 "allwinner,sun50i-r329-i2s"; 860 reg = <0x07113000 0x1000>; 861 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>; 862 clocks = <&mcu_ccu CLK_BUS_MCU_I2S1>, <&mcu_ccu CLK_MCU_I2S1>; 863 clock-names = "apb", "mod"; 864 resets = <&mcu_ccu RST_BUS_MCU_I2S1>; 865 dmas = <&mcu_dma 4>, <&mcu_dma 4>; 866 dma-names = "rx", "tx"; 867 #sound-dai-cells = <0>; 868 status = "disabled"; 869 }; 870 871 i2s2: i2s@7114000 { 872 compatible = "allwinner,sun55i-a523-i2s", 873 "allwinner,sun50i-r329-i2s"; 874 reg = <0x07114000 0x1000>; 875 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; 876 clocks = <&mcu_ccu CLK_BUS_MCU_I2S2>, <&mcu_ccu CLK_MCU_I2S2>; 877 clock-names = "apb", "mod"; 878 resets = <&mcu_ccu RST_BUS_MCU_I2S2>; 879 dmas = <&mcu_dma 5>, <&mcu_dma 5>; 880 dma-names = "rx", "tx"; 881 #sound-dai-cells = <0>; 882 status = "disabled"; 883 }; 884 885 i2s3: i2s@7115000 { 886 compatible = "allwinner,sun55i-a523-i2s", 887 "allwinner,sun50i-r329-i2s"; 888 reg = <0x07115000 0x1000>; 889 interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>; 890 clocks = <&mcu_ccu CLK_BUS_MCU_I2S3>, <&mcu_ccu CLK_MCU_I2S3>; 891 clock-names = "apb", "mod"; 892 resets = <&mcu_ccu RST_BUS_MCU_I2S3>; 893 dmas = <&mcu_dma 6>, <&mcu_dma 6>; 894 dma-names = "rx", "tx"; 895 #sound-dai-cells = <0>; 896 status = "disabled"; 897 }; 898 899 spdif: spdif@7116000 { 900 compatible = "allwinner,sun55i-a523-spdif"; 901 reg = <0x07116000 0x400>; 902 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>; 903 clocks = <&mcu_ccu CLK_BUS_MCU_SPDIF>, 904 <&mcu_ccu CLK_MCU_SPDIF_TX>, 905 <&mcu_ccu CLK_MCU_SPDIF_RX>; 906 clock-names = "apb", "tx", "rx"; 907 resets = <&mcu_ccu RST_BUS_MCU_SPDIF>; 908 dmas = <&mcu_dma 2>, <&mcu_dma 2>; 909 dma-names = "rx", "tx"; 910 #sound-dai-cells = <0>; 911 status = "disabled"; 912 }; 913 914 mcu_dma: dma-controller@7121000 { 915 compatible = "allwinner,sun55i-a523-mcu-dma", 916 "allwinner,sun50i-a100-dma"; 917 reg = <0x07121000 0x1000>; 918 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; 919 clocks = <&mcu_ccu CLK_BUS_MCU_DMA>, <&mcu_ccu CLK_MCU_MBUS_DMA>; 920 clock-names = "bus", "mbus"; 921 dma-channels = <16>; 922 dma-requests = <15>; 923 resets = <&mcu_ccu RST_BUS_MCU_DMA>; 924 #dma-cells = <1>; 925 }; 926 927 npu: npu@7122000 { 928 compatible = "vivante,gc"; 929 reg = <0x07122000 0x1000>; 930 interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>; 931 clocks = <&mcu_ccu CLK_BUS_MCU_NPU_ACLK>, 932 <&ccu CLK_NPU>, 933 <&mcu_ccu CLK_BUS_MCU_NPU_HCLK>; 934 clock-names = "bus", "core", "reg"; 935 resets = <&mcu_ccu RST_BUS_MCU_NPU>; 936 power-domains = <&ppu PD_NPU>; 937 }; 938 }; 939}; 940