1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright 2025 Cix Technology Group Co., Ltd. 4 * 5 */ 6 7#include <dt-bindings/interrupt-controller/arm-gic.h> 8#include <dt-bindings/clock/cix,sky1.h> 9 10/ { 11 interrupt-parent = <&gic>; 12 #address-cells = <2>; 13 #size-cells = <2>; 14 15 cpus { 16 #address-cells = <2>; 17 #size-cells = <0>; 18 19 cpu0: cpu@0 { 20 compatible = "arm,cortex-a520"; 21 enable-method = "psci"; 22 reg = <0x0 0x0>; 23 device_type = "cpu"; 24 capacity-dmips-mhz = <403>; 25 }; 26 27 cpu1: cpu@100 { 28 compatible = "arm,cortex-a520"; 29 enable-method = "psci"; 30 reg = <0x0 0x100>; 31 device_type = "cpu"; 32 capacity-dmips-mhz = <403>; 33 }; 34 35 cpu2: cpu@200 { 36 compatible = "arm,cortex-a520"; 37 enable-method = "psci"; 38 reg = <0x0 0x200>; 39 device_type = "cpu"; 40 capacity-dmips-mhz = <403>; 41 }; 42 43 cpu3: cpu@300 { 44 compatible = "arm,cortex-a520"; 45 enable-method = "psci"; 46 reg = <0x0 0x300>; 47 device_type = "cpu"; 48 capacity-dmips-mhz = <403>; 49 }; 50 51 cpu4: cpu@400 { 52 compatible = "arm,cortex-a720"; 53 enable-method = "psci"; 54 reg = <0x0 0x400>; 55 device_type = "cpu"; 56 capacity-dmips-mhz = <1024>; 57 }; 58 59 cpu5: cpu@500 { 60 compatible = "arm,cortex-a720"; 61 enable-method = "psci"; 62 reg = <0x0 0x500>; 63 device_type = "cpu"; 64 capacity-dmips-mhz = <1024>; 65 }; 66 67 cpu6: cpu@600 { 68 compatible = "arm,cortex-a720"; 69 enable-method = "psci"; 70 reg = <0x0 0x600>; 71 device_type = "cpu"; 72 capacity-dmips-mhz = <1024>; 73 }; 74 75 cpu7: cpu@700 { 76 compatible = "arm,cortex-a720"; 77 enable-method = "psci"; 78 reg = <0x0 0x700>; 79 device_type = "cpu"; 80 capacity-dmips-mhz = <1024>; 81 }; 82 83 cpu8: cpu@800 { 84 compatible = "arm,cortex-a720"; 85 enable-method = "psci"; 86 reg = <0x0 0x800>; 87 device_type = "cpu"; 88 capacity-dmips-mhz = <1024>; 89 }; 90 91 cpu9: cpu@900 { 92 compatible = "arm,cortex-a720"; 93 enable-method = "psci"; 94 reg = <0x0 0x900>; 95 device_type = "cpu"; 96 capacity-dmips-mhz = <1024>; 97 }; 98 99 cpu10: cpu@a00 { 100 compatible = "arm,cortex-a720"; 101 enable-method = "psci"; 102 reg = <0x0 0xa00>; 103 device_type = "cpu"; 104 capacity-dmips-mhz = <1024>; 105 }; 106 107 cpu11: cpu@b00 { 108 compatible = "arm,cortex-a720"; 109 enable-method = "psci"; 110 reg = <0x0 0xb00>; 111 device_type = "cpu"; 112 capacity-dmips-mhz = <1024>; 113 }; 114 115 cpu-map { 116 cluster0 { 117 core0 { 118 cpu = <&cpu0>; 119 }; 120 core1 { 121 cpu = <&cpu1>; 122 }; 123 core2 { 124 cpu = <&cpu2>; 125 }; 126 core3 { 127 cpu = <&cpu3>; 128 }; 129 core4 { 130 cpu = <&cpu4>; 131 }; 132 core5 { 133 cpu = <&cpu5>; 134 }; 135 core6 { 136 cpu = <&cpu6>; 137 }; 138 core7 { 139 cpu = <&cpu7>; 140 }; 141 core8 { 142 cpu = <&cpu8>; 143 }; 144 core9 { 145 cpu = <&cpu9>; 146 }; 147 core10 { 148 cpu = <&cpu10>; 149 }; 150 core11 { 151 cpu = <&cpu11>; 152 }; 153 }; 154 }; 155 }; 156 157 firmware { 158 ap_to_pm_scmi: scmi { 159 compatible = "arm,scmi"; 160 mbox-names = "tx", "rx"; 161 mboxes = <&mbox_ap2pm 8>, <&mbox_pm2ap 8>; 162 shmem = <&ap2pm_scmi_mem>, <&pm2ap_scmi_mem>; 163 #address-cells = <1>; 164 #size-cells = <0>; 165 166 scmi_clk: protocol@14 { 167 reg = <0x14>; 168 #clock-cells = <1>; 169 }; 170 }; 171 }; 172 173 pmu-a520 { 174 compatible = "arm,cortex-a520-pmu"; 175 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_partition0>; 176 }; 177 178 pmu-a720 { 179 compatible = "arm,cortex-a720-pmu"; 180 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_partition1>; 181 }; 182 183 psci { 184 compatible = "arm,psci-1.0"; 185 method = "smc"; 186 }; 187 188 soc@0 { 189 compatible = "simple-bus"; 190 ranges = <0 0 0 0 0x20 0>; 191 dma-ranges; 192 #address-cells = <2>; 193 #size-cells = <2>; 194 195 uart0: serial@40b0000 { 196 compatible = "arm,pl011", "arm,primecell"; 197 reg = <0x0 0x040b0000 0x0 0x1000>; 198 interrupts = <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH 0>; 199 clocks = <&scmi_clk CLK_TREE_FCH_UART0_FUNC>, <&scmi_clk CLK_TREE_FCH_UART0_APB>; 200 clock-names = "uartclk", "apb_pclk"; 201 status = "disabled"; 202 }; 203 204 uart1: serial@40c0000 { 205 compatible = "arm,pl011", "arm,primecell"; 206 reg = <0x0 0x040c0000 0x0 0x1000>; 207 interrupts = <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH 0>; 208 clocks = <&scmi_clk CLK_TREE_FCH_UART1_FUNC>, <&scmi_clk CLK_TREE_FCH_UART1_APB>; 209 clock-names = "uartclk", "apb_pclk"; 210 status = "disabled"; 211 }; 212 213 uart2: serial@40d0000 { 214 compatible = "arm,pl011", "arm,primecell"; 215 reg = <0x0 0x040d0000 0x0 0x1000>; 216 interrupts = <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH 0>; 217 clocks = <&scmi_clk CLK_TREE_FCH_UART2_FUNC>, <&scmi_clk CLK_TREE_FCH_UART2_APB>; 218 clock-names = "uartclk", "apb_pclk"; 219 status = "disabled"; 220 }; 221 222 uart3: serial@40e0000 { 223 compatible = "arm,pl011", "arm,primecell"; 224 reg = <0x0 0x040e0000 0x0 0x1000>; 225 interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH 0>; 226 clocks = <&scmi_clk CLK_TREE_FCH_UART3_FUNC>, <&scmi_clk CLK_TREE_FCH_UART3_APB>; 227 clock-names = "uartclk", "apb_pclk"; 228 status = "disabled"; 229 }; 230 231 mbox_ap2se: mailbox@5060000 { 232 compatible = "cix,sky1-mbox"; 233 reg = <0x0 0x05060000 0x0 0x10000>; 234 interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH 0>; 235 #mbox-cells = <1>; 236 cix,mbox-dir = "tx"; 237 }; 238 239 mbox_se2ap: mailbox@5070000 { 240 compatible = "cix,sky1-mbox"; 241 reg = <0x0 0x05070000 0x0 0x10000>; 242 interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH 0>; 243 #mbox-cells = <1>; 244 cix,mbox-dir = "rx"; 245 }; 246 247 ap2pm_scmi_mem: shmem@6590000 { 248 compatible = "arm,scmi-shmem"; 249 reg = <0x0 0x06590000 0x0 0x80>; 250 reg-io-width = <4>; 251 }; 252 253 mbox_ap2pm: mailbox@6590080 { 254 compatible = "cix,sky1-mbox"; 255 reg = <0x0 0x06590080 0x0 0xff80>; 256 interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH 0>; 257 #mbox-cells = <1>; 258 cix,mbox-dir = "tx"; 259 }; 260 261 pm2ap_scmi_mem: shmem@65a0000 { 262 compatible = "arm,scmi-shmem"; 263 reg = <0x0 0x065a0000 0x0 0x80>; 264 reg-io-width = <4>; 265 }; 266 267 mbox_pm2ap: mailbox@65a0080 { 268 compatible = "cix,sky1-mbox"; 269 reg = <0x0 0x065a0080 0x0 0xff80>; 270 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH 0>; 271 #mbox-cells = <1>; 272 cix,mbox-dir = "rx"; 273 }; 274 275 mbox_sfh2ap: mailbox@8090000 { 276 compatible = "cix,sky1-mbox"; 277 reg = <0x0 0x08090000 0x0 0x10000>; 278 interrupts = <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH 0>; 279 #mbox-cells = <1>; 280 cix,mbox-dir = "rx"; 281 }; 282 283 mbox_ap2sfh: mailbox@80a0000 { 284 compatible = "cix,sky1-mbox"; 285 reg = <0x0 0x080a0000 0x0 0x10000>; 286 interrupts = <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH 0>; 287 #mbox-cells = <1>; 288 cix,mbox-dir = "tx"; 289 }; 290 291 gic: interrupt-controller@e010000 { 292 compatible = "arm,gic-v3"; 293 reg = <0x0 0x0e010000 0 0x10000>, /* GICD */ 294 <0x0 0x0e090000 0 0x300000>; /* GICR * 12 */ 295 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW 0>; 296 #interrupt-cells = <4>; 297 interrupt-controller; 298 #address-cells = <2>; 299 #size-cells = <2>; 300 ranges; 301 302 gic_its: msi-controller@e050000 { 303 compatible = "arm,gic-v3-its"; 304 reg = <0x0 0x0e050000 0x0 0x30000>; 305 msi-controller; 306 #msi-cells = <1>; 307 }; 308 309 ppi-partitions { 310 ppi_partition0: interrupt-partition-0 { 311 affinity = <&cpu0 &cpu1 &cpu2 &cpu3>; 312 }; 313 314 ppi_partition1: interrupt-partition-1 { 315 affinity = <&cpu4 &cpu5 &cpu6 &cpu7 &cpu8 &cpu9 &cpu10 &cpu11>; 316 }; 317 }; 318 }; 319 }; 320 321 timer { 322 compatible = "arm,armv8-timer"; 323 interrupt-names = "sec-phys", "phys", "virt", "hyp-phys", "hyp-virt"; 324 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>, 325 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>, 326 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>, 327 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>, 328 <GIC_PPI 12 IRQ_TYPE_LEVEL_LOW 0>; 329 }; 330}; 331