1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Copyright © 2022 Intel Corporation 4 */ 5 6 #ifndef __SKL_WATERMARK_H__ 7 #define __SKL_WATERMARK_H__ 8 9 #include <linux/types.h> 10 11 #include "intel_display_limits.h" 12 #include "intel_global_state.h" 13 #include "intel_wm_types.h" 14 15 struct drm_i915_private; 16 struct intel_atomic_state; 17 struct intel_bw_state; 18 struct intel_crtc; 19 struct intel_crtc_state; 20 struct intel_plane; 21 struct intel_plane_state; 22 struct skl_pipe_wm; 23 struct skl_wm_level; 24 25 u8 intel_enabled_dbuf_slices_mask(struct drm_i915_private *i915); 26 27 void intel_sagv_pre_plane_update(struct intel_atomic_state *state); 28 void intel_sagv_post_plane_update(struct intel_atomic_state *state); 29 bool intel_can_enable_sagv(struct drm_i915_private *i915, 30 const struct intel_bw_state *bw_state); 31 bool intel_has_sagv(struct drm_i915_private *i915); 32 33 u32 skl_ddb_dbuf_slice_mask(struct drm_i915_private *i915, 34 const struct skl_ddb_entry *entry); 35 36 bool skl_ddb_allocation_overlaps(const struct skl_ddb_entry *ddb, 37 const struct skl_ddb_entry *entries, 38 int num_entries, int ignore_idx); 39 40 void intel_wm_state_verify(struct intel_atomic_state *state, 41 struct intel_crtc *crtc); 42 43 void skl_watermark_ipc_init(struct drm_i915_private *i915); 44 void skl_watermark_ipc_update(struct drm_i915_private *i915); 45 bool skl_watermark_ipc_enabled(struct drm_i915_private *i915); 46 void skl_watermark_debugfs_register(struct drm_i915_private *i915); 47 48 unsigned int skl_watermark_max_latency(struct drm_i915_private *i915, 49 int initial_wm_level); 50 void skl_wm_init(struct drm_i915_private *i915); 51 52 const struct skl_wm_level *skl_plane_wm_level(const struct skl_pipe_wm *pipe_wm, 53 enum plane_id plane_id, 54 int level); 55 const struct skl_wm_level *skl_plane_trans_wm(const struct skl_pipe_wm *pipe_wm, 56 enum plane_id plane_id); 57 unsigned int skl_plane_relative_data_rate(const struct intel_crtc_state *crtc_state, 58 struct intel_plane *plane, int width, 59 int height, int cpp); 60 61 struct intel_dbuf_state { 62 struct intel_global_state base; 63 64 struct skl_ddb_entry ddb[I915_MAX_PIPES]; 65 unsigned int weight[I915_MAX_PIPES]; 66 u8 slices[I915_MAX_PIPES]; 67 u8 enabled_slices; 68 u8 active_pipes; 69 u8 mdclk_cdclk_ratio; 70 bool joined_mbus; 71 }; 72 73 struct intel_dbuf_state * 74 intel_atomic_get_dbuf_state(struct intel_atomic_state *state); 75 76 #define to_intel_dbuf_state(global_state) \ 77 container_of_const((global_state), struct intel_dbuf_state, base) 78 79 #define intel_atomic_get_old_dbuf_state(state) \ 80 to_intel_dbuf_state(intel_atomic_get_old_global_obj_state(state, &to_intel_display(state)->dbuf.obj)) 81 #define intel_atomic_get_new_dbuf_state(state) \ 82 to_intel_dbuf_state(intel_atomic_get_new_global_obj_state(state, &to_intel_display(state)->dbuf.obj)) 83 84 int intel_dbuf_init(struct drm_i915_private *i915); 85 int intel_dbuf_state_set_mdclk_cdclk_ratio(struct intel_atomic_state *state, 86 int ratio); 87 88 void intel_dbuf_pre_plane_update(struct intel_atomic_state *state); 89 void intel_dbuf_post_plane_update(struct intel_atomic_state *state); 90 void intel_dbuf_mdclk_cdclk_ratio_update(struct drm_i915_private *i915, 91 int ratio, bool joined_mbus); 92 void intel_dbuf_mbus_pre_ddb_update(struct intel_atomic_state *state); 93 void intel_dbuf_mbus_post_ddb_update(struct intel_atomic_state *state); 94 void intel_program_dpkgc_latency(struct intel_atomic_state *state); 95 96 #endif /* __SKL_WATERMARK_H__ */ 97 98